Many-core approach to 2D-DCT calculation using an FPGA

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia de Electrónica e Telecomunicações

Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication

Recent integrated circuit technologies have opened the possibility to design parallel architectures with hundreds of cores on a single chip. The design space of these parallel architectures is huge with many architectural options. Exploring the design space gets even more difficult if, beyond performance and area, we also consider extra metrics like performance and area efficiency, where the designer tries to design the architecture with the best performance per chip area and the best sustainable performance. In this paper we present an algorithm-oriented approach to design a many-core architecture. Instead of doing the design space exploration of the many core architecture based on the experimental execution results of a particular benchmark of algorithms, our approach is to make a formal analysis of the algorithms considering the main architectural aspects and to determine how each particular architectural aspect is related to the performance of the architecture when running an algorithm or set of algorithms. The architectural aspects considered include the number of cores, the local memory available in each core, the communication bandwidth between the many-core architecture and the external memory and the memory hierarchy. To exemplify the approach we did a theoretical analysis of a dense matrix multiplication algorithm and determined an equation that relates the number of execution cycles with the architectural parameters. Based on this equation a many-core architecture has been designed. The results obtained indicate that a 100 mm(2) integrated circuit design of the proposed architecture, using a 65 nm technology, is able to achieve 464 GFLOPs (double precision floating-point) for a memory bandwidth of 16 GB/s. This corresponds to a performance efficiency of 71 %. Considering a 45 nm technology, a 100 mm(2) chip attains 833 GFLOPs which corresponds to 84 % of peak performance These figures are better than those obtained by previous many-core architectures, except for the area efficiency which is limited by the lower memory bandwidth considered. The results achieved are also better than those of previous state-of-the-art many-cores architectures designed specifically to achieve high performance for matrix multiplication.

A many-core co-processor for embedded parallel computing on FPGA

Single processor architectures are unable to provide the required performance of high performance embedded systems. Parallel processing based on general-purpose processors can achieve these performances with a considerable increase of required resources. However, in many cases, simplified optimized parallel cores can be used instead of general-purpose processors achieving better performance at lower resource utilization. In this paper, we propose a configurable many-core architecture to serve as a co-processor for high-performance embedded computing on Field-Programmable Gate Arrays. The architecture consists of an array of configurable simple cores with support for floating-point operations interconnected with a configurable interconnection network. For each core it is possible to configure the size of the internal memory, the supported operations and number of interfacing ports. The architecture was tested in a ZYNQ-7020 FPGA in the execution of several parallel algorithms. The results show that the proposed many-core architecture achieves better performance than that achieved with a parallel generalpurpose processor and that up to 32 floating-point cores can be implemented in a ZYNQ-7020 SoC FPGA.

Sparse matrix multiplication on a reconfigurable many-core architecture

Sparse matrix-vector multiplication (SMVM) is a fundamental operation in many scientific and engineering applications. In many cases sparse matrices have thousands of rows and columns where most of the entries are zero, while non-zero data is spread over the matrix. This sparsity of data locality reduces the effectiveness of data cache in general-purpose processors quite reducing their performance efficiency when compared to what is achieved with dense matrix multiplication. In this paper, we propose a parallel processing solution for SMVM in a many-core architecture. The architecture is tested with known benchmarks using a ZYNQ-7020 FPGA. The architecture is scalable in the number of core elements and limited only by the available memory bandwidth. It achieves performance efficiencies up to almost 70% and better performances than previous FPGA designs.

A framework for memory contention analysis in multi-core platforms

The last decade has witnessed a major shift towards the deployment of embedded applications on multi-core platforms. However, real-time applications have not been able to fully benefit from this transition, as the computational gains offered by multi-cores are often offset by performance degradation due to shared resources, such as main memory. To efficiently use multi-core platforms for real-time systems, it is hence essential to tightly bound the interference when accessing shared resources. Although there has been much recent work in this area, a remaining key problem is to address the diversity of memory arbiters in the analysis to make it applicable to a wide range of systems. This work handles diverse arbiters by proposing a general framework to compute the maximum interference caused by the shared memory bus and its impact on the execution time of the tasks running on the cores, considering different bus arbiters. Our novel approach clearly demarcates the arbiter-dependent and independent stages in the analysis of these upper bounds. The arbiter-dependent phase takes the arbiter and the task memory-traffic pattern as inputs and produces a model of the availability of the bus to a given task. Then, based on the availability of the bus, the arbiter-independent phase determines the worst-case request-release scenario that maximizes the interference experienced by the tasks due to the contention for the bus. We show that the framework addresses the diversity problem by applying it to a memory bus shared by a fixed-priority arbiter, a time-division multiplexing (TDM) arbiter, and an unspecified work-conserving arbiter using applications from the MediaBench test suite. We also experimentally evaluate the quality of the analysis by comparison with a state-of-the-art TDM analysis approach and consistently showing a considerable reduction in maximum interference.

Hard real-time multiprocessor scheduling resilient to core failures

Presented at 21st IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2015). 19 to 21, Aug, 2015, pp 122-131. Hong Kong, China.

Parallel Software framework for time-critical many-core systems

The recent technological advancements and market trends are causing an interesting phenomenon towards the convergence of High-Performance Computing (HPC) and Embedded Computing (EC) domains. On one side, new kinds of HPC applications are being required by markets needing huge amounts of information to be processed within a bounded amount of time. On the other side, EC systems are increasingly concerned with providing higher performance in real-time, challenging the performance capabilities of current architectures. The advent of next-generation many-core embedded platforms has the chance of intercepting this converging need for predictable high-performance, allowing HPC and EC applications to be executed on efficient and powerful heterogeneous architectures integrating general-purpose processors with many-core computing fabrics. To this end, it is of paramount importance to develop new techniques for exploiting the massively parallel computation capabilities of such platforms in a predictable way. P-SOCRATES will tackle this important challenge by merging leading research groups from the HPC and EC communities. The time-criticality and parallelisation challenges common to both areas will be addressed by proposing an integrated framework for executing workload-intensive applications with real-time requirements on top of next-generation commercial-off-the-shelf (COTS) platforms based on many-core accelerated architectures. The project will investigate new HPC techniques that fulfil real-time requirements. The main sources of indeterminism will be identified, proposing efficient mapping and scheduling algorithms, along with the associated timing and schedulability analysis, to guarantee the real-time and performance requirements of the applications.

Influência de um programa de treino da musculatura do core em jogadoras ado-lescentes de voleibol

Introdução: Apesar de na reabilitação e nas atividades da vida diária já se perceber que o treino do core tem bastantes benefícios, no desporto ainda não há provas conclusivas deste mesmo benefício e de como o treino do core deve ser elaborado. Objectivo(s): Avaliar a eficácia de um programa de intervenção sobre a musculatura do core em jogadoras de voleibol Métodos: O presente estudo quasi experimental longitudinal teve uma amostra final de 56 indivíduos – grupo controlo (GC) (n= 27), e grupo experimental (GE) (n=29). Avaliou-se os testes de endurance, e respectivos rácios, descritos por McGill. Ambos os grupos foram avaliados antes (Momento 0) e após (Momento 1) a aplicação de um programa de intervenção. Resultados: Na análise entre os 2 grupos, tanto no Momento 0 como no Momento 1, não se registou diferenças estatisticamente significativas, nem nas médias de tempo dos testes de McGill nem nos rácios. Já na análise intragrupo, o GC não apresentou resultados estatisti-camente significativos, nem nas médias de tempo dos testes do McGill nem nos rácios, enquanto o GE apenas apresentou valores estatisticamente significativos nas médias de tempo da prancha lateral direita (p = 0,04) e prancha lateral esquerda (p = 0,03). Conclusão: Atletas jovens e do sexo feminino, apresentaram um fraco de-sempenho da musculatura extensora do tronco que as torna mais passíveis de contrair lesões lumbopélvicas. Será necessário implementar um programa de intervenção, diferente do aplicado neste estudo, e com maior ênfase na musculatura extensora para equilibrar os rácios propostos por McGill, e assim, diminuir o risco de lesão.

Dominant and Recessive RYR1 Mutations in Adults with Core Lesions and Mild Muscle Symptoms

INTRODUCTION: Ryanodine receptor gene (RYR1) mutations have been associated with central core disease (CCD), multiminicore/minicore/multicore disease (MmD), and susceptibility to malignant hyperthermia (MH). METHODS: Patients with muscle symptoms in adulthood, who had features compatible with CCD/MmD, underwent clinical, histological, and genetic (RYR1 and SEPN1 genes) evaluations. Published cases of CCD and MmD with adult onset were also reviewed. RESULTS: Eight patients fulfilled the criteria for further analysis. Five RYR1 mutations, 4 of them unreported, were detected in 3 patients. Compound heterozygosity was proven in 1 case. CONCLUSIONS: To our knowledge, this is the only report of adult onset associated with recessive RYR1 mutations and central core/multiminicores on muscle biopsy. Although adult patients with CCD, MmD, and minimally symptomatic MH with abnormal muscle biopsy findings usually have a mild clinical course, differential diagnosis and carrier screening is crucial for prevention of potentially life-threatening reactions to general anesthesia.

Brotherly love and filial obedience: the commemorative programme of the Avis princes at Santa Maria da Vitória, Batalha

This dissertation focuses on a rare 15th century commemorative programme that has thus far received little scholarly attention: the collective monument erected in the Founder’s Chapel, at the Monastery of Santa Maria da Vitória, Batalha, to house the remains of four Avis princes, members of what would become known as ‘the Illustrious Generation’. A patron is proposed for the commission of this erudite monument - the princes’ eldest brother, king Duarte I - arguing its integration into a broader propaganda programme to glorify the memory of the Avis dynasty founder, king João I. The dissertation then proceeds to discuss various highly innovative features of the monument, such as its pseudo-architectural character, its use of sophisticated heraldry and personal badges, the apparent absence of religious iconography on the tombs and, importantly, the collective nature of the programme, key to its interpretation. Using a semiotic approach, a discussion is also offered on the way the various formal, iconographic and conceptual novelties of the princes’ monument impacted on the 15th century monumental landscape in Portugal. Finally, the monument and the chapel housing it are looked at through the prism of the various readings that successive generations of viewers have projected onto it, from the time of its creation to the turn of the 20th century, in order to offer a more comprehensive understanding of the object as it stands today.

Investing beyond the core: The case of Soares da Costa

This study aims to analyze how Grupo Soares da Costa, a diversified group centered on construction, behaved in terms of strategy to the current crisis. More specifically, it purposes to understand why Soares da Costa was forced to abandon its strategic plan “Ambições Renovadas”, which was about diversification and internationalization, to decide to focus on it core business. This study uses a SWOT analysis, the examination of the strategic plans and annual reports and the conclusions of two interviews that were carried out. Being the construction sector such a traditional and significant sector to the Portuguese economy, it is important to understand what a company can do to overcome such circumstances. To deal with all the negative circumstances, Soares da Costa should give priority to projects that require low levels of initial capital and diversify geographically to markets with similar characteristics of Angola and Mozambique, where Soares da Costa already excels.

Implementation of Multi-Core Processor Based on PLASMA (Most MIPS I) IP Core

Multi-core processors is a design philosophy that has become mainstream in scientific and engineering applications. Increasing performance and gate capacity of recent FPGA devices has permitted complex logic systems to be implemented on a single programmable device. By using VHDL here we present an implementation of one multi-core processor by using the PLASMA IP core based on the (most) MIPS I ISA and give an overview of the processor architecture and share theexecution results.

The fusion protein SS18-SSX1 employs core Wnt pathway transcription factors to induce a partial Wnt signature in synovial sarcoma.

Expression of the SS18/SYT-SSX fusion protein is believed to underlie the pathogenesis of synovial sarcoma (SS). Recent evidence suggests that deregulation of the Wnt pathway may play an important role in SS but the mechanisms whereby SS18-SSX might affect Wnt signaling remain to be elucidated. Here, we show that SS18/SSX tightly regulates the elevated expression of the key Wnt target AXIN2 in primary SS. SS18-SSX is shown to interact with TCF/LEF, TLE and HDAC but not β-catenin in vivo and to induce Wnt target gene expression by forming a complex containing promoter-bound TCF/LEF and HDAC but lacking β-catenin. Our observations provide a tumor-specific mechanistic basis for Wnt target gene induction in SS that can occur in the absence of Wnt ligand stimulation.

Recueil de portraits des roys et reynes de France, des princes, princesses, seigneurs et dames, et des personnes de toutes sortes de professions, dessinez à la main ou peints en miniature, et pris sur des monumens qui font connoistre les differens habillemens de chaque regne. T. I, Clovis - Saint-Louis

Collectionneur : Gaignières, Roger de (1642-1715)

11/3/20, Parc des Princes, M. Deschanel assiste au match [de rugby] armée française contre armée anglaise [vue sur la tribune] : [photographie de presse] / [Agence Rol]

Référence bibliographique : Rol, 58448