Probing Individual Quantum Dots: Noise in Self-Assembled Systems

In this work we explore the noise characteristics in lithographically-defined two terminal devices containing self-assembled InAs/InP quantum dots. The experimental ensemble of InAs dots show random telegraph noise (RTN) with tuneable relative amplitude-up to 150%-in well defined temperature and source-drain applied voltage ranges. Our numerical simulation indicates that the RTN signature correlates with a very low number of quantum dots acting as effective charge storage centres in the structure for a given applied voltage. The modulation in relative amplitude variation can thus be associated to the altered electrostatic potential profile around such centres and enhanced carrier scattering provided by a charged dot.

Cryogenic operation of FinFETs aiming at analog applications

FinFETs are recognized as promising candidates for the CMOS nanometer era. In this paper the most recent results for cryogenic operation of FinFETs will be demonstrated with special emphasis on analog applications. Threshold voltage, subthreshold slope and carrier mobility will be studied. Also some important figures of merit for analog circuit operation as for readout electronics, such as transconductance, output conductance and intrinsic voltage gain will be covered. It is demonstrated that the threshold voltage of undoped narrow FinFETs is less temperature-dependent than for a planar single-gate device with similar doping concentration. The temperature reduction improves the transconductance over drain current ratio in any operational region. On the other hand, the output conductance is degraded when the temperature is reduced. The combination of these effects shows that the intrinsic gain of a L = 90 nm FinFET is degraded by 2 dB when the temperature reduces from 300 K to 100 K. (C) 2009 Elsevier Ltd. All rights reserved.

Study of reactive sputtering titanium oxide for metal-oxide-semiconductor capacitors

Metal oxide semiconductor (MOS) capacitors with titanium oxide (TiO(x)) dielectric layer, deposited with different oxygen partial pressure (30,35 and 40%) and annealed at 550, 750 and 1000 degrees C, were fabricated and characterized. Capacitance-voltage and current-voltage measurements were utilized to obtain, the effective dielectric constant, effective oxide thickness, leakage current density and interface quality. The obtained TiO(x) films present a dielectric constant varying from 40 to 170 and a leakage current density, for a gate voltage of - 1 V, as low as 1 nA/cm(2) for some of the structures, acceptable for MOS fabrication, indicating that this material is a viable high dielectric constant substitute for current ultra thin dielectric layers. (C) 2009 Elsevier B.V. All rights reserved.

Low-temperature deposition of silicon oxide and silicon nitride by reactive magnetron sputtering

In this study, oxide and nitride films were deposited at room temperature through the reaction of silicon Sputtered by argon and oxygen ions or argon and nitrogen ions at 250 and 350 W with 0.67 Pa pressure. It was observed that for both thin films the deposition rates increase with the applied RF power and decrease with the increase of the gas concentration. The Si/O and Si/N ratio were obtained through RBS analyses and for silicon oxide the values changed from 0.42 to 0.57 and for silicon nitride the Values changed from 0.4 to 1.03. The dielectric constants were calculated through capacitance-voltage curves with the silicon oxide values varying from 2.4 to 5.5, and silicon nitride values varying from 6.2 to 6.7, which are good options for microelectronic dielectrics. (c) 2008 Elsevier Ltd. All rights reserved.

Influence of the sidewall crystal orientation, HfSiO nitridation and TiN metal gate thickness on n-MuGFETs under analog operation

This work characterizes the analog performance of SOI n-MuGFETs with HfSiO gate dielectric and TiN metal gate with respect to the influence of the high-k post-nitridation. TiN thickness and device rotation. A thinner TiN metal gate is found favorable for improved analog characteristics showing an increase in intrinsic voltage gain. The devices where the high-k material is subjected to a nitridation step indicated a degradation of the Early voltage (V(EA)) values which resulted in a lower voltage gain. The 45 degrees rotated devices have a smaller V(EA) than the standard ones when a HfSiO dielectric is used. However, the higher transconductance of these devices, due to the increased mobility in the (1 0 0) sidewall orientation, compensates this V(EA) degradation of the voltage gain, keeping it nearly equal to the voltage gain values of the standard devices. (C) 2011 Elsevier Ltd. All rights reserved.

Threshold voltages of SOI MuGFETs

The multiple-gate field-effect transistor (MuGFET) is a device with a gate folded on different sides of the channel region. They are one of the most promising technological solutions to create high-performance ultra-scaled SOI CMOS. In this work, the behavior of the threshold voltage in double-gate, triple-gate and quadruple-gate SOI transistors with different channel doping concentrations is studied through three-dimensional numerical simulation. The results indicated that for double-gate transistors, one or two threshold voltages can be observed, depending on the channel doping concentration. However, in triple-gate and quadruple-gate it is possible to observe up to four threshold voltages due to the corner effect and the different doping concentration between the top and bottom of the Fin. (C) 2008 Elsevier Ltd. All rights reserved.

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

This work shows a comparison between the analog performance of standard and strained Si n-type triple-gate FinFETs with high-K dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is demonstrated that both standard and strained FinFETs with short channel length and narrow fins have similar analog properties, whereas the increase of the channel length degrades the early voltage of the strained devices, consequently decreasing the device intrinsic voltage gain with respect to standard ones. Narrow strained FinFETs with long channel show a degradation of the Early voltage if compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect. (C) 2008 Elsevier Ltd. All rights reserved.

Temperature influence on the gate-induced floating body effect parameters in fully depleted SOI nMOSFETs

The temperature influence on the gate-induced floating body effect (GIFBE) in fully depleted (FD) silicon-on-insulator (SOI) nMOSFETs is investigated, based on experimental results and two-dimensional numerical simulations. The GIFBE behavior will be evaluated taking into account the impact of carrier recombination and of the effective electric field mobility degradation on the second peak in the transconductance (gm). This floating body effect is also analyzed as a function of temperature. It is shown that the variation of the studied parameters with temperature results in a ""C"" shape of the threshold voltage corresponding with the second peak in the gm curve. (C) 2008 Elsevier Ltd. All rights reserved.

Harmonic distortion of 2-MOS structures for MOSFET-C filters implemented with n-type unstrained and strained FINFETS

This work investigates the harmonic distortion (HD) in 2-MOS balanced structures composed of triple gate FinFETs. HD has been evaluated through the determination of the third-order harmonic distortion (HD3), since this represents the major non-linearity source in balanced structures. The 2-MOS structures with devices of different channel lengths (L) and fin widths (W(fin)) have been studied operating in the linear region as tunable resistors. The analysis was performed as a function of the gate voltage, aiming to verify the correlation between operation bias and HD3. The physical origins of the non-linearities have been investigated and are pointed out. Being a resistive circuit, the 2-MOS structure is generally projected for a targeted on-resistance, which has also been evaluated in terms of HD3. The impact of the application of biaxial strain has been studied for FinFETs of different dimensions. It has been noted that HD3 reduces with the increase of the gate bias for all the devices and this reduction is more pronounced both in narrower and in longer devices. Also, the presence of strain slightly diminishes the non-linearity at a similar bias. However, a drawback associated with the use of strain engineering consists in a significant reduction of the on-resistance with respect to unstrained devices. (C) 2011 Elsevier Ltd. All rights reserved.

Improving the tracking capability of adaptive filters via convex combination

As is well known, Hessian-based adaptive filters (such as the recursive-least squares algorithm (RLS) for supervised adaptive filtering, or the Shalvi-Weinstein algorithm (SWA) for blind equalization) converge much faster than gradient-based algorithms [such as the least-mean-squares algorithm (LMS) or the constant-modulus algorithm (CMA)]. However, when the problem is tracking a time-variant filter, the issue is not so clear-cut: there are environments for which each family presents better performance. Given this, we propose the use of a convex combination of algorithms of different families to obtain an algorithm with superior tracking capability. We show the potential of this combination and provide a unified theoretical model for the steady-state excess mean-square error for convex combinations of gradient- and Hessian-based algorithms, assuming a random-walk model for the parameter variations. The proposed model is valid for algorithms of the same or different families, and for supervised (LMS and RLS) or blind (CMA and SWA) algorithms.

A Class of Channels Resulting in Ill-Convergence for CMA in Decision Feedback Equalizers

This paper analyzes the convergence of the constant modulus algorithm (CMA) in a decision feedback equalizer using only a feedback filter. Several works had already observed that the CMA presented a better performance than decision directed algorithm in the adaptation of the decision feedback equalizer, but theoretical analysis always showed to be difficult specially due to the analytical difficulties presented by the constant modulus criterion. In this paper, we surmount such obstacle by using a recent result concerning the CM analysis, first obtained in a linear finite impulse response context with the objective of comparing its solutions to the ones obtained through the Wiener criterion. The theoretical analysis presented here confirms the robustness of the CMA when applied to the adaptation of the decision feedback equalizer and also defines a class of channels for which the algorithm will suffer from ill-convergence when initialized at the origin.

Network of phase-locking oscillators and a possible model for neural synchronization

In order to model the synchronization of brain signals, a three-node fully-connected network is presented. The nodes are considered to be voltage control oscillator neurons (VCON) allowing to conjecture about how the whole process depends on synaptic gains, free-running frequencies and delays. The VCON, represented by phase-locked loops (PLL), are fully-connected and, as a consequence, an asymptotically stable synchronous state appears. Here, an expression for the synchronous state frequency is derived and the parameter dependence of its stability is discussed. Numerical simulations are performed providing conditions for the use of the derived formulae. Model differential equations are hard to be analytically treated, but some simplifying assumptions combined with simulations provide an alternative formulation for the long-term behavior of the fully-connected VCON network. Regarding this kind of network as models for brain frequency signal processing, with each PLL representing a neuron (VCON), conditions for their synchronization are proposed, considering the different bands of brain activity signals and relating them to synaptic gains, delays and free-running frequencies. For the delta waves, the synchronous state depends strongly on the delays. However, for alpha, beta and theta waves, the free-running individual frequencies determine the synchronous state. (C) 2011 Elsevier B.V. All rights reserved.

Avoiding Divergence in the Shalvi-Weinstein Algorithm

The most popular algorithms for blind equalization are the constant-modulus algorithm (CMA) and the Shalvi-Weinstein algorithm (SWA). It is well-known that SWA presents a higher convergence rate than CMA. at the expense of higher computational complexity. If the forgetting factor is not sufficiently close to one, if the initialization is distant from the optimal solution, or if the signal-to-noise ratio is low, SWA can converge to undesirable local minima or even diverge. In this paper, we show that divergence can be caused by an inconsistency in the nonlinear estimate of the transmitted signal. or (when the algorithm is implemented in finite precision) by the loss of positiveness of the estimate of the autocorrelation matrix, or by a combination of both. In order to avoid the first cause of divergence, we propose a dual-mode SWA. In the first mode of operation. the new algorithm works as SWA; in the second mode, it rejects inconsistent estimates of the transmitted signal. Assuming the persistence of excitation condition, we present a deterministic stability analysis of the new algorithm. To avoid the second cause of divergence, we propose a dual-mode lattice SWA, which is stable even in finite-precision arithmetic, and has a computational complexity that increases linearly with the number of adjustable equalizer coefficients. The good performance of the proposed algorithms is confirmed through numerical simulations.

Cryogenic Operation of Junctionless Nanowire Transistors

This letter presents the properties of nMOS junctionless nanowire transistors (JNTs) under cryogenic operation. Experimental results of drain current, subthreshold slope, maximum transconductance at low electric field, and threshold voltage, as well as its variation with temperature, are presented. Unlike in classical devices, the drain current of JNTs decreases when temperature is lowered, although the maximum transconductance increases when the temperature is lowered down to 125 K. An analytical model for the threshold voltage is proposed to explain the influence of nanowire width and doping concentration on its variation with temperature. It is shown that the wider the nanowire or the lower the doping concentration, the higher the threshold voltage variation with temperature.

Thin titanium oxide films deposited by e-beam evaporation with additional rapid thermal oxidation and annealing for ISFET applications

Titanium oxide (TiO(2)) has been extensively applied in the medical area due to its proved biocompatibility with human cells [1]. This work presents the characterization of titanium oxide thin films as a potential dielectric to be applied in ion sensitive field-effect transistors. The films were obtained by rapid thermal oxidation and annealing (at 300, 600, 960 and 1200 degrees C) of thin titanium films of different thicknesses (5 nm, 10 nm and 20 nm) deposited by e-beam evaporation on silicon wafers. These films were analyzed as-deposited and after annealing in forming gas for 25 min by Ellipsometry, Fourier Transform Infrared Spectroscopy (FTIR), Raman Spectroscopy (RAMAN), Atomic Force Microscopy (AFM), Rutherford Backscattering Spectroscopy (RBS) and Ti-K edge X-ray Absorption Near Edge Structure (XANES). Thin film thickness, roughness, surface grain sizes, refractive indexes and oxygen concentration depend on the oxidation and annealing temperature. Structural characterization showed mainly presence of the crystalline rutile phase, however, other oxides such Ti(2)O(3), an interfacial SiO(2) layer between the dielectric and the substrate and the anatase crystalline phase of TiO(2) films were also identified. Electrical characteristics were obtained by means of I-V and C-V measured curves of Al/Si/TiO(x)/Al capacitors. These curves showed that the films had high dielectric constants between 12 and 33, interface charge density of about 10(10)/cm(2) and leakage current density between 1 and 10(-4) A/cm(2). Field-effect transistors were fabricated in order to analyze I(D) x V(DS) and log I(D) x Bias curves. Early voltage value of -1629 V, R(OUT) value of 215 M Omega and slope of 100 mV/dec were determined for the 20 nm TiO(x) film thermally treated at 960 degrees C. (C) 2009 Elsevier B.V. All rights reserved.