A Compiler Integrated Assistance for Optimum Data Allocation in Banked Memory Embedded Processors

Bank switching in embedded processors having partitioned memory architecture results in code size as well as run time overhead. An algorithm and its application to assist the compiler in eliminating the redundant bank switching codes introduced and deciding the optimum data allocation to banked memory is presented in this work. A relation matrix formed for the memory bank state transition corresponding to each bank selection instruction is used for the detection of redundant codes. Data allocation to memory is done by considering all possible permutation of memory banks and combination of data. The compiler output corresponding to each data mapping scheme is subjected to a static machine code analysis which identifies the one with minimum number of bank switching codes. Even though the method is compiler independent, the algorithm utilizes certain architectural features of the target processor. A prototype based on PIC 16F87X microcontrollers is described. This method scales well into larger number of memory blocks and other architectures so that high performance compilers can integrate this technique for efficient code generation. The technique is illustrated with an example

Test for basis-set errors in relativistic Dirac-Fock-Slater calculations with a numerical AO-DFS-basis

A fully relativistic four-component Dirac-Fock-Slater program for diatomics, with numerically given AO's as basis functions is presented. We discuss the problem of the errors due to the finite basis-set, and due to the influence of the negative energy solutions of the Dirac Hamiltonian. The negative continuum contributions are found to be very small.

Learning Commonsense Categorical Knowledge in a Thread Memory System

If we are to understand how we can build machines capable of broad purpose learning and reasoning, we must first aim to build systems that can represent, acquire, and reason about the kinds of commonsense knowledge that we humans have about the world. This endeavor suggests steps such as identifying the kinds of knowledge people commonly have about the world, constructing suitable knowledge representations, and exploring the mechanisms that people use to make judgments about the everyday world. In this work, I contribute to these goals by proposing an architecture for a system that can learn commonsense knowledge about the properties and behavior of objects in the world. The architecture described here augments previous machine learning systems in four ways: (1) it relies on a seven dimensional notion of context, built from information recently given to the system, to learn and reason about objects' properties; (2) it has multiple methods that it can use to reason about objects, so that when one method fails, it can fall back on others; (3) it illustrates the usefulness of reasoning about objects by thinking about their similarity to other, better known objects, and by inferring properties of objects from the categories that they belong to; and (4) it represents an attempt to build an autonomous learner and reasoner, that sets its own goals for learning about the world and deduces new facts by reflecting on its acquired knowledge. This thesis describes this architecture, as well as a first implementation, that can learn from sentences such as ``A blue bird flew to the tree'' and ``The small bird flew to the cage'' that birds can fly. One of the main contributions of this work lies in suggesting a further set of salient ideas about how we can build broader purpose commonsense artificial learners and reasoners.

Fast Sorting on a Distributed-Memory Architecture

We consider the often-studied problem of sorting, for a parallel computer. Given an input array distributed evenly over p processors, the task is to compute the sorted output array, also distributed over the p processors. Many existing algorithms take the approach of approximately load-balancing the output, leaving each processor with Θ(n/p) elements. However, in many cases, approximate load-balancing leads to inefficiencies in both the sorting itself and in further uses of the data after sorting. We provide a deterministic parallel sorting algorithm that uses parallel selection to produce any output distribution exactly, particularly one that is perfectly load-balanced. Furthermore, when using a comparison sort, this algorithm is 1-optimal in both computation and communication. We provide an empirical study that illustrates the efficiency of exact data splitting, and shows an improvement over two sample sort algorithms.

Memory Hierarchy Hardware-Software Co-design in Embedded Systems

The memory hierarchy is the main bottleneck in modern computer systems as the gap between the speed of the processor and the memory continues to grow larger. The situation in embedded systems is even worse. The memory hierarchy consumes a large amount of chip area and energy, which are precious resources in embedded systems. Moreover, embedded systems have multiple design objectives such as performance, energy consumption, and area, etc. Customizing the memory hierarchy for specific applications is a very important way to take full advantage of limited resources to maximize the performance. However, the traditional custom memory hierarchy design methodologies are phase-ordered. They separate the application optimization from the memory hierarchy architecture design, which tend to result in local-optimal solutions. In traditional Hardware-Software co-design methodologies, much of the work has focused on utilizing reconfigurable logic to partition the computation. However, utilizing reconfigurable logic to perform the memory hierarchy design is seldom addressed. In this paper, we propose a new framework for designing memory hierarchy for embedded systems. The framework will take advantage of the flexible reconfigurable logic to customize the memory hierarchy for specific applications. It combines the application optimization and memory hierarchy design together to obtain a global-optimal solution. Using the framework, we performed a case study to design a new software-controlled instruction memory that showed promising potential.

Memory Usage Inference for Object-Oriented Programs

We present a type-based approach to statically derive symbolic closed-form formulae that characterize the bounds of heap memory usages of programs written in object-oriented languages. Given a program with size and alias annotations, our inference system will compute the amount of memory required by the methods to execute successfully as well as the amount of memory released when methods return. The obtained analysis results are useful for networked devices with limited computational resources as well as embedded software.

Sexual orientation and spatial memory

Resumen tomado de la publicaci??n

El papel de la memoria de trabajo en el cálculo mental un cuarto de siglo después de Hitch = The role of working memory in mental arithmetic a quarter of century after Hitch

Desde que Hitch (1978) publicó el primer estudio sobre el rol de la memoria de trabajo en el cálculo han ido aumentando las investigaciones en este campo. Muchos trabajos han estudiado un único subsistema, pero nuestro objetivo es identificar qué subsistema de la memoria de trabajo (bucle fonológico, agenda viso-espacial o ejecutivo central) está más implicado en el cálculo mental. Para ello hemos realizado un estudio correlacional en el que hemos administrado dos pruebas aritméticas y nueve pruebas de la “Bateria de Test de Memòria de Treball” de Pickering, Baqués y Gathercole (1999) a una muestra de 94 niños españoles de 7-8 años. Nuestros resultados indican que el bucle fonológico y sobretodo el ejecutivo central inciden de forma estadísticamente significativa en el rendimiento aritmético

Short-term storage and mental speed account for the relationship between working memory and fluid intelligence. 'El almacenamiento a corto plazo y la velocidad mental dan cuenta de la relaci??n entre memoria de trabajo e inteligencia fluida'

Resumen tomado de la publicaci??n

Executive function and memory in patients with relapsing-remitting multiple sclerosis. 'Funci??n ejecutiva y memoria en pacientes con esclerosis m??ltiple recurrente-remitente'

Resumen tomado de la publicaci??n

Effects of memory load on visual search

Resumen tomado de la publicaci??n

Memory, revision and exam techniques

University of Southampton, Dyslexia Services have developed a range of academic study skills resources available to download. This resource supports revision and techniques for use in examinations.

IRP Poster - Side-effects in Software Transactional Memory

Poster for IRP project 'Side-effects in Software Transactional Memory: Extending Deuce with TwilightSTM'

Alteración de la atención y concentración en estudiantes de medicina que realizan turnos de noche

El sueño, es indispensable para la recuperación, física, mental y de procesos como la consolidación de memoria, atención y lenguaje. La privación de sueño (PS) incide en la atención y concentración. La PS es inherente a la formación médica, pero no es claro el papel de los turnos nocturnos en estudiantes, porque no cumplen con un objetivo académico, pero hay relación con disminución de la salud, productividad, accidentes, y alteraciones en diversas actividades. Está descrito el impacto de la PS sobre la capacidad de aprendizaje y aspectos como el ánimo y las relaciones interpersonales. MÉTODOS: Se realizó un estudio analítico observacional de cohorte longitudinal, con tres etapas de medición a 180 estudiantes de Medicina de la Universidad del Rosario, que evaluó atención selectiva y concentración mediante la aplicación de la prueba d2, validada internacionalmente para tal fin. RESULTADOS: Se estudiaron 180 estudiantes, 115 mujeres, 65 hombres, entre los 18 y 26 años (promedio 21). Al inicio del estudio dormían en promedio 7,9 horas, cifra que se redujo a 5,8 y 6,3 en la segunda y tercera etapa respectivamente. El promedio de horas de sueño nocturno, disminuyó en el segundo y tercer momento (p<0,001); Además se encontró mediante la aplicación de la prueba d2, que hubo correlación significativa directa débil, entre el promedio de horas de sueño, y el promedio del desempeño en la prueba (r=0.168, p=0.029) CONCLUSIONES: La PS, con períodos de sueño menores a 7,2 horas, impactan de manera importante la atención selectiva, la concentración