Disturbance attenuation in linear systems via dynamical compensators: A parametric eigenstructure assignment approach

A simple approach is proposed for disturbance attenuation in multivariable linear systems via dynamical output compensators based on complete parametric eigenstructure assignment. The basic idea is to minimise the H-2 norm of the disturbance-output transfer function using the design freedom provided by eigenstructure assignment. For robustness, the closed-loop system is restricted to be nondefective. Besides the design parameters, the closed-loop eigenvalues are also optimised within desired regions on the left-half complex plane to ensure both closed-loop stability and dynamical performance. With the proposed approach, additional closed-loop specifications can be easily achieved. As a demonstration, robust pole assignment, in the sense that the closed-loop eigenvalues are as insensitive as possible to open-loop system parameter perturbations, is treated. Application of the proposed approach to robust control of a magnetic bearing with a pair of opposing electromagnets and a rigid rotor is discussed.

FMRFamide-like peptides (FLPs) enhance voltage-gated calcium currents to elicit muscle contraction in the human parasite Schistosoma mansoni.

Schistosomes are amongst the most important and neglected pathogens in the world, and schistosomiasis control relies almost exclusively on a single drug. The neuromuscular system of schistosomes is fertile ground for therapeutic intervention, yet the details of physiological events involved in neuromuscular function remain largely unknown. Short amidated neuropeptides, FMRFamide-like peptides (FLPs), are distributed abundantly throughout the nervous system of every flatworm examined and they produce potent myoexcitation. Our goal here was to determine the mechanism by which FLPs elicit contractions of schistosome muscle fibers. Contraction studies showed that the FLP Tyr-Ile-Arg-Phe-amide (YIRFamide) contracts the muscle fibers through a mechanism that requires Ca2+ influx through sarcolemmal voltage operated Ca2+ channels (VOCCs), as the contractions are inhibited by classical VOCC blockers nicardipine, verapamil and methoxyverapamil. Whole-cell patch-clamp experiments revealed that inward currents through VOCCs are significantly and reversibly enhanced by the application of 1 µM YIRFamide; the sustained inward currents were increased to 190% of controls and the peak currents were increased to 180%. In order to examine the biochemical link between the FLP receptor and the VOCCs, PKC inhibitors calphostin C, RO 31–8220 and chelerythrine were tested and all produced concentration dependent block of the contractions elicited by 1 µM YIRFamide. Taken together, the data show that FLPs elicit contractions by enhancing Ca2+ influx through VOCC currents using a PKC-dependent pathway.

How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications?

In the present work, by investigating the influence of source/drain (S/D) extension region engineering (also known as gate-underlap architecture) in planar Double Gate (DG) SOI MOSFETs, we offer new design insights to achieve high tolerance to gate misalignment/oversize in nanoscale devices for ultra-low-voltage (ULV) analog/rf applications. Our results show that (i) misaligned gate-underlap devices perform significantly better than DC devices with abrupt source/drain junctions with identical misalignment, (ii) misaligned gate underlap performance (with S/D optimization) exceeds perfectly aligned DG devices with abrupt S/D regions and (iii) 25% back gate misalignment can be tolerated without any significant degradation in cut-off frequency (f(T)) and intrinsic voltage gain (A(VO)). Gate-underlap DG devices designed with spacer-to-straggle ratio lying within the range 2.5 to 3.0 show best tolerance to misaligned/oversize back gate and indeed are better than self-aligned DG MOSFETs with non-underlap (abrupt) S/D regions. Impact of gate length and silicon film thickness scaling is also discussed. These results are very significant as the tolerable limit of misaligned/oversized back gate is considerably extended and the stringent process control requirements to achieve self-alignment can be relaxed for nanoscale planar ULV DG MOSFETs operating in weak-inversion region. The present work provides new opportunities for realizing future ULV analog/rf design with nanoscale gate-underlap DG MOSFETs. (C) 2008 Elsevier Ltd. All rights reserved.