Design and Analysis of Inexact Floating-Point Adders

Power has become a key constraint in nanoscale inte-grated circuit design due to the increasing demands for mobile computing and higher integration density. As an emerging compu-tational paradigm, an inexact circuit offers a promising approach to significantly reduce both dynamic and static power dissipation for error-tolerant applications. In this paper, an inexact floating-point adder is proposed by approximately designing an exponent sub-tractor and mantissa adder. Related operations such as normaliza-tion and rounding are also dealt with in terms of inexact computing. An upper bound error analysis for the average case is presented to guide the inexact design; it shows that the inexact floating-point adder design is dependent on the application data range. High dynamic range images are then processed using the proposed inexact floating-point adders to show the validity of the inexact design; comparison results show that the proposed inexact floating-point adders can improve the power consumption and power-delay product by 29.98% and 39.60%, respectively.

Reconfigurable photonic logic architecture

The amorphous silicon photo-sensor studied in this thesis, is a double pin structure (p(a-SiC:H)-i’(a-SiC:H)-n(a-SiC:H)-p(a-SiC:H)-i(a-Si:H)-n(a-Si:H)) sandwiched between two transparent contacts deposited over transparent glass thus with the possibility of illumination on both sides, responding to wave-lengths from the ultra-violet, visible to the near infrared range. The frontal il-lumination surface, glass side, is used for light signal inputs. Both surfaces are used for optical bias, which changes the dynamic characteristics of the photo-sensor resulting in different outputs for the same input. Experimental studies were made with the photo-sensor to evaluate its applicability in multiplexing and demultiplexing several data communication channels. The digital light sig-nal was defined to implement simple logical operations like the NOT, AND, OR, and complex like the XOR, MAJ, full-adder and memory effect. A pro-grammable pattern emission system was built and also those for the validation and recovery of the obtained signals. This photo-sensor has applications in op-tical communications with several wavelengths, as a wavelength detector and to execute directly logical operations over digital light input signals.

Performance Analysis of Reversible Fast Decimal Adders

This paper presents a performance analysis of reversible, fault tolerant VLSI implementations of carry select and hybrid decimal adders suitable for multi-digit BCD addition. The designs enable partial parallel processing of all digits that perform high-speed addition in decimal domain. When the number of digits is more than 25 the hybrid decimal adder can operate 5 times faster than conventional decimal adder using classical logic gates. The speed up factor of hybrid adder increases above 10 when the number of decimal digits is more than 25 for reversible logic implementation. Such highspeed decimal adders find applications in real time processors and internet-based applications. The implementations use only reversible conservative Fredkin gates, which make it suitable for VLSI circuits.

Implementation of Parallel (p,q) Counters for High Speed Digital Multipliers

Both the (5,3) counter and (2,2,3) counter multiplication techniques are investigated for the efficiency of their operation speed and the viability of the architectures when implemented in a fast bipolar ECL technology. The implementation of the counters in series-gated ECL and threshold logic are contrasted for speed, noise immunity and complexity, and are critically compared with the fastest practical design of a full-adder. A novel circuit technique to overcome the problems of needing high fan-in input weights in threshold circuits through the use of negative weighted inputs is presented. The authors conclude that a (2,2,3) counter based array multiplier implemented in series-gated ECL should enable a significant increase in speed over conventional full adder based array multipliers.

Parallel Architectures for High Speed Multipliers

The authors compare various array multiplier architectures based on (p,q) counter circuits. The tradeoff in multiplier design is always between adding complexity and increasing speed. It is shown that by using a (2,2,3) counter cell it is possible to gain a significant increase in speed over a conventional full-adder, carry-save array based approach. The increase in complexity should be easily accommodated using modern emitter-coupled-logic processes.

The potential demise of a population of adders (Vipera berus) in Smygehuk, Sweden

Abstract.—In 1999 and 2004, we published reports on how the introduction of 20 males into a severely inbred and isolated population of Adders halted its decline towards extinction. The introduction significantly enhanced the population’s genetic variability, which resulted in a dramatic increase in offspring viability and a rapid increase in numbers.

A Modular and digitally programmable interface based on band-pass sigma-delta modulator for mixed-signal systems-on-chip

The focus of this thesis is to discuss the development and modeling of an interface architecture to be employed for interfacing analog signals in mixed-signal SOC. We claim that the approach that is going to be presented is able to achieve wide frequency range, and covers a large range of applications with constant performance, allied to digital configuration compatibility. Our primary assumptions are to use a fixed analog block and to promote application configurability in the digital domain, which leads to a mixed-signal interface. The use of a fixed analog block avoids the performance loss common to configurable analog blocks. The usage of configurability on the digital domain makes possible the use of all existing tools for high level design, simulation and synthesis to implement the target application, with very good performance prediction. The proposed approach utilizes the concept of frequency translation (mixing) of the input signal followed by its conversion to the ΣΔ domain, which makes possible the use of a fairly constant analog block, and also, a uniform treatment of input signal from DC to high frequencies. The programmability is performed in the ΣΔ digital domain where performance can be closely achieved according to application specification. The interface performance theoretical and simulation model are developed for design space exploration and for physical design support. Two prototypes are built and characterized to validate the proposed model and to implement some application examples. The usage of this interface as a multi-band parametric ADC and as a two channels analog multiplier and adder are shown. The multi-channel analog interface architecture is also presented. The characterization measurements support the main advantages of the approach proposed.

Modelagem em SystemC-AMS de uma plataforma compatível com o sistema de coleta de dados brasileiro

This work presents simulation results of an identification platform compatible with the INPE Brazilian Data Collection System, modeled with SystemC-AMS. SystemC-AMS that is a library of C++ classes dedicated to the simulation of heterogeneous systems, offering a powerful resource to describe models in digital, analog and RF domains, as well as mechanical and optic. The designed model was divided in four parts. The first block takes into account the satellite s orbit, necessary to correctly model the propagation channel, including Doppler effect, attenuation and thermal noise. The identification block detects the satellite presence. It is composed by low noise amplifier, band pass filter, power detector and logic comparator. The controller block is responsible for enabling the RF transmitter when the presence of the satellite is detected. The controller was modeled as a Petri net, due to the asynchronous nature of the system. The fourth block is the RF transmitter unit, which performs the modulation of the information in BPSK ±60o. This block is composed by oscillator, mixer, adder and amplifier. The whole system was simulated simultaneously. The results are being used to specify system components and to elaborate testbenchs for design verification

Customizing floating-point units for FPGAs: Area-performance-standard trade-offs

The high integration density of current nanometer technologies allows the implementation of complex floating-point applications in a single FPGA. In this work the intrinsic complexity of floating-point operators is addressed targeting configurable devices and making design decisions providing the most suitable performance-standard compliance trade-offs. A set of floating-point libraries composed of adder/subtracter, multiplier, divisor, square root, exponential, logarithm and power function are presented. Each library has been designed taking into account special characteristics of current FPGAs, and with this purpose we have adapted the IEEE floating-point standard (software-oriented) to a custom FPGA-oriented format. Extended experimental results validate the design decisions made and prove the usefulness of reducing the format complexity

Method to analyze the influence of hysteresis in optical arithmetic units

A new method to analyze the influence of possible hysteresis cycles in devices employed for optical computing architectures is reported. A simple full adder structure is taken as the basis for this method. Single units, called optical programmable logic cells, previously reported by the authors, compose this structure. These cells employ, as basic devices, on-off and SEED-like components. Their hysteresis cycles have been modeled by numerical analysis. The influence of the different characteristic cycles is studied with respect to the obtained possible errors at the output. Two different approaches have been adopted. The first one shows the change in the arithmetic result output with respect to the different values and positions of the hysteresis cycle. The second one offers a similar result, but in a polar diagram where the total behavior of the system is better analyzed.

Coder/decoder with an optical programmable logic cell

A major research area is the representation of knowledge for a given application in a compact manner such that desired information relating to this knowledge is easily recoverable. A complicated procedure may be required to recover the information from the stored representation and convert it back to usable form. Coder/decoder are the devices dedicated to that task. In this paper the capabilities that an Optical Programmable Logic Cell offers as a basic building block for coding and decoding are analyzed. We have previously published an Optically Programmable Logic Cells (OPLC), for applications as a chaotic generator or as basic element for optical computing. In optical computing previous studies these cells have been analyzed as full-adder units, being this element a basic component for the arithmetic logic structure in computing. Another application of this unit is reported in this paper. Coder and decoder are basic elements in computers, for example, in connections between processors and memory addressing. Moreover, another main application is the generation of signals for machine controlling from a certain instruction. In this paper we describe the way to obtain a coder/decoder with the OPLC and which type of applications may be the best suitable for this type of cell.

Semisumador y sumador completo para computación óptica

A half-adder and ñxll-adder desing using a new optical processing element is presented. The Optical Processing element is maded using fiber optic, optical couplers and non-linear optical device. This element allow programmability of fourteen difference pair of logical function of two inputs in two outputs. Two optical control signáis of non-binary logic made the choice of the logical function pair obtain in the outputs. By the appropiate selection of the power levels of the optical control signáis, we can configúrate a half-adder and with an small modification a full-adder. Also, a ripple carry adder desing is presented.

Logic gates using high Rydberg states

Connected logic gates can be operated on the levels of one molecule by making use of the special properties of high Rydberg states. Explicit experimental results for the NO molecule are provided as an example. A number of other options, including that of several gates concatenated so as to operate as a full adder, are discussed. Specific properties of high Rydberg states that are used are: their autoionization is delayed so that they can be distinguished from direct multiphoton ionization, during their long life such states also can decay by energy transfer to the molecular core in a way that can be controlled by the judicious application of very weak external electrical fields, and the Rydberg states can be detected by the application of an ionizing electrical field. The combination of two (or three) color photons with and without external weak fields allows the construction of quite elaborate logic circuit diagrams and shows that taking advantage of the different intramolecular dynamics of levels that differ by their excitation enables the compounding of logic operations on one molecular frame.

Análise de projetos de reassentamento habitacional: o caso do projeto Serra do Mar no estado de São Paulo.

As remoções de favelas são cada vez mais frequentes no contexto brasileiro e mundial. O reassentamento de famílias atingidas por estes processos deve respeitar os preceitos de moradia adequada como um direito que venha agregar qualidade de vida e dignidade às famílias atingidas, pois do contrário podem intensificar vulnerabilidades. A presente pesquisa analisa a adaptação e a satisfação dos moradores de um reassentamento, o Conjunto Rubens Lara, localizado no bairro Jardim Casqueiro na cidade de Cubatão, resultado de um deslocamento involuntário de famílias moradoras de favelas. O conjunto possui características distintas da produção de habitação social comumente praticada, como aspectos de localização, trabalho social e projeto. O método da pesquisa foi baseado em instrumentos que permitissem a visão dos diversos atores do processo, bem como a satisfação do usuário. Para análise dos dados quantitativos foi utilizada estatística descritiva, análise fatorial e a medida de incerteza. Os resultados mostram que o fato de se tratar de uma remoção involuntária não é determinante para a satisfação do morador. Atributos positivos que ofereçam qualidade de vida trazem maior influência na satisfação, mesmo em uma situação de remoção involuntária. A localização do empreendimento foi apontada como um aspecto determinante da satisfação por conta da oferta de serviços públicos, equipamentos urbanos e oportunidades de trabalho. No entanto, questões como o arranjo em condomínio, manutenção e incremento de gastos podem colocar os ganhos do projeto em risco. Quanto à gestão condominial verificou-se que a manutenção tem importante papel nas questões condominiais, pois é influenciada tanto por aspectos de engenharia como administrativos, podendo assim, ser um componente de preocupação no futuro. A satisfação com a manutenção se mostrou como um elemento de influência para a satisfação com a gestão condominial. Por outro lado, a satisfação com o valor da taxa de condomínio está ligada à capacidade de pagamento dos moradores e não pela qualidade dos serviços em si. Foi observada inadimplência menor que as encontradas na bibliografia.

BURSTLOGIC : design and analysis of logic circuitry to perform arithmetic on data in the Burst format /

Thesis--Illinois.