Preliminary Characterisation of Low-Temperature Bonded Copper Interconnects for 3-D Integrated Circuits

Three dimensional (3-D) integrated circuits can be fabricated by bonding previously processed device layers using metal-metal bonds that also serve as layer-to-layer interconnects. Bonded copper interconnects test structures were created by thermocompression bonding and the bond toughness was measured using the four-point test. The effects of bonding temperature, physical bonding and failure mechanisms were investigated. The surface effects on copper surface due to pre-bond clean (with glacial acetic acid) were also looked into. A maximum average bond toughness of approximately 35 J/m² was obtained bonding temperature 300 C.

Equivalent Circuits and Nanoplasmonics

We show how a circuit analysis, used widely in electrical engineering, finds application to problems of light wave injection and transport in subwavelength structures in the optical frequency range. Lumped circuit and transmission-line analysis may prove helpful in the design of plasmonic devices with standard, functional properties.

Design methodologies of microwawe integrated circuits for satellite telecommunications

The running innovation processes of the microwave transistor technologies, used in the implementation of microwave circuits, have to be supported by the study and development of proper design methodologies which, depending on the applications, will fully exploit the technology potentialities. After the choice of the technology to be used in the particular application, the circuit designer has few degrees of freedom when carrying out his design; in the most cases, due to the technological constrains, all the foundries develop and provide customized processes optimized for a specific performance such as power, low-noise, linearity, broadband etc. For these reasons circuit design is always a “compromise”, an investigation for the best solution to reach a trade off between the desired performances. This approach becomes crucial in the design of microwave systems to be used in satellite applications; the tight space constraints impose to reach the best performances under proper electrical and thermal de-rated conditions, respect to the maximum ratings provided by the used technology, in order to ensure adequate levels of reliability. In particular this work is about one of the most critical components in the front-end of a satellite antenna, the High Power Amplifier (HPA). The HPA is the main power dissipation source and so the element which mostly engrave on space, weight and cost of telecommunication apparatus; it is clear from the above reasons that design strategies addressing optimization of power density, efficiency and reliability are of major concern. Many transactions and publications demonstrate different methods for the design of power amplifiers, highlighting the availability to obtain very good levels of output power, efficiency and gain. Starting from existing knowledge, the target of the research activities summarized in this dissertation was to develop a design methodology capable optimize power amplifier performances complying all the constraints imposed by the space applications, tacking into account the thermal behaviour in the same manner of the power and the efficiency. After a reminder of the existing theories about the power amplifier design, in the first section of this work, the effectiveness of the methodology based on the accurate control of the dynamic Load Line and her shaping will be described, explaining all steps in the design of two different kinds of high power amplifiers. Considering the trade-off between the main performances and reliability issues as the target of the design activity, we will demonstrate that the expected results could be obtained working on the characteristics of the Load Line at the intrinsic terminals of the selected active device. The methodology proposed in this first part is based on the assumption that designer has the availability of an accurate electrical model of the device; the variety of publications about this argument demonstrates that it is so difficult to carry out a CAD model capable to taking into account all the non-ideal phenomena which occur when the amplifier operates at such high frequency and power levels. For that, especially for the emerging technology of Gallium Nitride (GaN), in the second section a new approach for power amplifier design will be described, basing on the experimental characterization of the intrinsic Load Line by means of a low frequency high power measurements bench. Thanks to the possibility to develop my Ph.D. in an academic spin-off, MEC – Microwave Electronics for Communications, the results of this activity has been applied to important research programs requested by space agencies, with the aim support the technological transfer from universities to industrial world and to promote a science-based entrepreneurship. For these reasons the proposed design methodology will be explained basing on many experimental results.

Analog Signal Acquisition and Conditioning for Near-Field Capacitive Communication and Active Combined EEG-EIT Monitoring

The work of the present thesis is focused on the implementation of microelectronic voltage sensing devices, with the purpose of transmitting and extracting analog information between devices of different nature at short distances or upon contact. Initally, chip-to-chip communication has been studied, and circuitry for 3D capacitive coupling has been implemented. Such circuits allow the communication between dies fabricated in different technologies. Due to their novelty, they are not standardized and currently not supported by standard CAD tools. In order to overcome such burden, a novel approach for the characterization of such communicating links has been proposed. This results in shorter design times and increased accuracy. Communication between an integrated circuit (IC) and a probe card has been extensively studied as well. Today wafer probing is a costly test procedure with many drawbacks, which could be overcome by a different communication approach such as capacitive coupling. For this reason wireless wafer probing has been investigated as an alternative approach to standard on-contact wafer probing. Interfaces between integrated circuits and biological systems have also been investigated. Active electrodes for simultaneous electroencephalography (EEG) and electrical impedance tomography (EIT) have been implemented for the first time in a 0.35 um process. Number of wires has been minimized by sharing the analog outputs and supply on a single wire, thus implementing electrodes that require only 4 wires for their operation. Minimization of wires reduces the cable weight and thus limits the patient's discomfort. The physical channel for communication between an IC and a biological medium is represented by the electrode itself. As this is a very crucial point for biopotential acquisitions, large efforts have been carried in order to investigate the different electrode technologies and geometries and an electromagnetic model is presented in order to characterize the properties of the electrode to skin interface.

Nano-Power Integrated Circuits for Energy Harvesting

The energy harvesting research field has grown considerably in the last decade due to increasing interests in energy autonomous sensing systems, which require smart and efficient interfaces for extracting power from energy source and power management (PM) circuits. This thesis investigates the design trade-offs for minimizing the intrinsic power of PM circuits, in order to allow operation with very weak energy sources. For validation purposes, three different integrated power converter and PM circuits for energy harvesting applications are presented. They have been designed for nano-power operations and single-source converters can operate with input power lower than 1 μW. The first IC is a buck-boost converter for piezoelectric transducers (PZ) implementing Synchronous Electrical Charge Extraction (SECE), a non-linear energy extraction technique. Moreover, Residual Charge Inversion technique is exploited for extracting energy from PZ with weak and irregular excitations (i.e. lower voltage), and the implemented PM policy, named Two-Way Energy Storage, considerably reduces the start-up time of the converter, improving the overall conversion efficiency. The second proposed IC is a general-purpose buck-boost converter for low-voltage DC energy sources, up to 2.5 V. An ultra-low-power MPPT circuit has been designed in order to track variations of source power. Furthermore, a capacitive boost circuit has been included, allowing the converter start-up from a source voltage VDC0 = 223 mV. A nano-power programmable linear regulator is also included in order to provide a stable voltage to the load. The third IC implements an heterogeneous multisource buck-boost converter. It provides up to 9 independent input channels, of which 5 are specific for PZ (with SECE) and 4 for DC energy sources with MPPT. The inductor is shared among channels and an arbiter, designed with asynchronous logic to reduce the energy consumption, avoids simultaneous access to the buck-boost core, with a dynamic schedule based on source priority.

FPGA BASED DESIGN FOR ACCELERATED FAULT-TESTING OF INTEGRATED CIRCUITS

In the past few decades, integrated circuits have become a major part of everyday life. Every circuit that is created needs to be tested for faults so faulty circuits are not sent to end-users. The creation of these tests is time consuming, costly and difficult to perform on larger circuits. This research presents a novel method for fault detection and test pattern reduction in integrated circuitry under test. By leveraging the FPGA's reconfigurability and parallel processing capabilities, a speed up in fault detection can be achieved over previous computer simulation techniques. This work presents the following contributions to the field of Stuck-At-Fault detection: We present a new method for inserting faults into a circuit net list. Given any circuit netlist, our tool can insert multiplexers into a circuit at correct internal nodes to aid in fault emulation on reconfigurable hardware. We present a parallel method of fault emulation. The benefit of the FPGA is not only its ability to implement any circuit, but its ability to process data in parallel. This research utilizes this to create a more efficient emulation method that implements numerous copies of the same circuit in the FPGA. A new method to organize the most efficient faults. Most methods for determinin the minimum number of inputs to cover the most faults require sophisticated softwareprograms that use heuristics. By utilizing hardware, this research is able to process data faster and use a simpler method for an efficient way of minimizing inputs.

Semiconductor measurement technology : techniques for measuring the integrity of passivation overcoats on integrated circuits /

Mode of access: Internet.

ARPA/NBS workshop III : test patterns for integrated circuits /

Consists of synopses of talks and discussions presented at the workshop held Sept. 6, 1974 in Scottsdale, Ariz.

Introduction to UHF circuits and components.

"Based on an earlier work entitled UHF radio simplified, by M.S. Kiver."

Testing of Interposer-Based 2.5D Integrated Circuits

The unprecedented and relentless growth in the electronics industry is feeding the demand for integrated circuits (ICs) with increasing functionality and performance at minimum cost and power consumption. As predicted by Moore's law, ICs are being aggressively scaled to meet this demand. While the continuous scaling of process technology is reducing gate delays, the performance of ICs is being increasingly dominated by interconnect delays. In an effort to improve submicrometer interconnect performance, to increase packing density, and to reduce chip area and power consumption, the semiconductor industry is focusing on three-dimensional (3D) integration. However, volume production and commercial exploitation of 3D integration are not feasible yet due to significant technical hurdles.

At the present time, interposer-based 2.5D integration is emerging as a precursor to stacked 3D integration. All the dies and the interposer in a 2.5D IC must be adequately tested for product qualification. However, since the structure of 2.5D ICs is different from the traditional 2D ICs, new challenges have emerged: (1) pre-bond interposer testing, (2) lack of test access, (3) limited ability for at-speed testing, (4) high density I/O ports and interconnects, (5) reduced number of test pins, and (6) high power consumption. This research targets the above challenges and effective solutions have been developed to test both dies and the interposer.

The dissertation first introduces the basic concepts of 3D ICs and 2.5D ICs. Prior work on testing of 2.5D ICs is studied. An efficient method is presented to locate defects in a passive interposer before stacking. The proposed test architecture uses e-fuses that can be programmed to connect or disconnect functional paths inside the interposer. The concept of a die footprint is utilized for interconnect testing, and the overall assembly and test flow is described. Moreover, the concept of weighted critical area is defined and utilized to reduce test time. In order to fully determine the location of each e-fuse and the order of functional interconnects in a test path, we also present a test-path design algorithm. The proposed algorithm can generate all test paths for interconnect testing.

In order to test for opens, shorts, and interconnect delay defects in the interposer, a test architecture is proposed that is fully compatible with the IEEE 1149.1 standard and relies on an enhancement of the standard test access port (TAP) controller. To reduce test cost, a test-path design and scheduling technique is also presented that minimizes a composite cost function based on test time and the design-for-test (DfT) overhead in terms of additional through silicon vias (TSVs) and micro-bumps needed for test access. The locations of the dies on the interposer are taken into consideration in order to determine the order of dies in a test path.

To address the scenario of high density of I/O ports and interconnects, an efficient built-in self-test (BIST) technique is presented that targets the dies and the interposer interconnects. The proposed BIST architecture can be enabled by the standard TAP controller in the IEEE 1149.1 standard. The area overhead introduced by this BIST architecture is negligible; it includes two simple BIST controllers, a linear-feedback-shift-register (LFSR), a multiple-input-signature-register (MISR), and some extensions to the boundary-scan cells in the dies on the interposer. With these extensions, all boundary-scan cells can be used for self-configuration and self-diagnosis during interconnect testing. To reduce the overall test cost, a test scheduling and optimization technique under power constraints is described.

In order to accomplish testing with a small number test pins, the dissertation presents two efficient ExTest scheduling strategies that implements interconnect testing between tiles inside an system on chip (SoC) die on the interposer while satisfying the practical constraint that the number of required test pins cannot exceed the number of available pins at the chip level. The tiles in the SoC are divided into groups based on the manner in which they are interconnected. In order to minimize the test time, two optimization solutions are introduced. The first solution minimizes the number of input test pins, and the second solution minimizes the number output test pins. In addition, two subgroup configuration methods are further proposed to generate subgroups inside each test group.

Finally, the dissertation presents a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs. An SoC die in the 2.5D IC is typically composed of several blocks and two neighboring blocks that share the same power rails should not be toggled at the same time during shift. Therefore, the proposed programmable method does not assign the same stagger value to neighboring blocks. The positions of all blocks are first analyzed and the shared boundary length between blocks is then calculated. Based on the position relationships between the blocks, a mathematical model is presented to derive optimal result for small-to-medium sized problems. For larger designs, a heuristic algorithm is proposed and evaluated.

In summary, the dissertation targets important design and optimization problems related to testing of interposer-based 2.5D ICs. The proposed research has led to theoretical insights, experiment results, and a set of test and design-for-test methods to make testing effective and feasible from a cost perspective.

Solid-liquid interactions in microscale structures and devices

Liquid-solid interactions become important as dimensions approach mciro/nano-scale. This dissertation focuses on liquid-solid interactions in two distinct applications: capillary driven self-assembly of thin foils into 3D structures, and droplet wetting of hydrophobic micropatterned surfaces. The phenomenon of self-assembly of complex structures is common in biological systems. Examples include self-assembly of proteins into macromolecular structures and self-assembly of lipid bilayer membranes. The principles governing this phenomenon have been applied to induce self-assembly of millimeter scale Si thin films into spherical and other 3D structures, which are then integrated into light-trapping photovoltaic (PV) devices. Motivated by this application, we present a generalized analytical study of the self-folding of thin plates into deterministic 3D shapes, through fluid-solid interactions, to be used as PV devices. This study consists of developing a model using beam theory, which incorporates the two competing components — a capillary force that promotes folding and the bending rigidity of the foil that resists folding into a 3D structure. Through an equivalence argument of thin foils of different geometry, an effective folding parameter, which uniquely characterizes the driving force for folding, has been identified. A criterion for spontaneous folding of an arbitrarily shaped 2D foil, based on the effective folding parameter, is thus established. Measurements from experiments using different materials and predictions from the model match well, validating the assumptions used in the analysis. As an alternative to the mechanics model approach, the minimization of the total free energy is employed to investigate the interactions between a fluid droplet and a flexible thin film. A 2D energy functional is proposed, comprising the surface energy of the fluid, bending energy of the thin film and gravitational energy of the fluid. Through simulations with Surface Evolver, the shapes of the droplet and the thin film at equilibrium are obtained. A critical thin film length necessary for complete enclosure of the fluid droplet, and hence successful self-assembly into a PV device, is determined and compared with the experimental results and mechanics model predictions. The results from the modeling and energy approaches and the experiments are all consistent. Superhydrophobic surfaces, which have unique properties including self-cleaning and water repelling are desired in many applications. One excellent example in nature is the lotus leaf. To fabricate these surfaces, well designed micro/nano- surface structures are often employed. In this research, we fabricate superhydrophobic micropatterned Polydimethylsiloxane (PDMS) surfaces composed of micropillars of various sizes and arrangements by means of soft lithography. Both anisotropic surfaces, consisting of parallel grooves and cylindrical pillars in rectangular lattices, and isotropic surfaces, consisting of cylindrical pillars in square and hexagonal lattices, are considered. A novel technique is proposed to image the contact line (CL) of the droplet on the hydrophobic surface. This technique provides a new approach to distinguish between partial and complete wetting. The contact area between droplet and microtextured surface is then measured for a droplet in the Cassie state, which is a state of partial wetting. The results show that although the droplet is in the Cassie state, the contact area does not necessarily follow Cassie model predictions. Moreover, the CL is not circular, and is affected by the micropatterns, in both isotropic and anisotropic cases. Thus, it is suggested that along with the contact angle — the typical parameter reported in literature quantifying wetting, the size and shape of the contact area should also be presented. This technique is employed to investigate the evolution of the CL on a hydrophobic micropatterned surface in the cases of: a single droplet impacting the micropatterned surface, two droplets coalescing on micropillars, and a receding droplet resting on the micropatterned surface. Another parameter which quantifies hydrophobicity is the contact angle hysteresis (CAH), which indicates the resistance of the surface to the sliding of a droplet with a given volume. The conventional methods of using advancing and receding angles or tilting stage to measure the resistance of the micropatterned surface are indirect, without mentioning the inaccuracy due to the discrete and stepwise motion of the CL on micropillars. A micronewton force sensor is utilized to directly measure the resisting force by dragging a droplet on a microtextured surface. Together with the proposed imaging technique, the evolution of the CL during sliding is also explored. It is found that, at the onset of sliding, the CL behaves as a linear elastic solid with a constant stiffness. Afterwards, the force first increases and then decreases and reaches a steady state, accompanied with periodic oscillations due to regular pinning and depinning of the CL. Both the maximum and steady state forces are primarily dependent on area fractions of the micropatterned surfaces in our experiment. The resisting force is found to be proportional to the number of pillars which pin the CL at the trailing edge, validating the assumption that the resistance mainly arises from the CL pinning at the trailing edge. In each pinning-and-depinning cycle during the steady state, the CL also shows linear elastic behavior but with a lower stiffness. The force variation and energy dissipation involved can also be determined. This novel method of measuring the resistance of the micropatterned surface elucidates the dependence on CL pinning and provides more insight into the mechanisms of CAH.

PCM-based in-memory computing: architectures, circuits and applications

Analog In-memory Computing (AIMC) has been proposed in the context of Beyond Von Neumann architectures as a valid strategy to reduce internal data transfers energy consumption and latency, and to improve compute efficiency. The aim of AIMC is to perform computations within the memory unit, typically leveraging the physical features of memory devices. Among resistive Non-volatile Memories (NVMs), Phase-change Memory (PCM) has become a promising technology due to its intrinsic capability to store multilevel data. Hence, PCM technology is currently investigated to enhance the possibilities and the applications of AIMC. This thesis aims at exploring the potential of new PCM-based architectures as in-memory computational accelerators. In a first step, a preliminar experimental characterization of PCM devices has been carried out in an AIMC perspective. PCM cells non-idealities, such as time-drift, noise, and non-linearity have been studied to develop a dedicated multilevel programming algorithm. Measurement-based simulations have been then employed to evaluate the feasibility of PCM-based operations in the fields of Deep Neural Networks (DNNs) and Structural Health Monitoring (SHM). Moreover, a first testchip has been designed and tested to evaluate the hardware implementation of Multiply-and-Accumulate (MAC) operations employing PCM cells. This prototype experimentally demonstrates the possibility to reach a 95% MAC accuracy with a circuit-level compensation of cells time drift and non-linearity. Finally, empirical circuit behavior models have been included in simulations to assess the use of this technology in specific DNN applications, and to enhance the potentiality of this innovative computation approach.

Progress in integrated assessment and modelling

Environmental processes have been modelled for decades. However. the need for integrated assessment and modeling (IAM) has,town as the extent and severity of environmental problems in the 21st Century worsens. The scale of IAM is not restricted to the global level as in climate change models, but includes local and regional models of environmental problems. This paper discusses various definitions of IAM and identifies five different types of integration that Lire needed for the effective solution of environmental problems. The future is then depicted in the form of two brief scenarios: one optimistic and one pessimistic. The current state of IAM is then briefly reviewed. The issues of complexity and validation in IAM are recognised as more complex than in traditional disciplinary approaches. Communication is identified as a central issue both internally among team members and externally with decision-makers. stakeholders and other scientists. Finally it is concluded that the process of integrated assessment and modelling is considered as important as the product for any particular project. By learning to work together and recognise the contribution of all team members and participants, it is believed that we will have a strong scientific and social basis to address the environmental problems of the 21st Century. (C) 2002 Elsevier Science Ltd. All rights reserved.