Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor

A generalized power tracking algorithm that minimizes power consumption of digital circuits by dynamic control of supply voltage and the body bias is proposed. A direct power monitoring scheme is proposed that does not need any replica and hence can sense total power consumed by load circuit across process, voltage, and temperature corners. Design details and performance of power monitor and tracking algorithm are examined by a simulation framework developed using UMC 90-nm CMOS triple well process. The proposed algorithm with direct power monitor achieves a power savings of 42.2% for activity of 0.02 and 22.4% for activity of 0.04. Experimental results from test chip fabricated in AMS 350 nm process shows power savings of 46.3% and 65% for load circuit operating in super threshold and near sub-threshold region, respectively. Measured resolution of power monitor is around 0.25 mV and it has a power overhead of 2.2% of die power. Issues with loop convergence and design tradeoff for power monitor are also discussed in this paper.

A mostly-digital analog scan-out chain for low bandwidth voltage measurement for analog IP test

A method of precise measurement of on-chip analog voltages in a mostly-digital manner, with minimal overhead, is presented. A pair of clock signals is routed to the node of an analog voltage. This analog voltage controls the delay between this pair of clock signals, which is then measured in an all-digital manner using the technique of sub-sampling. This sub-sampling technique, having measurement time and accuracy trade-off, is well suited for low bandwidth signals. This concept is validated by designing delay cells, using current starved inverters in UMC 130nm CMOS process. Sub-mV accuracy is demonstrated for a measurement time of few seconds.

“Post silicon debug of SOC designs”

Continuous advances in VLSI technology have made implementation of very complicated systems possible. Modern System-on -Chips (SoCs) have many processors, IP cores and other functional units. As a result, complete verification of whole systems before implementation is becoming infeasible; hence it is likely that these systems may have some errors after manufacturing. This increases the need to find design errors in chips after fabrication. The main challenge for post-silicon debug is the observability of the internal signals. Post-silicon debug is the problem of determining what's wrong when the fabricated chip of a new design behaves incorrectly. This problem now consumes over half of the overall verification effort on large designs, and the problem is growing worse.Traditional post-silicon debug methods concentrate on functional parts of systems and provide mechanisms to increase the observability of internal state of systems. Those methods may not be sufficient as modern SoCs have lots of blocks (processors, IP cores, etc.) which are communicating with one another and communication is another source of design errors. This tutorial will be provide an insight into various observability enhancement techniques, on chip instrumentation techniques and use of high level models to support the debug process targeting both inside blocks and communication among them. It will also cover the use of formal methods to help debug process.

Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor

A generalized power tracking algorithm that minimizes power consumption of digital circuits by dynamic control of supply voltage and the body bias is proposed. A direct power monitoring scheme is proposed that does not need any replica and hence can sense total power consumed by load circuit across process, voltage, and temperature corners. Design details and performance of power monitor and tracking algorithm are examined by a simulation framework developed using UMC 90-nm CMOS triple well process. The proposed algorithm with direct power monitor achieves a power savings of 42.2% for activity of 0.02 and 22.4% for activity of 0.04. Experimental results from test chip fabricated in AMS 350 nm process shows power savings of 46.3% and 65% for load circuit operating in super threshold and near sub-threshold region, respectively. Measured resolution of power monitor is around 0.25 mV and it has a power overhead of 2.2% of die power. Issues with loop convergence and design tradeoff for power monitor are also discussed in this paper.

Microstructure and damping behaviour of consolidated magnesium chips

Chips produced by turning a commercial grade pure magnesium billet were consolidated by solid state recycling technique of cold compaction followed by hot extrusion. The cold compacted billets were extruded at four different temperatures: 250 degrees C, 300 degrees C, 350 degrees C and 400 degrees C. For the purpose of comparison, cast magnesium (pure) billets were extruded under similar conditions. Extruded products were characterized for damping properties. Damping capacity and dynamic modulus was measured as a function of time and temperature at a fixed frequency of 5 Hz 10 to 14% increase in damping capacity was observed in chip consolidated products compared to reference material. Microstructural changes after the temperature sweep tests were examined. Chip boundaries present in consolidated products were observed to suppress grain coarsening which otherwise was significant in reference material. The present work is significant from the viewpoint of recycling of machined chips and development of sustainable manufacturing processes. (C) 2012 Elsevier B.V. All rights reserved.

A Coordinated Interdependent Protein Circuitry Stabilizes the Kinetochore Ensemble to Protect CENP-A in the Human Pathogenic Yeast Candida albicans

Unlike most eukaryotes, a kinetochore is fully assembled early in the cell cycle in budding yeasts Saccharomyces cerevisiae and Candida albicans. These kinetochores are clustered together throughout the cell cycle. Kinetochore assembly on point centromeres of S. cerevisiae is considered to be a step-wise process that initiates with binding of inner kinetochore proteins on specific centromere DNA sequence motifs. In contrast, kinetochore formation in C. albicans, that carries regional centromeres of 3-5 kb long, has been shown to be a sequence independent but an epigenetically regulated event. In this study, we investigated the process of kinetochore assembly/disassembly in C. albicans. Localization dependence of various kinetochore proteins studied by confocal microscopy and chromatin immunoprecipitation (ChIP) assays revealed that assembly of a kinetochore is a highly coordinated and interdependent event. Partial depletion of an essential kinetochore protein affects integrity of the kinetochore cluster. Further protein depletion results in complete collapse of the kinetochore architecture. In addition, GFP-tagged kinetochore proteins confirmed similar time-dependent disintegration upon gradual depletion of an outer kinetochore protein (Dam1). The loss of integrity of a kinetochore formed on centromeric chromatin was demonstrated by reduced binding of CENP-A and CENP-C at the centromeres. Most strikingly, Western blot analysis revealed that gradual depletion of any of these essential kinetochore proteins results in concomitant reduction in cellular protein levels of CENP-A. We further demonstrated that centromere bound CENP-A is protected from the proteosomal mediated degradation. Based on these results, we propose that a coordinated interdependent circuitry of several evolutionarily conserved essential kinetochore proteins ensures integrity of a kinetochore formed on the foundation of CENP-A containing centromeric chromatin.

An Accurate Fractional Period Delay Generation System

An all-digital technique is proposed for generating an accurate delay irrespective of the inaccuracies of a controllable delay line. A subsampling technique-based delay measurement unit (DMU) capable of measuring delays accurately for the full period range is used as the feedback element to build accurate fractional period delays based on input digital control bits. The proposed delay generation system periodically measures and corrects the error and maintains it at the minimum value without requiring any special calibration phase. Up to 40x improvement in accuracy is demonstrated for a commercial programmable delay generator chip. The time-precision trade-off feature of the DMU is utilized to reduce the locking time. Loop dynamics are adjusted to stabilize the delay after the minimum error is achieved, thus avoiding additional jitter. Measurement results from a high-end oscilloscope also validate the effectiveness of the proposed system in improving accuracy.

Compiler-assisted energy optimization for clustered VLIW processors

Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption. Although clustering helps by improving the clock speed, reducing the energy consumption of the logic, and making the design simpler, it introduces extra overheads by way of inter-cluster communication. This communication happens over long global wires having high load capacitance which leads to delay in execution and significantly high energy consumption. Inter-cluster communication also introduces many short idle cycles, thereby significantly increasing the overall leakage energy consumption in the functional units. The trend towards miniaturization of devices (and associated reduction in threshold voltage) makes energy consumption in interconnects and functional units even worse, and limits the usability of clustered architectures in smaller technologies. However, technological advancements now permit the design of interconnects and functional units with varying performance and power modes. In this paper, we propose scheduling algorithms that aggregate the scheduling slack of instructions and communication slack of data values to exploit the low-power modes of functional units and interconnects. Finally, we present a synergistic combination of these algorithms that simultaneously saves energy in functional units and interconnects to improves the usability of clustered architectures by achieving better overall energy-performance trade-offs. Even with conservative estimates of the contribution of the functional units and interconnects to the overall processor energy consumption, the proposed combined scheme obtains on average 8% and 10% improvement in overall energy-delay product with 3.5% and 2% performance degradation for a 2-clustered and a 4-clustered machine, respectively. We present a detailed experimental evaluation of the proposed schemes. Our test bed uses the Trimaran compiler infrastructure. (C) 2012 Elsevier Inc. All rights reserved.

Colossal nonsaturating linear magnetoresistance in two-dimensional electron systems at a GaAs/(Al,Ga)As heterointerface

Engineering devices with a large electrical response to magnetic field is of fundamental importance for a range of applications such as magnetic field sensing and magnetic read heads. We show that a colossal nonsaturating linear magnetoresistance (NLMR) arises in two-dimensional electron systems hosted in a GaAs/AlGaAs heterostructure in the strongly insulating regime. When operated at high source-drain bias, the magnetoresistance of our devices increases almost linearly with magnetic field, reaching nearly 10 000% at 8 T, thus surpassing many known nonmagnetic materials that exhibit giant NLMR. The temperature dependence and mobility analysis indicate that the NLMR has a purely classical origin, driven by nanoscale inhomogeneities. A large NLMR combined with small device dimensions makes these systems an attractive candidate for on-chip magnetic field sensing.

Under-representation of intrinsic terminators across bacterial genomic islands: Rho as a principal regulator of xenogenic DNA expression

Two transcription termination mechanisms - intrinsic and Rho-dependent - have evolved in bacteria. The Rho factor occurs in most bacterial lineages, and has been hypothesized to play a global regulatory role. Genome-wide studies using microarray, 2D-gel electrophoresis and ChIP-chip provided evidence that Rho serves to silence transcription from horizontally acquired genes and prophages in Escherichia coli K-12, implicating the factor to be a part of the ``cellular immune mechanism'' protecting against deleterious phages and aberrant gene expression from acquired xenogenic DNA. We have investigated this model by adopting an alternate in silico approach and have extended the study to other species. Our analysis shows that several genomic islands across diverse phyla have under-representation of intrinsic terminators, similar to that experimentally observed in E. coli K-12. This implies that Rho-dependent termination is the predominant process operational in these islands and that silencing of foreign DNA is a conserved function of Rho. From the present analysis, it is evident that horizontally acquired islands have lost intrinsic terminators to facilitate Rho-dependent termination. These results underscore the importance of Rho as a conserved, genome-wide sentinel that regulates potentially toxic xenogenic DNA. (C) 2012 Elsevier B.V. All rights reserved.

A CMOS Gas Sensor Array Platform With Fourier Transform Based Impedance Spectroscopy

A CMOS gas sensor array platform with digital read-out containing 27 sensor pixels and a reference pixel is presented. A signal conditioning circuit at each pixel includes digitally programmable gain stages for sensor signal amplification followed by a second order continuous time delta sigma modulator for digitization. Each sensor pixel can be functionalized with a distinct sensing material that facilitates transduction based on impedance change. Impedance spectrum (up to 10 KHz) of the sensor is obtained off-chip by computing the fast Fourier transform of sensor and reference pixel outputs. The reference pixel also compensates for the phase shift introduced by the signal processing circuits. The chip also contains a temperature sensor with digital readout for ambient temperature measurement. A sensor pixel is functionalized with polycarbazole conducting polymer for sensing volatile organic gases and measurement results are presented. The chip is fabricated in a 0.35 CMOS technology and requires a single step post processing for functionalization. It consumes 57 mW from a 3.3 V supply.

MACHINING OF MMCs: A REVIEW

Over the last few decades, Metal Matrix Composites (MMCs) have emerged as a material system offering tremendous potential for future applications. The primary advantages offered by these materials are their improved mechanical properties, particularly in the areas of wear, strength and stiffness. Of the MMCs, Aluminum matrix composites have grown in prominence due to their low density, low melting point and low cost. However, machining these materials remains a challenging task mainly due to the high abrasiveness of the reinforcing phases. Conventional machining processes such as turning, milling or drilling are adopted for machining MMCs. In this article, the existing and ongoing developments in machining MMCs vis-a-vis tool life, tool wear, machinability and understanding chip formation mechanism have been highlighted. Most of the studies discussed in this review will focus on Aluminum matrix composites. Certain areas of machining studies which have hitherto not been investigated have also been detailed.

Evaluation of dynamic voltage and frequency scaling for stream programs

Dynamic Voltage and Frequency Scaling (DVFS) offers a huge potential for designing trade-offs involving energy, power, temperature and performance of computing systems. In this paper, we evaluate three different DVFS schemes - our enhancement of a Petri net performance model based DVFS method for sequential programs to stream programs, a simple profile based Linear Scaling method, and an existing hardware based DVFS method for multithreaded applications - using multithreaded stream applications, in a full system Chip Multiprocessor (CMP) simulator. From our evaluation, we find that the software based methods achieve significant Energy/Throughput2(ET−2) improvements. The hardware based scheme degrades performance heavily and suffers ET−2 loss. Our results indicate that the simple profile based scheme achieves the benefits of the complex Petri net based scheme for stream programs, and present a strong case for the need for independent voltage/frequency control for different cores of CMPs, which is lacking in most of the state-of-the-art CMPs. This is in contrast to the conclusions of a recent evaluation of per-core DVFS schemes for multithreaded applications for CMPs.

Comparison of performance of OCDMA networks with correlation and chiplevel receivers

In this paper optical code-division multiple-access (O-CDMA) packet network is considered, which offers inherent security in the access networks. Two types of random access protocols are proposed for packet transmission. In protocol 1, all distinct codes and in protocol 2, distinct codes as well as shifted versions of all these codes are used. O-CDMA network performance using optical orthogonal codes (OOCs) 1-D and two-dimensional (2-D) wavelength/time single-pulse-per-row (W/T SPR) codes are analyzed. The main advantage of using 2-D codes instead of one-dimensional (1-D) codes is to reduce the errors due to multiple access interference among different users. In this paper, correlation receiver and chip-level receiver are considered in the analysis. Using analytical model, we compute packet-success probability, throughput and compare for OOC and SPR codes in an O-CDMA network and the analysis shows improved performance with SPR codes as compared to OOC codes.

Multiuser detection in large-dimension multicode MIMO-CDMA systems with higher-order modulation

In this paper, we are interested in high spectral efficiency multicode CDMA systems with large number of users employing single/multiple transmit antennas and higher-order modulation. In particular, we consider a local neighborhood search based multiuser detection algorithm which offers very good performance and complexity, suited for systems with large number of users employing M-QAM/M-PSK. We apply the algorithm on the chip matched filter output vector. We demonstrate near-single user (SU) performance of the algorithm in CDMA systems with large number of users using 4-QAM/16-QAM/64-QAM/8-PSK on AWGN, frequency-flat, and frequency-selective fading channels. We further show that the algorithm performs very well in multicode multiple-input multiple-output (MIMO) CDMA systems as well, outperforming other linear detectors and interference cancelers reported in the literature for such systems. The per-symbol complexity of the search algorithm is O(K2n2tn2cM), K: number of users, nt: number of transmit antennas at each user, nc: number of spreading codes multiplexed on each transmit antenna, M: modulation alphabet size, making the algorithm attractive for multiuser detection in large-dimension multicode MIMO-CDMA systems with M-QAM.