Latency, Power and Performance Trade-offs in Network-on-Chips by Link Microarchitecture Exploration

This paper presents a power, latency and throughput trade-off study on NoCs by varying microarchitectural (e.g. pipelining) and circuit level (e.g. frequency and voltage) parameters. We change pipelining depth, operating frequency and supply voltage for 3 example NoCs - 16 node 2D Torus, Tree network and Reduced 2D Torus. We use an in-house NoC exploration framework capable of topology generation and comparison using parameterized models of Routers and links developed in SystemC. The framework utilizes interconnect power and delay models from a low-level modelling tool called Intacte[1]1. We find that increased pipelining can actually reduce latency. We also find that there exists an optimal degree of pipelining which is the most energy efficient in terms of minimizing energy-delay product.

A Dual Seven-Level Inverter Supply for an Open-End Winding Induction Motor Drive

This paper develops a seven-level inverter structure for open-end winding induction motor drives. The inverter supply is realized by cascading four two-level and two three-level neutral-point-clamped inverters. The inverter control is designed in such a way that the common-mode voltage (CMV) is eliminated. DC-link capacitor voltage balancing is also achieved by using only the switching-state redundancies. The proposed power circuit structure is modular and therefore suitable for fault-tolerant applications. By appropriately isolating some of the inverters, the drive can be operated during fault conditions in a five-level or a three-level inverter mode, with preserved CMV elimination and DC-link capacitor voltage balancing, within a reduced modulation range.

Regulating supply chains to protect road transport workers: An early assessment of the road safety remuneration tribunal

The Road Safety Remuneration Act 2012 (Cth) (the Act) explicitly enables the Road Safety Remuneration Tribunal to make orders that can impose binding requirements on all the participants in the road transport supply chain, including consignors and consignees at the apex the chain, for the pay and safety of both employee and independent contractor drivers. The tribunal is also specifically empowered to make enforceable orders to reduce or remove remuneration related incentives and pressures that contribute to unsafe work practices in the road transport industry. Recently the tribunal handed down its first order. The article considers whether, and the degree to which, the tribunal has been willing to exercise its explicit power to impose enforceable obligations on consignors and consignees — such as large supermarket chains — at the apex of road transport supply chains. It examines the substance and extent of the obligations imposed by the tribunal, including whether the tribunal has exercised the full range of powers vested in it by the Act. We contend that the tribunal’s first order primarily imposes obligations on direct work providers and drivers without making large, powerful consignors and consignees substantively responsible for driver pay and safety. We argue that the tribunal’s first order could have more comprehensively fulfilled the objectives of the Act by more directly addressing the root causes of low pay and poor safety in the road transport industry.

A 100MHz to 1GHz, 0.35V to 1.5V supply 256 x 64 SRAM mock using symmetrized 9T SRAM cell with controlled read

In this paper, we present Dynamic Voltage and Frequency Managed 256 x 64 SRAM block in 65nm technology, for frequency ranging from 100MHz to 1GHz. The total energy is minimized for any operating frequency in the above range and leakage energy is minimized during standby mode. Since noise margin of SRAM cell deteriorates at low voltages, we propose Static Noise Margin improvement circuitry, which symmetrizes the SRAM cell by controlling the body bias of pull down NMOS transistor. We used a 9T SRAM cell that isolates Read and Hold Noise Margin and has less leakage. We have implemented an efficient technique of pushing address decoder into zigzag-super-cut-off in stand-by mode without affecting its performance in active mode of operation. The Read Bit Line (RBL) voltage drop is controlled and pre-charge of bit lines is done only when needed for reducing power wastage.

Low Power continuous time common mode sensing for common mode feedback circuits

Continuous common mode feedback (CMFB) circuits having high input impedance and low distortion are proposed. The proposed circuits are characterized for 0.18 mu m CMOS process with 1.8 V supply. Simulation results indicate that the proposed common mode detector consumes no standby power and CMFB circuit consumes 27-34% less power than previous high swing CMFB circuits.

A System-C based Micro architectural Exploration Framework for Latency, Power and Performance Trade-offs of On-Chip Interconnection

We describe a System-C based framework we are developing, to explore the impact of various architectural and microarchitectural level parameters of the on-chip interconnection network elements on its power and performance. The framework enables one to choose from a variety of architectural options like topology, routing policy, etc., as well as allows experimentation with various microarchitectural options for the individual links like length, wire width, pitch, pipelining, supply voltage and frequency. The framework also supports a flexible traffic generation and communication model. We provide preliminary results of using this framework to study the power, latency and throughput of a 4x4 multi-core processing array using mesh, torus and folded torus, for two different communication patterns of dense and sparse linear algebra. The traffic consists of both Request-Response messages (mimicing cache accesses)and One-Way messages. We find that the average latency can be reduced by increasing the pipeline depth, as it enables higher link frequencies. We also find that there exists an optimum degree of pipelining which minimizes energy-delay product.

A 100MHz to 1GHz, 0.35V to 1.5V Supply 256 x 64 SRAM Block Using Symmetrized 9T SRAM Cell with Controlled Read

In this paper, we present dynamic voltage and frequency Managed 256 x 64 SRAM block in 65 nm technology, for frequency ranging from 100 MHz to 1 GHz. The total energy is minimized for any operating frequency in the above range and leakage energy is minimized during standby mode. Since noise margin of SRAM cell deteriorates at low voltages, we propose static noise margin improvement circuitry, which symmetrizes the SRAM cell by controlling the body bias of pull down NMOS transistor. We used a 9T SRAM cell that isolates Read and hold noise margin and has less leakage. We have implemented an efficient technique of pushing address decoder into zigzag- super-cut-off in stand-by mode without affecting its performance in active mode of operation. The read bit line (RBL) voltage drop is controlled and pre-charge of bit lines is done only when needed for reducing power wastage.

A Low Power Frequency Multiplication Technique for Zigbee Transceiver

A low-power frequency multiplication technique, developed for ZigBee (IEEE 802.15.4) like applications is presented. We have provided an estimate for the power consumption for a given output voltage swing using our technique. The advantages and disadvantages which determine the application areas of the technique are discussed. The issues related to design, layout and process variation are also addressed. Finally, a design is presented for operation in 2.405-2.485-GHz band of ZigBee receiver. SpectreRF simulations show 30% improvement in efficiency for our circuit with regard to conversion of DC bias current to output amplitude, against a LC-VCO. To establish the low-power credentials, we have compared our circuit with an existing technique; our circuit performs better with just 1/3 of total current from supply, and uses one inductor as against three in the latter case. A test chip was implemented in UMC 0.13-mum RF process with spiral on-chip inductors and MIM (metal-insulator-metal) capacitor option.

A Five-Level Inverter Topology with Single-DC Supply by Cascading a Flying Capacitor Inverter and an H-Bridge

In this paper, a new three-phase, five-level inverter topology with a single-dc source is presented. The proposed topology is obtained by cascading a three-level flying capacitor inverter with a flying H-bridge power cell in each phase. This topology has redundant switching states for generating different pole voltages. By selecting appropriate switching states, the capacitor voltages can be balanced instantaneously (as compared to the fundamental) in any direction of the current, irrespective of the load power factor. Another important feature of this topology is that if any H-bridge fails, it can be bypassed and the configuration can still operate as a three-level inverter at its full power rating. This feature improves the reliability of the circuit. A 3-kW induction motor is run with the proposed topology for the full modulation range. The effectiveness of the capacitor balancing algorithm is tested for the full range of speed and during the sudden acceleration of the motor.

Proportional resonant controller based circulating power setup for thermal testing of multilevel inverter

A regenerative or circulating-power method is presented in this paper for heat run test on the legs of a three-level neutral point clamped (NPC) inverter. This test ensures that only losses are drawn from the dc supply, while rated power is circulated between the two legs, thus minimising wastage of energy. A proportional-resonant (PR) controller based current control scheme is proposed here for the circulating power test setup in NPC inverter. Simulation and experimental results are presented to validate the controller design at various operating conditions. Results of thermal test on the inverter legs are presented at two different operating conditions.

A GIS (geographical information system)-based spatial data mining approach for optimal location and capacity planning of distributed biomass power generation facilities: A case study of Tumkur district, India

This paper primarily intends to develop a GIS (geographical information system)-based data mining approach for optimally selecting the locations and determining installed capacities for setting up distributed biomass power generation systems in the context of decentralized energy planning for rural regions. The optimal locations within a cluster of villages are obtained by matching the installed capacity needed with the demand for power, minimizing the cost of transportation of biomass from dispersed sources to power generation system, and cost of distribution of electricity from the power generation system to demand centers or villages. The methodology was validated by using it for developing an optimal plan for implementing distributed biomass-based power systems for meeting the rural electricity needs of Tumkur district in India consisting of 2700 villages. The approach uses a k-medoid clustering algorithm to divide the total region into clusters of villages and locate biomass power generation systems at the medoids. The optimal value of k is determined iteratively by running the algorithm for the entire search space for different values of k along with demand-supply matching constraints. The optimal value of the k is chosen such that it minimizes the total cost of system installation, costs of transportation of biomass, and transmission and distribution. A smaller region, consisting of 293 villages was selected to study the sensitivity of the results to varying demand and supply parameters. The results of clustering are represented on a GIS map for the region.

A Three-Level Common-Mode Voltage Eliminated Inverter With Single DC Supply Using Flying Capacitor Inverter and Cascaded H-Bridge

A three-level common-mode voltage eliminated inverter with single dc supply using flying capacitor inverter and cascaded H-bridge has been proposed in this paper. The three phase space vector polygon formed by this configuration and the polygon formed by the common-mode eliminated states have been discussed. The entire system is simulated in Simulink and the results are experimentally verified. This system has an advantage that if one of devices in the H-bridge fails, the system can still be operated as a normal three-level inverter at full power. This inverter has many other advantages like use of single dc supply, making it possible for a back-to-back grid-tied converter application, improved reliability, etc.

Decentralized demand-supply matching using community microgrids and consumer demand response: A scenario analysis

Developing countries constantly face the challenge of reliably matching electricity supply to increasing consumer demand. The traditional policy decisions of increasing supply and reducing demand centrally, by building new power plants and/or load shedding, have been insufficient. Locally installed microgrids along with consumer demand response can be suitable decentralized options to augment the centralized grid based systems and plug the demand-supply gap. The objectives of this paper are to: (1) develop a framework to identify the appropriate decentralized energy options for demand supply matching within a community, and, (2) determine which of these options can suitably plug the existing demand-supply gap at varying levels of grid unavailability. A scenario analysis framework is developed to identify and assess the impact of different decentralized energy options at a community level and demonstrated for a typical urban residential community Vijayanagar, Bangalore in India. A combination of LPG based CHP microgrid and proactive demand response by the community is the appropriate option that enables the Vijayanagar community to meet its energy needs 24/7 in a reliable, cost-effective manner. The paper concludes with an enumeration of the barriers and feasible strategies for the implementation of community microgrids in India based on stakeholder inputs. (C) 2014 Elsevier Ltd. All rights reserved.

Design and Testing of a Control System for Supply Side Electrical Load Management

India's energy demand is increasing rapidly with the intensive growth of economy. The electricity demand in India exceeded the availability, both in terms of base load energy and peak availability. The efficient use of energy source and its conversion and utilizations are the viable alternatives available to the utilities or industry. There are essentially two approaches to electrical energy management. First at the supply / utility end (Supply Side Management or SSM) and the other at the consumer end (Demand Side Management or DSM). This work is based on Supply Side Management (SSM) protocol and consists of design, fabrication and testing of a control device that will be able to automatically regulate the power flow to an individual consumer's premise. This control device can monitor the overuse of electricity (above the connected load or contracted demand) by the individual consumers. The present project work specially emphasizes on contract demand of every consumer and tries to reduce the use beyond the contract demand. This control unit design includes both software and hardware work and designed for 0.5 kW contract demand. The device is tested in laboratory and reveals its potential use in the field.

A low-power, low-cost soil-moisture sensor using dual-probe heat-pulse technique

This paper presents the development and testing of an integrated low-power and low-cost dual-probe heat-pulse (DPHP) soil-moisture sensor in view of the electrical power consumed and affordability in developing countries. A DPHP sensor has two probes: a heater and a temperature sensor probe spaced 3 mm apart from the heater probe. Supply voltage of 3.3V is given to the heater-coil having resistance of 33 Omega power consumption of 330 mW, which is among the lowest in this category of sensors. The heater probe is 40 mm long with 2 mm diameter and hence is stiff enough to be inserted into the soil. The parametric finite element simulation study was performed to ensure that the maximum temperature rise is between 1 degrees C and 5 degrees C for wet and dry soils, respectively. The discrepancy between the simulation and experiment is less than 3.2%. The sensor was validated with white clay and tested with red soil samples to detect volumetric water-content ranging from 0% to 30%. The sensor element is integrated with low-power electronics for amplifying the output from thermocouple sensor and TelosB mote for wireless communication. A 3.7V lithium ion battery with capacity of 1150 mAh is used to power the system. The battery is charged by a 6V and 300 mA solar cell array. Readings were taken in 30 min intervals. The life-time of DPHP sensor node is around 3.6 days. The sensor, encased in 30 mm x 20 mm x 10 mm sized box, and integrated with electronics was tested independently in two separate laboratories for validating as well as investigating the dependence of the measurement of soil-moisture on the density of the soil. The difference in the readings while repeating the experiments was found out to be less than 0.01%. Furthermore, the effect of ambient temperature on the measurement of soil-moisture is studied experimentally and computationally. (C) 2015 Elsevier B.V. All rights reserved.