Implementation of placement and routing algorithms for computer aided design of printed circuit boards

The Printed Circuit Board (PCB) layout design is one of the most important and time consuming phases during equipment design process in all electronic industries. This paper is concerned with the development and implementation of a computer aided PCB design package. A set of programs which operate on a description of the circuit supplied by the user in the form of a data file and subsequently design the layout of a double-sided PCB has been developed. The algorithms used for the design of the PCB optimise the board area and the length of copper tracks used for the interconnections. The output of the package is the layout drawing of the PCB, drawn on a CALCOMP hard copy plotter and a Tektronix 4012 storage graphics display terminal. The routing density (the board area required for one component) achieved by this package is typically 0.8 sq. inch per IC. The package is implemented on a DEC 1090 system in Pascal and FORTRAN and SIGN(1) graphics package is used for display generation.

Theories of moral education and implementation in Indonesia: Re-energizing cultural identity and addressing future challenges

School is regarded as a site of moral training for the younger generation to encounter nation’s future challenges as well as to re-energize nation’s cultural identity. The more competitive global society led by free market trade in terms of ASEAN Economic Community (AEC), requires the school to adapt and change its curriculum more frequently. Like many other countries, Indonesian Ministry of Education and Culture has introduced and nurtured universal values and traditional values respectively through school curriculum reforms to develop students’ ability to participating in global society. This paper will describe classical and contemporary theories related to moral education that have been implemented in Indonesia’s school curriculum and school activities. The theories developed by Durkheim, Alastair MacIntyre, and Basil Bernstein will be discussed. This includes explaining how far the theories have been adopted in Indonesia and how the approaches are currently being used in Indonesian schooling. This paper suggests despite the implementation of those theories in Indonesian schools, the government needs to optimise the operation of those theories to gain significant outcomes.

Implementation of e-learning: A case study of three schools

As Western Australian schools move to implement technology into the classroom, there appears to be prevalence in combining e-learning with face to face traditional classroom practice. This has been accompanied by a shift toward a digital curriculum that incorporates re-usable learning objects. Essential to any teacher contemplating the use of a digital curriculum resource is not only the knowledge of learning theories but models of best practice to create online curriculum for students to use in every day classrooms. This paper explores the e-learning practices in three case study schools (n=3) in Western Australia. Data were collected by observation and interviews (n=11) conducted with the teachers and the ICT co-ordinators, to ascertain their perceptions and experiences with regard to the e-learning environment. There were challenges associated with the implementation of e-learning by teachers into their classroom such as skill development, changes in their role and the pedagogies they employ. The case study schools were pilot schools breaking new ground in order to test a new portal technology. Findings indicated that successful implementation of the e-learning environment was dependent on the four key factors of ICT infrastructure, ICT leadership, support and training initiatives and the teachers’ ICT capacity.

Modified ILMI algorithm for practical PID/PD implementation on a Micro Air Vehicle

This paper extends the iterative linear matrix inequality algorithm (ILMI) for systems having non-ideal PI, PD and PID implementations. The new algorithm uses the practical implementation of the feedback blocksto form the equivalent static output feedback plant. The LMI based synthesis techniques are used in the algorithm to design a multi-loop, multi-objective fixed structure control. The benefits of such a control design technique are brought out by applying it to the lateral stabilizing and tracking feedback control problem of a 30cm wingspan micro air vehicle.

Are organisations prepared for e-health implementation to respond to pandemic influenza?

E-health can facilitate communication and interactions among stakeholders involved in pandemic responses. Its implementation, nevertheless, represents a disruptive change in the healthcare workplace. Organisational preparedness assessment is an essential requirement prior to e-health implementation; including this step in the planning process can increase the chances of programme success. The objective of this study is to develop an e-health preparedness assessment model for pandemic influenza (EHPM4P). Following the Analytic Hierarchy Process (AHP), 20 contextual interviews were conducted with domain experts from May to September 2010. We examined the importance of all preparedness components within a fivedimensional hierarchical framework that was recently published. We also calculated the relative weight for each component at all levels of the hierarchy. This paper presents the hierarchical model (EHPM4P) that can be used to precisely assess healthcare organisational and providers' preparedness for e-health implementation and potentially maximise e-health benefits in the context of an influenza pandemic. Copyright © 2013 Inderscience Enterprises Ltd.

Redefine: Runtime Reconfigurable Polymorphic ASIC

Emerging embedded applications are based on evolving standards (e.g., MPEG2/4, H.264/265, IEEE802.11a/b/g/n). Since most of these applications run on handheld devices, there is an increasing need for a single chip solution that can dynamically interoperate between different standards and their derivatives. In order to achieve high resource utilization and low power dissipation, we propose REDEFINE, a polymorphic ASIC in which specialized hardware units are replaced with basic hardware units that can create the same functionality by runtime re-composition. It is a ``future-proof'' custom hardware solution for multiple applications and their derivatives in a domain. In this article, we describe a compiler framework and supporting hardware comprising compute, storage, and communication resources. Applications described in high-level language (e.g., C) are compiled into application substructures. For each application substructure, a set of compute elements on the hardware are interconnected during runtime to form a pattern that closely matches the communication pattern of that particular application. The advantage is that the bounded CEs are neither processor cores nor logic elements as in FPGAs. Hence, REDEFINE offers the power and performance advantage of an ASIC and the hardware reconfigurability and programmability of that of an FPGA/instruction set processor. In addition, the hardware supports custom instruction pipelining. Existing instruction-set extensible processors determine a sequence of instructions that repeatedly occur within the application to create custom instructions at design time to speed up the execution of this sequence. We extend this scheme further, where a kernel is compiled into custom instructions that bear strong producer-consumer relationship (and not limited to frequently occurring sequences of instructions). Custom instructions, realized as hardware compositions effected at runtime, allow several instances of the same to be active in parallel. A key distinguishing factor in majority of the emerging embedded applications is stream processing. To reduce the overheads of data transfer between custom instructions, direct communication paths are employed among custom instructions. In this article, we present the overview of the hardware-aware compiler framework, which determines the NoC-aware schedule of transports of the data exchanged between the custom instructions on the interconnect. The results for the FFT kernel indicate a 25% reduction in the number of loads/stores, and throughput improves by log(n) for n-point FFT when compared to sequential implementation. Overall, REDEFINE offers flexibility and a runtime reconfigurability at the expense of 1.16x in power and 8x in area when compared to an ASIC. REDEFINE implementation consumes 0.1x the power of an FPGA implementation. In addition, the configuration overhead of the FPGA implementation is 1,000x more than that of REDEFINE.

Development and evaluation of a spatial decision support system for malaria elimination in Bhutan

Background: Bhutan has reduced its malaria incidence significantly in the last 5 years, and is aiming for malaria elimination by 2016. To assist with the management of the Bhutanese malaria elimination programme a spatial decision support system (SDSS) was developed. The current study aims to describe SDSS development and evaluate SDSS utility and acceptability through informant interviews. Methods: The SDSS was developed based on the open-source Quantum geographical information system (QGIS) and piloted to support the distribution of long-lasting insecticidal nets (LLINs) and indoor residual spraying (IRS) in the two sub-districts of Samdrup Jongkhar District. It was subsequently used to support reactive case detection (RACD) in the two sub-districts of Samdrup Jongkhar and two additional sub-districts in Sarpang District. Interviews were conducted to ascertain perceptions on utility and acceptability of 11 informants using the SDSS, including programme and district managers, and field workers. Results: A total of 1502 households with a population of 7165 were enumerated in the four sub-districts, and a total of 3491 LLINs were distributed with one LLIN per 1.7 persons. A total of 279 households representing 728 residents were involved with RACD. Informants considered that the SDSS was an improvement on previous methods for organizing LLIN distribution, IRS and RACD, and could be easily integrated into routine malaria and other vector-borne disease surveillance systems. Informants identified some challenges at the programme and field level, including the need for more skilled personnel to manage the SDSS, and more training to improve the effectiveness of SDSS implementation and use of hardware. Conclusions: The SDSS was well accepted and informants expected its use to be extended to other malaria reporting districts and other vector-borne diseases. Challenges associated with efficient SDSS use included adequate skills and knowledge, access to training and support, and availability of hardware including computers and global positioning system receivers.

COMPASS – A tool for evaluation of compression strategies for embedded processors

A major concern of embedded system architects is the design for low power. We address one aspect of the problem in this paper, namely the effect of executable code compression. There are two benefits of code compression – firstly, a reduction in the memory footprint of embedded software, and secondly, potential reduction in memory bus traffic and power consumption. Since decompression has to be performed at run time it is achieved by hardware. We describe a tool called COMPASS which can evaluate a range of strategies for any given set of benchmarks and display compression ratios. Also, given an execution trace, it can compute the effect on bus toggles, and cache misses for a range of compression strategies. The tool is interactive and allows the user to vary a set of parameters, and observe their effect on performance. We describe an implementation of the tool and demonstrate its effectiveness. To the best of our knowledge this is the first tool proposed for such a purpose.

Experimental implementation of a three qubit quantum game with corrupt source using nuclear magnetic resonance quantum information processor

In a three player quantum `Dilemma' game each player takes independent decisions to maximize his/her individual gain. The optimal strategy in the quantum version of this game has a higher payoff compared to its classical counterpart. However, this advantage is lost if the initial qubits provided to the players are from a noisy source. We have experimentally implemented the three player quantum version of the `Dilemma' game as described by Johnson, [N.F. Johnson, Phys. Rev. A 63 (2001) 020302(R)] using nuclear magnetic resonance quantum information processor and have experimentally verified that the payoff of the quantum game for various levels of corruption matches the theoretical payoff. (c) 2007 Elsevier Inc. All rights reserved.

System-level analysis of network interfaces for hierarchical MPSoCs

Network Interfaces (NIs) are used in Multiprocessor System-on-Chips (MPSoCs) to connect CPUs to a packet switched Network-on-Chip. In this work we introduce a new NI architecture for our hierarchical CoreVA-MPSoC. The CoreVA-MPSoC targets streaming applications in embedded systems. The main contribution of this paper is a system-level analysis of different NI configurations, considering both software and hardware costs for NoC communication. Different configurations of the NI are compared using a benchmark suite of 10 streaming applications. The best performing NI configuration shows an average speedup of 20 for a CoreVA-MPSoC with 32 CPUs compared to a single CPU. Furthermore, we present physical implementation results using a 28 nm FD-SOI standard cell technology. A hierarchical MPSoC with 8 CPU clusters and 4 CPUs in each cluster running at 800MHz requires an area of 4.56mm2.

RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router

A polymorphic ASIC is a runtime reconfigurable hardware substrate comprising compute and communication elements. It is a ldquofuture proofrdquo custom hardware solution for multiple applications and their derivatives in a domain. Interoperability between application derivatives at runtime is achieved through hardware reconfiguration. In this paper we present the design of a single cycle Network on Chip (NoC) router that is responsible for effecting runtime reconfiguration of the hardware substrate. The router design is optimized to avoid FIFO buffers at the input port and loop back at output crossbar. It provides virtual channels to emulate a non-blocking network and supports a simple X-Y relative addressing scheme to limit the control overhead to 9 bits per packet. The 8times8 honeycomb NoC (RECONNECT) implemented in 130 nm UMC CMOS standard cell library operates at 500 MHz and has a bisection bandwidth of 28.5 GBps. The network is characterized for random, self-similar and application specific traffic patterns that model the execution of multimedia and DSP kernels with varying network loads and virtual channels. Our implementation with 4 virtual channels has an average network latency of 24 clock cycles and throughput of 62.5% of the network capacity for random traffic. For application specific traffic the latency is 6 clock cycles and throughput is 87% of the network capacity.

Parallel implementation of AutoDock

Computational docking of ligands to protein structures is a key step in structure-based drug design. Currently, the time required for each docking run is high and thus limits the use of docking in a high-throughput manner, warranting parallelization of docking algorithms. AutoDock, a widely used tool, has been chosen for parallelization. Near-linear increases in speed were observed with 96 processors, reducing the time required for docking ligands to HIV-protease from 81 min, as an example, on a single IBM Power-5 processor ( 1.65 GHz), to about 1 min on an IBM cluster, with 96 such processors. This implementation would make it feasible to perform virtual ligand screening using AutoDock.