A toothless chihuahua? : the Australian Competition and Consumer Commission, neoliberalism and supermarket power in Australia

During the Senate Inquiry into 'milk price wars' in 2011, Senator Nick Xenophon accused the Australian Competition and Consumer Commission (ACCC) of being 'less effective than a toothless Chihuahua'. This follows the ACCC's lack of action regarding the reported abuse of market power of Australia's supermarket duopoly, where an extensive inquiry into the competitiveness of retail prices in 2008 found grocery retailing to be 'workably competitive' despite numerous claims to the contrary. How can farmers' submissions to the inquiry that cite market abuse be reconciled with the ACCC's finding that all is well in the food supply chain? Following an in-depth examination of 53 farmer submissions to the inquiry, we conclude that the findings of the ACCC are commensurate with the neoliberal economisation of the political sphere, where commercial entities 'legitimately' govern beyond their corporate boundaries, often using disciplinary measures that were once exclusive to governments. We argue that such clear structural inequalities between farmers and major corporations is reason to re-regulate markets and reinsert a stronger role for government to 'level the playing field'.

A SiC-based matrix converter topology for inductive power transfer system

Typical inductive power transfer (IPT) systems employ two power conversion stages to generate a high-frequency primary current from low-frequency utility supply. This paper proposes a matrix-converter-based IPT system, which employs high-speed SiC devices to facilitate the generation of high-frequency current through a single power conversion stage. The proposed matrix converter topology transforms a three-phase low-frequency voltage system to a high-frequency single-phase voltage, which, in turn, powers a series compensated IPT system. A comprehensive mathematical model is developed and power losses are evaluated to investigate the efficiency of the proposed converter topology. Theoretical results are presented with simulations, which are performed in MATLAB/Simulink, in comparison to a conventional two-stage converter. Experimental evident of a prototype IPT system is also presented to demonstrate the applicability of the proposed concept.

A matrix converter based Inductive Power Transfer system

Typical Inductive Power Transfer (IPT) systems employ two power conversion stages to generate a high frequency current from low frequency utility supply. This paper proposes a matrix converter based IPT system that facilitates the generation of high frequency current through a single power conversion stage. The proposed matrix converter topology transforms a 3-phase low frequency voltage system to a high frequency single phase voltage which in turn powers a series compensated IPT system. A comprehensive mathematical model is developed to investigate the behavior of the proposed IPT topology. Theoretical results are presented in comparison to simulations, which are performed in Matlab/ Simulink, to demonstrate the applicability of the proposed concept and the validity of the developed model.

On the design of power buffer and its applications

A power electronics-based buffer is examined in which through control of its PWM converters, the buffer-load combination is driven to operate under either constant power or constant impedance modes. A battery, incorporated within the buffer, provides the energy storage facility to facilitate the necessary power flow control. Real power demand from upstream supply is regulated under fault condition, and the possibility of voltage or network instability is reduced. The proposed buffer is also applied to a wind farm. It is shown that the buffer stabilizes the power contribution from the farm. Based on a battery cost-benefit analysis, a method is developed to determine the optimal level of the power supplied from the wind farm and the corresponding capacity of the battery storage system.

Modeling and control of a robotic power line inspection vehicle

Power line inspection is a vital function for electricity supply companies but it involves labor-intensive and expensive procedures which are tedious and error-prone for humans to perform. A possible solution is to use an unmanned aerial vehicle (UAV) equipped with video surveillance equipment to perform the inspection. This paper considers how a small, electrically driven rotorcraft conceived for this application could be controlled by visually tracking the overhead supply lines. A dynamic model for a ducted-fan rotorcraft is presented and used to control the action of an Air Vehicle Simulator (AVS), consisting of a cable-array robot. Results show how visual data can be used to determine, and hence regulate in closed loop, the simulated vehicle’s position relative to the overhead lines.

Protective legal regulation for home-based workers in Australian textile, clothing and footwear supply chains

Supply chain outsourcing has posed problems for conventional labour regulation, which focuses on employers contracting directly with workers, particularly employees. These difficulties have been exacerbated by the traditional trifurcated approach to regulation of pay and conditions, work health and safety and workers’ compensation. This paper analyses the parallel interaction of two legal developments within the Australian textile, clothing and footwear industry. The first is mandatory contractual tracking mechanisms within state and federal labour laws and the second is the duties imposed by the harmonised Work Health and Safety Acts. Their combined effect has created an innovative, fully enforceable and integrated regulatory framework for the textile, clothing and footwear industry and, it is argued, other supply chains in different industry contexts. This paper highlights how regulatory solutions can address adverse issues for workers at the bottom of contractual networks, such as fissured workplaces and capital fragmentation, by enabling regulators to harness the commercial power of business controllers at the apex to ensure compliance throughout the entire chain.

Latency, Power and Performance Trade-offs in Network-on-Chips by Link Microarchitecture Exploration

This paper presents a power, latency and throughput trade-off study on NoCs by varying microarchitectural (e.g. pipelining) and circuit level (e.g. frequency and voltage) parameters. We change pipelining depth, operating frequency and supply voltage for 3 example NoCs - 16 node 2D Torus, Tree network and Reduced 2D Torus. We use an in-house NoC exploration framework capable of topology generation and comparison using parameterized models of Routers and links developed in SystemC. The framework utilizes interconnect power and delay models from a low-level modelling tool called Intacte[1]1. We find that increased pipelining can actually reduce latency. We also find that there exists an optimal degree of pipelining which is the most energy efficient in terms of minimizing energy-delay product.

A Dual Seven-Level Inverter Supply for an Open-End Winding Induction Motor Drive

This paper develops a seven-level inverter structure for open-end winding induction motor drives. The inverter supply is realized by cascading four two-level and two three-level neutral-point-clamped inverters. The inverter control is designed in such a way that the common-mode voltage (CMV) is eliminated. DC-link capacitor voltage balancing is also achieved by using only the switching-state redundancies. The proposed power circuit structure is modular and therefore suitable for fault-tolerant applications. By appropriately isolating some of the inverters, the drive can be operated during fault conditions in a five-level or a three-level inverter mode, with preserved CMV elimination and DC-link capacitor voltage balancing, within a reduced modulation range.

Regulating supply chains to protect road transport workers: An early assessment of the road safety remuneration tribunal

The Road Safety Remuneration Act 2012 (Cth) (the Act) explicitly enables the Road Safety Remuneration Tribunal to make orders that can impose binding requirements on all the participants in the road transport supply chain, including consignors and consignees at the apex the chain, for the pay and safety of both employee and independent contractor drivers. The tribunal is also specifically empowered to make enforceable orders to reduce or remove remuneration related incentives and pressures that contribute to unsafe work practices in the road transport industry. Recently the tribunal handed down its first order. The article considers whether, and the degree to which, the tribunal has been willing to exercise its explicit power to impose enforceable obligations on consignors and consignees — such as large supermarket chains — at the apex of road transport supply chains. It examines the substance and extent of the obligations imposed by the tribunal, including whether the tribunal has exercised the full range of powers vested in it by the Act. We contend that the tribunal’s first order primarily imposes obligations on direct work providers and drivers without making large, powerful consignors and consignees substantively responsible for driver pay and safety. We argue that the tribunal’s first order could have more comprehensively fulfilled the objectives of the Act by more directly addressing the root causes of low pay and poor safety in the road transport industry.

A 100MHz to 1GHz, 0.35V to 1.5V supply 256 x 64 SRAM mock using symmetrized 9T SRAM cell with controlled read

In this paper, we present Dynamic Voltage and Frequency Managed 256 x 64 SRAM block in 65nm technology, for frequency ranging from 100MHz to 1GHz. The total energy is minimized for any operating frequency in the above range and leakage energy is minimized during standby mode. Since noise margin of SRAM cell deteriorates at low voltages, we propose Static Noise Margin improvement circuitry, which symmetrizes the SRAM cell by controlling the body bias of pull down NMOS transistor. We used a 9T SRAM cell that isolates Read and Hold Noise Margin and has less leakage. We have implemented an efficient technique of pushing address decoder into zigzag-super-cut-off in stand-by mode without affecting its performance in active mode of operation. The Read Bit Line (RBL) voltage drop is controlled and pre-charge of bit lines is done only when needed for reducing power wastage.

Low Power continuous time common mode sensing for common mode feedback circuits

Continuous common mode feedback (CMFB) circuits having high input impedance and low distortion are proposed. The proposed circuits are characterized for 0.18 mu m CMOS process with 1.8 V supply. Simulation results indicate that the proposed common mode detector consumes no standby power and CMFB circuit consumes 27-34% less power than previous high swing CMFB circuits.

A System-C based Micro architectural Exploration Framework for Latency, Power and Performance Trade-offs of On-Chip Interconnection

We describe a System-C based framework we are developing, to explore the impact of various architectural and microarchitectural level parameters of the on-chip interconnection network elements on its power and performance. The framework enables one to choose from a variety of architectural options like topology, routing policy, etc., as well as allows experimentation with various microarchitectural options for the individual links like length, wire width, pitch, pipelining, supply voltage and frequency. The framework also supports a flexible traffic generation and communication model. We provide preliminary results of using this framework to study the power, latency and throughput of a 4x4 multi-core processing array using mesh, torus and folded torus, for two different communication patterns of dense and sparse linear algebra. The traffic consists of both Request-Response messages (mimicing cache accesses)and One-Way messages. We find that the average latency can be reduced by increasing the pipeline depth, as it enables higher link frequencies. We also find that there exists an optimum degree of pipelining which minimizes energy-delay product.

A 100MHz to 1GHz, 0.35V to 1.5V Supply 256 x 64 SRAM Block Using Symmetrized 9T SRAM Cell with Controlled Read

In this paper, we present dynamic voltage and frequency Managed 256 x 64 SRAM block in 65 nm technology, for frequency ranging from 100 MHz to 1 GHz. The total energy is minimized for any operating frequency in the above range and leakage energy is minimized during standby mode. Since noise margin of SRAM cell deteriorates at low voltages, we propose static noise margin improvement circuitry, which symmetrizes the SRAM cell by controlling the body bias of pull down NMOS transistor. We used a 9T SRAM cell that isolates Read and hold noise margin and has less leakage. We have implemented an efficient technique of pushing address decoder into zigzag- super-cut-off in stand-by mode without affecting its performance in active mode of operation. The read bit line (RBL) voltage drop is controlled and pre-charge of bit lines is done only when needed for reducing power wastage.

A Low Power Frequency Multiplication Technique for Zigbee Transceiver

A low-power frequency multiplication technique, developed for ZigBee (IEEE 802.15.4) like applications is presented. We have provided an estimate for the power consumption for a given output voltage swing using our technique. The advantages and disadvantages which determine the application areas of the technique are discussed. The issues related to design, layout and process variation are also addressed. Finally, a design is presented for operation in 2.405-2.485-GHz band of ZigBee receiver. SpectreRF simulations show 30% improvement in efficiency for our circuit with regard to conversion of DC bias current to output amplitude, against a LC-VCO. To establish the low-power credentials, we have compared our circuit with an existing technique; our circuit performs better with just 1/3 of total current from supply, and uses one inductor as against three in the latter case. A test chip was implemented in UMC 0.13-mum RF process with spiral on-chip inductors and MIM (metal-insulator-metal) capacitor option.

A Five-Level Inverter Topology with Single-DC Supply by Cascading a Flying Capacitor Inverter and an H-Bridge

In this paper, a new three-phase, five-level inverter topology with a single-dc source is presented. The proposed topology is obtained by cascading a three-level flying capacitor inverter with a flying H-bridge power cell in each phase. This topology has redundant switching states for generating different pole voltages. By selecting appropriate switching states, the capacitor voltages can be balanced instantaneously (as compared to the fundamental) in any direction of the current, irrespective of the load power factor. Another important feature of this topology is that if any H-bridge fails, it can be bypassed and the configuration can still operate as a three-level inverter at its full power rating. This feature improves the reliability of the circuit. A 3-kW induction motor is run with the proposed topology for the full modulation range. The effectiveness of the capacitor balancing algorithm is tested for the full range of speed and during the sudden acceleration of the motor.