Utilização de um aplicativo de simulação computacional na avaliação de desempenho térmico de protótipo de habitação de interesse social (his)

This Masters Degree dissertation seeks to make a comparative study of internal air temperature data, simulated through the thermal computer application DesignBuilder 1.2, and data registered in loco through HOBO® Temp Data Logger, in a Social Housing Prototype (HIS), located at the Central Campus of the Federal University of Rio Grande do Norte UFRN. The prototype was designed and built seeking strategies of thermal comfort recommended for the local climate where the study was carried out, and built with panels of cellular concrete by Construtora DoisA, a collaborator of research project REPESC Rede de Pesquisa em Eficiência Energética de Sistemas Construtivos (Research Network on Energy Efficiency of Construction Systems), an integral part of Habitare program. The methodology employed carefully examined the problem, reviewed the bibliography, analyzing the major aspects related to computer simulations for thermal performance of buildings, such as climate characterization of the region under study and users thermal comfort demands. The DesignBuilder 1.2 computer application was used as a simulation tool, and theoretical alterations were carried out in the prototype, then they were compared with the parameters of thermal comfort adopted, based on the area s current technical literature. Analyses of the comparative studies were performed through graphical outputs for a better understanding of air temperature amplitudes and thermal comfort conditions. The data used for the characterization of external air temperature were obtained from the Test Reference Year (TRY), defined for the study area (Natal-RN). Thus the author also performed comparative studies for TRY data registered in the years 2006, 2007 and 2008, at weather station Davis Precision Station, located at the Instituto Nacional de Pesquisas Espaciais INPE-CRN (National Institute of Space Research), in a neighboring area of UFRN s Central Campus. The conclusions observed from the comparative studies performed among computer simulations, and the local records obtained from the studied prototype, point out that the simulations performed in naturally ventilated buildings is quite a complex task, due to the applications limitations, mainly owed to the complexity of air flow phenomena, the influence of comfort conditions in the surrounding areas and climate records. Lastly, regarding the use of the application DesignBuilder 1.2 in the present study, one may conclude that it is a good tool for computer simulations. However, it needs some adjustments to improve reliability in its use. There is a need for continued research, considering the dedication of users to the prototype, as well as the thermal charges of the equipment, in order to check sensitivity

A three dimensional model of Caspian Sea circulation

Observations of Caspian Sea during August - September 1995 are used to develop a three dimensional numerical for calculating temperature and current. This period was chosen because of extensive set of observational data including surface temperature observations. Data from the meteorological buoy network on Caspian Sea are combined with routine observation at first order synoptic station around the lake to obtain hourly values of wind stress and pressure fields. Initial temperature distribution as a function of depth and horizontal coordinates are derived from ship cruises. The model has variable grid resolution and horizontal smoothing which filters out small scale vertical motion. The hydrodynamic model of Caspian Sea has 6 vertical levels and a uniform horizontal grid size of 50 km The model is driven with surface fluxes of heat and momentum derived from observed meteorological. The model was able to reproduce all of the basic feature of the thermal structure in Caspian sea and: larger scale circulation patterns tend to be cyclone, with cyclone circulation with each sub basin. Result has agreement with observations.

Low-power high-performance SAR ADC design with digital calibration techniques

This dissertation presents the design of three high-performance successive-approximation-register (SAR) analog-to-digital converters (ADCs) using distinct digital background calibration techniques under the framework of a generalized code-domain linear equalizer. These digital calibration techniques effectively and efficiently remove the static mismatch errors in the analog-to-digital (A/D) conversion. They enable aggressive scaling of the capacitive digital-to-analog converter (DAC), which also serves as sampling capacitor, to the kT/C limit. As a result, outstanding conversion linearity, high signal-to-noise ratio (SNR), high conversion speed, robustness, superb energy efficiency, and minimal chip-area are accomplished simultaneously. The first design is a 12-bit 22.5/45-MS/s SAR ADC in 0.13-μm CMOS process. It employs a perturbation-based calibration based on the superposition property of linear systems to digitally correct the capacitor mismatch error in the weighted DAC. With 3.0-mW power dissipation at a 1.2-V power supply and a 22.5-MS/s sample rate, it achieves a 71.1-dB signal-to-noise-plus-distortion ratio (SNDR), and a 94.6-dB spurious free dynamic range (SFDR). At Nyquist frequency, the conversion figure of merit (FoM) is 50.8 fJ/conversion step, the best FoM up to date (2010) for 12-bit ADCs. The SAR ADC core occupies 0.06 mm2, while the estimated area the calibration circuits is 0.03 mm2. The second proposed digital calibration technique is a bit-wise-correlation-based digital calibration. It utilizes the statistical independence of an injected pseudo-random signal and the input signal to correct the DAC mismatch in SAR ADCs. This idea is experimentally verified in a 12-bit 37-MS/s SAR ADC fabricated in 65-nm CMOS implemented by Pingli Huang. This prototype chip achieves a 70.23-dB peak SNDR and an 81.02-dB peak SFDR, while occupying 0.12-mm2 silicon area and dissipating 9.14 mW from a 1.2-V supply with the synthesized digital calibration circuits included. The third work is an 8-bit, 600-MS/s, 10-way time-interleaved SAR ADC array fabricated in 0.13-μm CMOS process. This work employs an adaptive digital equalization approach to calibrate both intra-channel nonlinearities and inter-channel mismatch errors. The prototype chip achieves 47.4-dB SNDR, 63.6-dB SFDR, less than 0.30-LSB differential nonlinearity (DNL), and less than 0.23-LSB integral nonlinearity (INL). The ADC array occupies an active area of 1.35 mm2 and dissipates 30.3 mW, including synthesized digital calibration circuits and an on-chip dual-loop delay-locked loop (DLL) for clock generation and synchronization.

Microfluidic platforms for the characterization of in meso membrane protein crystallization

Membrane proteins, which reside in the membranes of cells, play a critical role in many important biological processes including cellular signaling, immune response, and material and energy transduction. Because of their key role in maintaining the environment within cells and facilitating intercellular interactions, understanding the function of these proteins is of tremendous medical and biochemical significance. Indeed, the malfunction of membrane proteins has been linked to numerous diseases including diabetes, cirrhosis of the liver, cystic fibrosis, cancer, Alzheimer's disease, hypertension, epilepsy, cataracts, tubulopathy, leukodystrophy, Leigh syndrome, anemia, sensorineural deafness, and hypertrophic cardiomyopathy.1-3 However, the structure of many of these proteins and the changes in their structure that lead to disease-related malfunctions are not well understood. Additionally, at least 60% of the pharmaceuticals currently available are thought to target membrane proteins, despite the fact that their exact mode of operation is not known.4-6 Developing a detailed understanding of the function of a protein is achieved by coupling biochemical experiments with knowledge of the structure of the protein. Currently the most common method for obtaining three-dimensional structure information is X-ray crystallography. However, no a priori methods are currently available to predict crystallization conditions for a given protein.7-14 This limitation is currently overcome by screening a large number of possible combinations of precipitants, buffer, salt, and pH conditions to identify conditions that are conducive to crystal nucleation and growth.7,9,11,15-24 Unfortunately, these screening efforts are often limited by difficulties associated with quantity and purity of available protein samples. While the two most significant bottlenecks for protein structure determination in general are the (i) obtaining sufficient quantities of high quality protein samples and (ii) growing high quality protein crystals that are suitable for X-ray structure determination,7,20,21,23,25-47 membrane proteins present additional challenges. For crystallization it is necessary to extract the membrane proteins from the cellular membrane. However, this process often leads to denaturation. In fact, membrane proteins have proven to be so difficult to crystallize that of the more than 66,000 structures deposited in the Protein Data Bank,48 less than 1% are for membrane proteins, with even fewer present at high resolution (< 2Å)4,6,49 and only a handful are human membrane proteins.49 A variety of strategies including detergent solubilization50-53 and the use of artificial membrane-like environments have been developed to circumvent this challenge.43,53-55 In recent years, the use of a lipidic mesophase as a medium for crystallizing membrane proteins has been demonstrated to increase success for a wide range of membrane proteins, including human receptor proteins.54,56-62 This in meso method for membrane protein crystallization, however, is still by no means routine due to challenges related to sample preparation at sub-microliter volumes and to crystal harvesting and X-ray data collection. This dissertation presents various aspects of the development of a microfluidic platform to enable high throughput in meso membrane protein crystallization at a level beyond the capabilities of current technologies. Microfluidic platforms for protein crystallization and other lab-on-a-chip applications have been well demonstrated.9,63-66 These integrated chips provide fine control over transport phenomena and the ability to perform high throughput analyses via highly integrated fluid networks. However, the development of microfluidic platforms for in meso protein crystallization required the development of strategies to cope with extremely viscous and non-Newtonian fluids. A theoretical treatment of highly viscous fluids in microfluidic devices is presented in Chapter 3, followed by the application of these strategies for the development of a microfluidic mixer capable of preparing a mesophase sample for in meso crystallization at a scale of less than 20 nL in Chapter 4. This approach was validated with the successful on chip in meso crystallization of the membrane protein bacteriorhodopsin. In summary, this is the first report of a microfluidic platform capable of performing in meso crystallization on-chip, representing a 1000x reduction in the scale at which mesophase trials can be prepared. Once protein crystals have formed, they are typically harvested from the droplet they were grown in and mounted for crystallographic analysis. Despite the high throughput automation present in nearly all other aspects of protein structure determination, the harvesting and mounting of crystals is still largely a manual process. Furthermore, during mounting the fragile protein crystals can potentially be damaged, both from physical and environmental shock. To circumvent these challenges an X-ray transparent microfluidic device architecture was developed to couple the benefits of scale, integration, and precise fluid control with the ability to perform in situ X-ray analysis (Chapter 5). This approach was validated successfully by crystallization and subsequent on-chip analysis of the soluble proteins lysozyme, thaumatin, and ribonuclease A and will be extended to microfluidic platforms for in meso membrane protein crystallization. The ability to perform in situ X-ray analysis was shown to provide extremely high quality diffraction data, in part as a result of not being affected by damage due to physical handling of the crystals. As part of the work described in this thesis, a variety of data collection strategies for in situ data analysis were also tested, including merging of small slices of data from a large number of crystals grown on a single chip, to allow for diffraction analysis at biologically relevant temperatures. While such strategies have been applied previously,57,59,61,67 they are potentially challenging when applied via traditional methods due to the need to grow and then mount a large number of crystals with minimal crystal-to-crystal variability. The integrated nature of microfluidic platforms easily enables the generation of a large number of reproducible crystallization trials. This, coupled with in situ analysis capabilities has the potential of being able to acquire high resolution structural data of proteins at biologically relevant conditions for which only small crystals, or crystals which are adversely affected by standard cryocooling techniques, could be obtained (Chapters 5 and 6). While the main focus of protein crystallography is to obtain three-dimensional protein structures, the results of typical experiments provide only a static picture of the protein. The use of polychromatic or Laue X-ray diffraction methods enables the collection of time resolved structural information. These experiments are very sensitive to crystal quality, however, and often suffer from severe radiation damage due to the intense polychromatic X-ray beams. Here, as before, the ability to perform in situ X-ray analysis on many small protein crystals within a microfluidic crystallization platform has the potential to overcome these challenges. An automated method for collecting a "single-shot" of data from a large number of crystals was developed in collaboration with the BioCARS team at the Advanced Photon Source at Argonne National Laboratory (Chapter 6). The work described in this thesis shows that, even more so than for traditional structure determination efforts, the ability to grow and analyze a large number of high quality crystals is critical to enable time resolved structural studies of novel proteins. In addition to enabling X-ray crystallography experiments, the development of X-ray transparent microfluidic platforms also has tremendous potential to answer other scientific questions, such as unraveling the mechanism of in meso crystallization. For instance, the lipidic mesophases utilized during in meso membrane protein crystallization can be characterized by small angle X-ray diffraction analysis. Coupling in situ analysis with microfluidic platforms capable of preparing these difficult mesophase samples at very small volumes has tremendous potential to enable the high throughput analysis of these systems on a scale that is not reasonably achievable using conventional sample preparation strategies (Chapter 7). In collaboration with the LS-CAT team at the Advanced Photon Source, an experimental station for small angle X-ray analysis coupled with the high quality visualization capabilities needed to target specific microfluidic samples on a highly integrated chip is under development. Characterizing the phase behavior of these mesophase systems and the effects of various additives present in crystallization trials is key for developing an understanding of how in meso crystallization occurs. A long term goal of these studies is to enable the rational design of in meso crystallization experiments so as to avoid or limit the need for high throughput screening efforts. In summary, this thesis describes the development of microfluidic platforms for protein crystallization with in situ analysis capabilities. Coupling the ability to perform in situ analysis with the small scale, fine control, and the high throughput nature of microfluidic platforms has tremendous potential to enable a new generation of crystallographic studies and facilitate the structure determination of important biological targets. The development of platforms for in meso membrane protein crystallization is particularly significant because they enable the preparation of highly viscous mixtures at a previously unachievable scale. Work in these areas is ongoing and has tremendous potential to improve not only current the methods of protein crystallization and crystallography, but also to enhance our knowledge of the structure and function of proteins which could have a significant scientific and medical impact on society as a whole. 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Optimisation of digitally coded test vectors for mixed-signal components

International audience

Perspetivas da comunidade do autismo em relação à investigação em autismo

Dada a sua elevada prevalência global (cerca de 1 em 100), gravidade e complexidade etiológica, o autismo é hoje uma importante área de investigação. O presente trabalho teve como objetivo compreender quais as preocupações éticas, perspetivas e expetativas de pais e profissionais da saúde e educadores ligados ao autismo, no que diz respeito à investigação desta patologia. O trabalho foi desenvolvido no âmbito de uma rede de investigação europeia sobre sinais precoces de autismo. Em paralelo em vários países da Europa, foram identificados os tópicos de maior interesse para pais e profissionais através de grupos de foco, na sequência dos quais se elaborou um inquérito online que foi distribuído por esta comunidade ligada ao autismo. Em Portugal, os inquiridos (n=331) mostraram um interesse global pela investigação em autismo, nomeadamente sobre as bases genéticas e sobre sinais precoces de autismo. Relativamente aos benefícios resultantes da participação em projetos de investigação, os pais privilegiaram o acesso a intervenção e a formação pessoal, enquanto que os profissionais deram mais importância ao acesso a mais conhecimento e a equipas especializadas. Os três grupos deram ênfase ao acesso à informação completa obtida durante a investigação e às conclusões gerais do estudo. Os resultados obtidos reforçam a importância da investigação do autismo, indicando também linhas claras de atuação que têm em observação as perspetivas da comunidade ligada ao autismo.

Thermal Tracking and Estimation for Microprocessors

Due to increasing integration density and operating frequency of today's high performance processors, the temperature of a typical chip can easily exceed 100 degrees Celsius. However, the runtime thermal state of a chip is very hard to predict and manage due to the random nature in computing workloads, as well as the process, voltage and ambient temperature variability (together called PVT variability). The uneven nature (both in time and space) of the heat dissipation of the chip could lead to severe reliability issues and error-prone chip behavior (e.g. timing errors). Many dynamic power/thermal management techniques have been proposed to address this issue such as dynamic voltage and frequency scaling (DVFS), clock gating and etc. However, most of such techniques require accurate knowledge of the runtime thermal state of the chip to make efficient and effective control decisions. In this work we address the problem of tracking and managing the temperature of microprocessors which include the following sub-problems: (1) how to design an efficient sensor-based thermal tracking system on a given design that could provide accurate real-time temperature feedback; (2) what statistical techniques could be used to estimate the full-chip thermal profile based on very limited (and possibly noise-corrupted) sensor observations; (3) how do we adapt to changes in the underlying system's behavior, since such changes could impact the accuracy of our thermal estimation. The thermal tracking methodology proposed in this work is enabled by on-chip sensors which are already implemented in many modern processors. We first investigate the underlying relationship between heat distribution and power consumption, then we introduce an accurate thermal model for the chip system. Based on this model, we characterize the temperature correlation that exists among different chip modules and explore statistical approaches (such as those based on Kalman filter) that could utilize such correlation to estimate the accurate chip-level thermal profiles in real time. Such estimation is performed based on limited sensor information because sensors are usually resource constrained and noise-corrupted. We also took a further step to extend the standard Kalman filter approach to account for (1) nonlinear effects such as leakage-temperature interdependency and (2) varying statistical characteristics in the underlying system model. The proposed thermal tracking infrastructure and estimation algorithms could consistently generate accurate thermal estimates even when the system is switching among workloads that have very distinct characteristics. Through experiments, our approaches have demonstrated promising results with much higher accuracy compared to existing approaches. Such results can be used to ensure thermal reliability and improve the effectiveness of dynamic thermal management techniques.

Measurement of finite-frequency current statistics in a single-electron transistor

Electron transport in nanoscale structures is strongly influenced by the Coulomb interaction that gives rise to correlations in the stream of charges and leaves clear fingerprints in the fluctuations of the electrical current. A complete understanding of the underlying physical processes requires measurements of the electrical fluctuations on all time and frequency scales, but experiments have so far been restricted to fixed frequency ranges, as broadband detection of current fluctuations is an inherently difficult experimental procedure. Here we demonstrate that the electrical fluctuations in a single-electron transistor can be accurately measured on all relevant frequencies using a nearby quantum point contact for on-chip real-time detection of the current pulses in the single-electron device. We have directly measured the frequency-dependent current statistics and, hereby, fully characterized the fundamental tunnelling processes in the single-electron transistor. Our experiment paves the way for future investigations of interaction and coherence-induced correlation effects in quantum transport.

Components and circuits for tunneling diode based high frequency sources

Terahertz (THz) technology has been generating a lot of interest because of the potential applications for systems working in this frequency range. However, to fully achieve this potential, effective and efficient ways of generating controlled signals in the terahertz range are required. Devices that exhibit negative differential resistance (NDR) in a region of their current-voltage (I-V ) characteristics have been used in circuits for the generation of radio frequency signals. Of all of these NDR devices, resonant tunneling diode (RTD) oscillators, with their ability to oscillate in the THz range are considered as one of the most promising solid-state sources for terahertz signal generation at room temperature. There are however limitations and challenges with these devices, from inherent low output power usually in the range of micro-watts (uW) for RTD oscillators when milli-watts (mW) are desired. At device level, parasitic oscillations caused by the biasing line inductance when the device is biased in the NDR region prevent accurate device characterisation, which in turn prevents device modelling for computer simulations. This thesis describes work on I-V characterisation of tunnel diode (TD) and RTD (fabricated by Dr. Jue Wang) devices, and the radio frequency (RF) characterisation and small signal modelling of RTDs. The thesis also describes the design and measurement of hybrid TD oscillators for higher output power and the design and measurement of a planar Yagi antenna (fabricated by Khalid Alharbi) for THz applications. To enable oscillation free current-voltage characterisation of tunnel diodes, a commonly employed method is the use of a suitable resistor connected across the device to make the total differential resistance in the NDR region positive. However, this approach is not without problems as the value of the resistor has to satisfy certain conditions or else bias oscillations would still be present in the NDR region of the measured I-V characteristics. This method is difficult to use for RTDs which are fabricated on wafer due to the discrepancies in designed and actual resistance values of fabricated resistors using thin film technology. In this work, using pulsed DC rather than static DC measurements during device characterisation were shown to give accurate characteristics in the NDR region without the need for a stabilisation resistor. This approach allows for direct oscillation free characterisation for devices. Experimental results show that the I-V characterisation of tunnel diodes and RTD devices free of bias oscillations in the NDR region can be made. In this work, a new power-combining topology to address the limitations of low output power of TD and RTD oscillators is presented. The design employs the use of two oscillators biased separately, but with the combined output power from both collected at a single load. Compared to previous approaches, this method keeps the frequency of oscillation of the combined oscillators the same as for one of the oscillators. Experimental results with a hybrid circuit using two tunnel diode oscillators compared with a single oscillator design with similar values shows that the coupled oscillators produce double the output RF power of the single oscillator. This topology can be scaled for higher (up to terahertz) frequencies in the future by using RTD oscillators. Finally, a broadband Yagi antenna suitable for wireless communication at terahertz frequencies is presented in this thesis. The return loss of the antenna showed that the bandwidth is larger than the measured range (140-220 GHz). A new method was used to characterise the radiation pattern of the antenna in the E-plane. This was carried out on-wafer and the measured radiation pattern showed good agreement with the simulated pattern. In summary, this work makes important contributions to the accurate characterisation and modelling of TDs and RTDs, circuit-based techniques for power combining of high frequency TD or RTD oscillators, and to antennas suitable for on chip integration with high frequency oscillators.

Data structures for SIMD logic simulation

Due to the growth of design size and complexity, design verification is an important aspect of the Logic Circuit development process. The purpose of verification is to validate that the design meets the system requirements and specification. This is done by either functional or formal verification. The most popular approach to functional verification is the use of simulation based techniques. Using models to replicate the behaviour of an actual system is called simulation. In this thesis, a software/data structure architecture without explicit locks is proposed to accelerate logic gate circuit simulation. We call thus system ZSIM. The ZSIM software architecture simulator targets low cost SIMD multi-core machines. Its performance is evaluated on the Intel Xeon Phi and 2 other machines (Intel Xeon and AMD Opteron). The aim of these experiments is to: • Verify that the data structure used allows SIMD acceleration, particularly on machines with gather instructions ( section 5.3.1). • Verify that, on sufficiently large circuits, substantial gains could be made from multicore parallelism ( section 5.3.2 ). • Show that a simulator using this approach out-performs an existing commercial simulator on a standard workstation ( section 5.3.3 ). • Show that the performance on a cheap Xeon Phi card is competitive with results reported elsewhere on much more expensive super-computers ( section 5.3.5 ). To evaluate the ZSIM, two types of test circuits were used: 1. Circuits from the IWLS benchmark suit [1] which allow direct comparison with other published studies of parallel simulators.2. Circuits generated by a parametrised circuit synthesizer. The synthesizer used an algorithm that has been shown to generate circuits that are statistically representative of real logic circuits. The synthesizer allowed testing of a range of very large circuits, larger than the ones for which it was possible to obtain open source files. The experimental results show that with SIMD acceleration and multicore, ZSIM gained a peak parallelisation factor of 300 on Intel Xeon Phi and 11 on Intel Xeon. With only SIMD enabled, ZSIM achieved a maximum parallelistion gain of 10 on Intel Xeon Phi and 4 on Intel Xeon. Furthermore, it was shown that this software architecture simulator running on a SIMD machine is much faster than, and can handle much bigger circuits than a widely used commercial simulator (Xilinx) running on a workstation. The performance achieved by ZSIM was also compared with similar pre-existing work on logic simulation targeting GPUs and supercomputers. It was shown that ZSIM simulator running on a Xeon Phi machine gives comparable simulation performance to the IBM Blue Gene supercomputer at very much lower cost. The experimental results have shown that the Xeon Phi is competitive with simulation on GPUs and allows the handling of much larger circuits than have been reported for GPU simulation. When targeting Xeon Phi architecture, the automatic cache management of the Xeon Phi, handles and manages the on-chip local store without any explicit mention of the local store being made in the architecture of the simulator itself. However, targeting GPUs, explicit cache management in program increases the complexity of the software architecture. Furthermore, one of the strongest points of the ZSIM simulator is its portability. Note that the same code was tested on both AMD and Xeon Phi machines. The same architecture that efficiently performs on Xeon Phi, was ported into a 64 core NUMA AMD Opteron. To conclude, the two main achievements are restated as following: The primary achievement of this work was proving that the ZSIM architecture was faster than previously published logic simulators on low cost platforms. The secondary achievement was the development of a synthetic testing suite that went beyond the scale range that was previously publicly available, based on prior work that showed the synthesis technique is valid.

The third dimension: new developments in cell culture models for colorectal research

Cellular models are important tools in various research areas related to colorectal biology and associated diseases. Herein, we review the most widely used cell lines and the different techniques to grow them, either as cell monolayer, polarized two-dimensional epithelia on membrane filters, or as three-dimensional spheres in scaffoldfree or matrix-supported culture conditions. Moreover, recent developments, such as gut-on-chip devices or the ex vivo growth of biopsy-derived organoids, are also discussed. We provide an overview on the potential applications but also on the limitations for each of these techniques, while evaluating their contribution to provide more reliable cellular models for research, diagnostic testing, or pharmacological validation related to colon physiology and pathophysiology.

Algorithme de branch-and-price-and-cut pour le problème de conception de réseaux avec coûts fixes, capacités et un seul produit

De nombreux problèmes liés aux domaines du transport, des télécommunications et de la logistique peuvent être modélisés comme des problèmes de conception de réseaux. Le problème classique consiste à transporter un flot (données, personnes, produits, etc.) sur un réseau sous un certain nombre de contraintes dans le but de satisfaire la demande, tout en minimisant les coûts. Dans ce mémoire, on se propose d'étudier le problème de conception de réseaux avec coûts fixes, capacités et un seul produit, qu'on transforme en un problème équivalent à plusieurs produits de façon à améliorer la valeur de la borne inférieure provenant de la relaxation continue du modèle. La méthode que nous présentons pour la résolution de ce problème est une méthode exacte de branch-and-price-and-cut avec une condition d'arrêt, dans laquelle nous exploitons à la fois la méthode de génération de colonnes, la méthode de génération de coupes et l'algorithme de branch-and-bound. Ces méthodes figurent parmi les techniques les plus utilisées en programmation linéaire en nombres entiers. Nous testons notre méthode sur deux groupes d'instances de tailles différentes (gran-des et très grandes), et nous la comparons avec les résultats donnés par CPLEX, un des meilleurs logiciels permettant de résoudre des problèmes d'optimisation mathématique, ainsi qu’avec une méthode de branch-and-cut. Il s'est avéré que notre méthode est prometteuse et peut donner de bons résultats, en particulier pour les instances de très grandes tailles.

Does prenatal diagnosis modify neonatal treatment and early outcome of children with esophageal atresia?

International audience

Desarrollo de arquitecturas para procesamiento de control de la mirada en sistemas de visión activa con resolución espacial variable

En esta tesis se aborda la implementación de un sistema completo de visión activa, en el que se capturan y generan imágenes de resolución espacial variable. Todo el sistema se integra en un sólo dispositivo del tipo AP SoC (All Programmable System on Chip), lo que nos permite llevar a cabo el codiseño hardware-software del mismo, implementando en la parte lógica los bloques de preprocesado intensivo, y en la parte software los algoritmos de procesado de control más complejo. El objetivo es que, trabajando con un campo visual del orden de Megapíxeles, se pueda procesar una tasa moderada de imágenes por segundo. Las imágenes multiresolución se generan a partir de sensores de resolución uniforme con una latencia nula, lo que permite tener preparada la imagen de resolución variable en el mismo instante en que se ha terminado de capturar la imagen original. Como innovación con respecto a las primeras contribuciones relacionadas con esta Tesis, se procesan imágenes con toda la información de color. Esto implica la necesidad de diseñar conversores entre espacios de color distintos, para adecuar la información al tipo de procesado que se va a realizar con ella. Estos bloques se integran sin alterar la latencia de entrega de los sucesivos fotogramas. El procesamiento de estas imágenes multirresolución genera un mapa de saliencia que permite mover la fóvea hacía la región considerada como más relevante en la escena. El contenido de la imagen se estructura en una jerarquía de niveles de abstracción. A diferencia de otras arquitecturas de este tipo, como son la pirámide regular y el polígono foveal, en las que se trabaja con imágenes de resolución uniforme en los distintos niveles de la jerarquía, la pirámide irregular foveal que se propone en esta tesis combina las ideas de trabajar con una imagen realmente multirresolución, que incluya el campo de visión completo que abarcan sensor y óptica, con el procesamiento jerárquico propio de las pirámides irregulares. Para ello en esta tesis se propone la implementación de un algoritmo de diezmado irregular que, tomando como base la imagen multirresolución, dará como resultado una estructura piramidal donde los distintos niveles no son imágenes sino grafos orientados a la resolución del problema de segmentación y estimación de saliencia. Todo el sistema se integra en torno a la arquitectura de bus AXI, que permite conectar entre si todos los cores desarrollados en la parte lógica, así como el acceso a la memoria compartida con los algoritmos implementados en la parte software. Esto es posible gracias a los bloques de acceso directo a memoria AXI-VDMA, en una propuesta de configuración que permite tanto la integración perfectamente coordinada de la transferencia de la imagen multirresolución generada a la zona de trabajo del algoritmo de segmentación como su recuperación para la posterior visualización del resultado del proceso, y todo ello con una tasa de trabajo que mejora los resultados de plataformas similares.

Holistic Design In High-Speed Optical Interconnects

Integrated circuit scaling has enabled a huge growth in processing capability, which necessitates a corresponding increase in inter-chip communication bandwidth. As bandwidth requirements for chip-to-chip interconnection scale, deficiencies of electrical channels become more apparent. Optical links present a viable alternative due to their low frequency-dependent loss and higher bandwidth density in the form of wavelength division multiplexing. As integrated photonics and bonding technologies are maturing, commercialization of hybrid-integrated optical links are becoming a reality. Increasing silicon integration leads to better performance in optical links but necessitates a corresponding co-design strategy in both electronics and photonics. In this light, holistic design of high-speed optical links with an in-depth understanding of photonics and state-of-the-art electronics brings their performance to unprecedented levels. This thesis presents developments in high-speed optical links by co-designing and co-integrating the primary elements of an optical link: receiver, transmitter, and clocking.

In the first part of this thesis a 3D-integrated CMOS/Silicon-photonic receiver will be presented. The electronic chip features a novel design that employs a low-bandwidth TIA front-end, double-sampling and equalization through dynamic offset modulation. Measured results show -14.9dBm of sensitivity and energy efficiency of 170fJ/b at 25Gb/s. The same receiver front-end is also used to implement source-synchronous 4-channel WDM-based parallel optical receiver. Quadrature ILO-based clocking is employed for synchronization and a novel frequency-tracking method that exploits the dynamics of IL in a quadrature ring oscillator to increase the effective locking range. An adaptive body-biasing circuit is designed to maintain the per-bit-energy consumption constant across wide data-rates. The prototype measurements indicate a record-low power consumption of 153fJ/b at 32Gb/s. The receiver sensitivity is measured to be -8.8dBm at 32Gb/s.

Next, on the optical transmitter side, three new techniques will be presented. First one is a differential ring modulator that breaks the optical bandwidth/quality factor trade-off known to limit the speed of high-Q ring modulators. This structure maintains a constant energy in the ring to avoid pattern-dependent power droop. As a first proof of concept, a prototype has been fabricated and measured up to 10Gb/s. The second technique is thermal stabilization of micro-ring resonator modulators through direct measurement of temperature using a monolithic PTAT temperature sensor. The measured temperature is used in a feedback loop to adjust the thermal tuner of the ring. A prototype is fabricated and a closed-loop feedback system is demonstrated to operate at 20Gb/s in the presence of temperature fluctuations. The third technique is a switched-capacitor based pre-emphasis technique designed to extend the inherently low bandwidth of carrier injection micro-ring modulators. A measured prototype of the optical transmitter achieves energy efficiency of 342fJ/bit at 10Gb/s and the wavelength stabilization circuit based on the monolithic PTAT sensor consumes 0.29mW.

Lastly, a first-order frequency synthesizer that is suitable for high-speed on-chip clock generation will be discussed. The proposed design features an architecture combining an LC quadrature VCO, two sample-and-holds, a PI, digital coarse-tuning, and rotational frequency detection for fine-tuning. In addition to an electrical reference clock, as an extra feature, the prototype chip is capable of receiving a low jitter optical reference clock generated by a high-repetition-rate mode-locked laser. The output clock at 8GHz has an integrated RMS jitter of 490fs, peak-to-peak periodic jitter of 2.06ps, and total RMS jitter of 680fs. The reference spurs are measured to be –64.3dB below the carrier frequency. At 8GHz the system consumes 2.49mW from a 1V supply.