Asymptotically Zero Energy Computing Using Split-Level Charge Recovery Logic

The dynamic power requirement of CMOS circuits is rapidly becoming a major concern in the design of personal information systems and large computers. In this work we present a number of new CMOS logic families, Charge Recovery Logic (CRL) as well as the much improved Split-Level Charge Recovery Logic (SCRL), within which the transfer of charge between the nodes occurs quasistatically. Operating quasistatically, these logic families have an energy dissipation that drops linearly with operating frequency, i.e., their power consumption drops quadratically with operating frequency as opposed to the linear drop of conventional CMOS. The circuit techniques in these new families rely on constructing an explicitly reversible pipelined logic gate, where the information necessary to recover the energy used to compute a value is provided by computing its logical inverse. Information necessary to uncompute the inverse is available from the subsequent inverse logic stage. We demonstrate the low energy operation of SCRL by presenting the results from the testing of the first fully quasistatic 8 x 8 multiplier chip (SCRL-1) employing SCRL circuit techniques.

Reconfigurable Architectures for General-Purpose Computing

General-purpose computing devices allow us to (1) customize computation after fabrication and (2) conserve area by reusing expensive active circuitry for different functions in time. We define RP-space, a restricted domain of the general-purpose architectural space focussed on reconfigurable computing architectures. Two dominant features differentiate reconfigurable from special-purpose architectures and account for most of the area overhead associated with RP devices: (1) instructions which tell the device how to behave, and (2) flexible interconnect which supports task dependent dataflow between operations. We can characterize RP-space by the allocation and structure of these resources and compare the efficiencies of architectural points across broad application characteristics. Conventional FPGAs fall at one extreme end of this space and their efficiency ranges over two orders of magnitude across the space of application characteristics. Understanding RP-space and its consequences allows us to pick the best architecture for a task and to search for more robust design points in the space. Our DPGA, a fine- grained computing device which adds small, on-chip instruction memories to FPGAs is one such design point. For typical logic applications and finite- state machines, a DPGA can implement tasks in one-third the area of a traditional FPGA. TSFPGA, a variant of the DPGA which focuses on heavily time-switched interconnect, achieves circuit densities close to the DPGA, while reducing typical physical mapping times from hours to seconds. Rigid, fabrication-time organization of instruction resources significantly narrows the range of efficiency for conventional architectures. To avoid this performance brittleness, we developed MATRIX, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs. Our focus MATRIX design point is based on an array of 8-bit ALU and register-file building blocks interconnected via a byte-wide network. With today's silicon, a single chip MATRIX array can deliver over 10 Gop/s (8-bit ops). On sample image processing tasks, we show that MATRIX yields 10-20x the computational density of conventional processors. Understanding the cost structure of RP-space helps us identify these intermediate architectural points and may provide useful insight more broadly in guiding our continual search for robust and efficient general-purpose computing structures.

ADAM: A Decentralized Parallel Computer Architecture Featuring Fast Thread and Data Migration and a Uniform Hardware Abstraction

The furious pace of Moore's Law is driving computer architecture into a realm where the the speed of light is the dominant factor in system latencies. The number of clock cycles to span a chip are increasing, while the number of bits that can be accessed within a clock cycle is decreasing. Hence, it is becoming more difficult to hide latency. One alternative solution is to reduce latency by migrating threads and data, but the overhead of existing implementations has previously made migration an unserviceable solution so far. I present an architecture, implementation, and mechanisms that reduces the overhead of migration to the point where migration is a viable supplement to other latency hiding mechanisms, such as multithreading. The architecture is abstract, and presents programmers with a simple, uniform fine-grained multithreaded parallel programming model with implicit memory management. In other words, the spatial nature and implementation details (such as the number of processors) of a parallel machine are entirely hidden from the programmer. Compiler writers are encouraged to devise programming languages for the machine that guide a programmer to express their ideas in terms of objects, since objects exhibit an inherent physical locality of data and code. The machine implementation can then leverage this locality to automatically distribute data and threads across the physical machine by using a set of high performance migration mechanisms. An implementation of this architecture could migrate a null thread in 66 cycles -- over a factor of 1000 improvement over previous work. Performance also scales well; the time required to move a typical thread is only 4 to 5 times that of a null thread. Data migration performance is similar, and scales linearly with data block size. Since the performance of the migration mechanism is on par with that of an L2 cache, the implementation simulated in my work has no data caches and relies instead on multithreading and the migration mechanism to hide and reduce access latencies.

Thermal control of electronics: Perspectives and prospects

One of the most prominent industrial applications of heat transfer science and engineering has been electronics thermal control. Driven by the relentless increase in spatial density of microelectronic devices, integrated circuit chip powers have risen by a factor of 100 over the past twenty years, with a somewhat smaller increase in heat flux. The traditional approaches using natural convection and forced-air cooling are becoming less viable as power levels increase. This paper provides a high-level overview of the thermal management problem from the perspective of a practitioner, as well as speculation on the prospects for electronics thermal engineering in years to come.

Memory Hierarchy Hardware-Software Co-design in Embedded Systems

The memory hierarchy is the main bottleneck in modern computer systems as the gap between the speed of the processor and the memory continues to grow larger. The situation in embedded systems is even worse. The memory hierarchy consumes a large amount of chip area and energy, which are precious resources in embedded systems. Moreover, embedded systems have multiple design objectives such as performance, energy consumption, and area, etc. Customizing the memory hierarchy for specific applications is a very important way to take full advantage of limited resources to maximize the performance. However, the traditional custom memory hierarchy design methodologies are phase-ordered. They separate the application optimization from the memory hierarchy architecture design, which tend to result in local-optimal solutions. In traditional Hardware-Software co-design methodologies, much of the work has focused on utilizing reconfigurable logic to partition the computation. However, utilizing reconfigurable logic to perform the memory hierarchy design is seldom addressed. In this paper, we propose a new framework for designing memory hierarchy for embedded systems. The framework will take advantage of the flexible reconfigurable logic to customize the memory hierarchy for specific applications. It combines the application optimization and memory hierarchy design together to obtain a global-optimal solution. Using the framework, we performed a case study to design a new software-controlled instruction memory that showed promising potential.

Review of bio-particle manipulation using dielectrophoresis

During the last decade, large and costly instruments are being replaced by system based on microfluidic devices. Microfluidic devices hold the promise of combining a small analytical laboratory onto a chip-sized substrate to identify, immobilize, separate, and purify cells, bio-molecules, toxins, and other chemical and biological materials. Compared to conventional instruments, microfluidic devices would perform these tasks faster with higher sensitivity and efficiency, and greater affordability. Dielectrophoresis is one of the enabling technologies for these devices. It exploits the differences in particle dielectric properties to allow manipulation and characterization of particles suspended in a fluidic medium. Particles can be trapped or moved between regions of high or low electric fields due to the polarization effects in non-uniform electric fields. By varying the applied electric field frequency, the magnitude and direction of the dielectrophoretic force on the particle can be controlled. Dielectrophoresis has been successfully demonstrated in the separation, transportation, trapping, and sorting of various biological particles.

Protein Microarray: "Theory" to "Real Practice"

Fueled by ever-growing genomic information and rapid developments of proteomics–the large scale analysis of proteins and mapping its functional role has become one of the most important disciplines for characterizing complex cell function. For building functional linkages between the biomolecules, and for providing insight into the mechanisms of biological processes, last decade witnessed the exploration of combinatorial and chip technology for the detection of bimolecules in a high throughput and spatially addressable fashion. Among the various techniques developed, the protein chip technology has been rapid. Recently we demonstrated a new platform called “Spacially addressable protein array” (SAPA) to profile the ligand receptor interactions. To optimize the platform, the present study investigated various parameters such as the surface chemistry and role of additives for achieving high density and high-throughput detection with minimal nonspecific protein adsorption. In summary the present poster will address some of the critical challenges in protein micro array technology and the process of fine tuning to achieve the optimum system for solving real biological problems.

Incidencia de los actores armados ilegales en la tributación minera de los municipios auríferos de Antioquia 2007 - I. 2012

Inmersos en un conflicto armado y guiados por un modelo político que busca aprovechar el boom minero en pro del desarrollo de Colombia, se han potencializado dinámicas ilegales donde los Actores Armados Ilegales (A.A.I), como ‘bandidos estacionarios’, se han ido adaptando a las nuevas dinámicas del mercado donde el lucro, la rentabilidad y la financiación son su objetivo central. En el departamento de Antioquia, esa situación data desde la formación de sus regiones, como son el caso del Bajo Cauca y Nordeste Antioqueño. Empero, lo novedoso en el conflicto armado, y que tiene relación directa con la minería aurífera es, la alta posibilidad que los A.A.I. estén viendo en esta actividad su principal fuente de financiación como consecuencia de dos hechos importantes: 1). El éxito que ha tenido la lucha contra el narcotráfico y por ende, contra los cultivos ilícitos. Y, 2) El elevado precio del oro en el mercado internacional puesto que, se estima que en los próximos años alcance entre $2.000 y $2.107 dólares la onza. En este orden de ideas, el lector encontrará como los actores armados ilegales actúan como bandidos estacionarios que ejerciendo la “minería criminal”, inciden en la política fiscal municipal a partir de la para-tributación o ‘impuesto de protección’, captación de regalías y el lavado de activos; donde el fin es financiar sus actividades criminales, afectando negativamente la política tributaria de los gobiernos municipales que se caracteriza por su baja capacidad de gestión.

Trans-Ancestral Studies Fine Map the SLE-Susceptibility Locus TNFSF4

We previously established an 80 kb haplotype upstream of TNFSF4 as a susceptibility locus in the autoimmune disease SLE. SLE-associated alleles at this locus are associated with inflammatory disorders, including atherosclerosis and ischaemic stroke. In Europeans, the TNFSF4 causal variants have remained elusive due to strong linkage disequilibrium exhibited by alleles spanning the region. Using a trans-ancestral approach to fine-map the locus, utilising 17,900 SLE and control subjects including Amerindian/Hispanics (1348 cases, 717 controls), African-Americans (AA) (1529, 2048) and better powered cohorts of Europeans and East Asians, we find strong association of risk alleles in all ethnicities; the AA association replicates in African-American Gullah (152,122). The best evidence of association comes from two adjacent markers: rs2205960-T (P = 1.71×10-34, OR = 1.43[1.26-1.60]) and rs1234317-T (P = 1.16×10-28, OR = 1.38[1.24-1.54]). Inference of fine-scale recombination rates for all populations tested finds the 80 kb risk and non-risk haplotypes in all except African-Americans. In this population the decay of recombination equates to an 11 kb risk haplotype, anchored in the 5′ region proximal to TNFSF4 and tagged by rs2205960-T after 1000 Genomes phase 1 (v3) imputation. Conditional regression analyses delineate the 5′ risk signal to rs2205960-T and the independent non-risk signal to rs1234314-C. Our case-only and SLE-control cohorts demonstrate robust association of rs2205960-T with autoantibody production. The rs2205960-T is predicted to form part of a decameric motif which binds NF-κBp65 with increased affinity compared to rs2205960-G. ChIP-seq data also indicate NF-κB interaction with the DNA sequence at this position in LCL cells. Our research suggests association of rs2205960-T with SLE across multiple groups and an independent non-risk signal at rs1234314-C. rs2205960-T is associated with autoantibody production and lymphopenia. Our data confirm a global signal at TNFSF4 and a role for the expressed product at multiple stages of lymphocyte dysregulation during SLE pathogenesis. We confirm the validity of trans-ancestral mapping in a complex trait. © 2013 Manku et al.

Autoreporte de la calidad de vida en niños y adolescentes colombianos: Estudio FUPRECOL

RESUMEN Introducción: El EQ-5D-Y proxy es un cuestionario genérico, de fácil comprensión y aplicación, que evalúa distintas dimensiones de la salud percibida. El objetivo del siguiente estudio fue describir por autoreporte la calidad de vida relacionada con la salud (CVRS) en una población escolar de Bogotá, Colombia, pertenecientes al estudio FUPRECOL. Métodos: Estudio descriptivo y transversal, realizado en 3.245 niños y 3.354 adolescentes, entre 9 y 17.9 años de edad, de 24 instituciones educativas oficiales de Bogotá, Colombia. Se aplicó de manera auto-administrada la versión validada al castellano por Olivares et al. (2009) del instrumento de CVRS infantil EQ-5D-Y proxy. Se analizaron los datos por medidas de tendencia central y se realizó una comparación de los observados en Colombia con estudios internacionales. Resultados: De la población evaluada, el 58,3% (n=3.848), fueron mujeres. En general, se observa puntuaciones elevadas en la CVRS en niños y adolescentes de ambos sexos. Al comparar por género, las dimensiones del EQ-5D-Y proxy “sentirse triste/preocupado o infeliz” y “tener dolor/malestar”, presentaron la mayor frecuencia de repuesta en el grupo de las mujeres. Al comparar los resultados de este estudio, por grupos de edad, con trabajos internacionales de niños y adolescentes, se observa que las puntuaciones del EQ-5D-Y proxy fueron superiores a los reportados en Suráfrica, Alemania e Italia. Conclusión: Se presentan valores de la CVRS según edad y sexo que podrán ser usados en la evaluación de la salud percibida en el ámbito escolar. Se hace necesario evaluar las propiedades psicométricas del EQ-5D-Y proxy en población Colombiana.

Una aproximación al financiamiento de un sistema de protección social en Colombia

El documento hace una revisión de las principales fuentes de protección social que hay en Colombia y las características de los sistemas de protección de otros países. Se encuentra que gran parte de lo que se conoce como gasto social se destina al tema pensional y que los resultados de los fondos de solidaridad son muy pequeños frente a la autoprotección de los hogares. Se propone tener en cuenta los esfuerzos individuales y privados que hay en Colombia al diseñar un sistema de protección social, pues de lo contrario se estarían desincentivando estos esfuerzos.

Representaciones sociales de la medicina complementaria y alternativa (MCA) para el cáncer en estudiantes universitarios de carreras de ciencias de la salud

Se realizó un estudio cualitativo exploratorio con estudiantes de carreras de Ciencias de la Salud con el objetivo de comprender las representaciones sociales que tienen acerca de la Medicina Complementaria y Alternativa (MCA) para el cáncer. Se desarrollaron grupos focales y la información obtenida fue analizada a través del Análisis Temático e interpretada con base en la Teoría de las Representaciones Sociales. Se encontraron diversas representaciones sociales asociadas con la definición, los objetivos, los tratamientos, la eficacia, las fuentes de información y el origen de la MCA. En conclusión se evidenció una alta tendencia a la aceptación y a la manifestación de una actitud positiva, aunque ambivalente frente a la MCA, además de un desconocimiento por la diferenciación conceptual entre este tipo de Medicina y la Medicina Popular. La cultura y las creencias sociales predominan en las representaciones sociales que tienen los estudiantes de la MCA para el cáncer, pese a su formación académica.

Programación del VIA 6522 : guía didáctica.

Se estudia el chip R-6522, definido como Versatile Interface Adapter (V.I.A.) y encargado de las tareas de entrada/salida en la microcomputadora R-6500. La guía se estructura en dos partes en las que se explica, de forma escalonada, el funcionamiento del V.I.A. En la primera parte se incluyen diez tareas y sus soluciones, en las que se analiza el funcionamiento de los elementos del V.I.A., los protocolos de diálogo y la generación y atención de interrupciones. En la segunda parte se incluyen los listados de programas complejos en los que intervienen la mayoría de los elementos del V.I.A. Se adjunta información sobre las instrucciones de la CPU 6502, los mapas de memoria, el software del AIM65/DRAC1, la programación de los registros del V.I.A. y los registros de control del V.I.A. 6522.

Noah's Ark adventure.

Pertenece a un amplio programa infantil de lectura que abarca distintos niveles de edad y, por tanto, de conocimientos. Se abordan las necesidades de lectura en los niños y la amplia variedad de habilidades que necesitan adquirir para su aprendizaje y, se destaca, también, la importancia de la narración en las historias y el orden recomendado para su lectura. La llave mágica de Biff y Chip les ayuda a trasladarse al Arca de Noé.

Mum to the rescue.

Pertenece a un amplio programa infantil de lectura que abarca distintos niveles de edad y, por tanto, de conocimientos. Se abordan las necesidades de lectura en los niños y la amplia variedad de habilidades que necesitan adquirir para su aprendizaje y, se destaca, también, la importancia de la narración en las historias y el orden recomendado para su lectura. Con la ayuda de su bote neumático la madre de Biff, Chip y Kipper rescata una barca antes de caer en una presa.