Low power optical phase conjugation in dyes embedded in polyvinyl alcohol films

Low power optical phase conjugation in polyvinyl alcohol films embedded with saturable dyes is reported. Phase conjugate reflectivity achieved is higher than that obtained in the case of similar gelatin films.

Modeling of ALFA Programs Using PVS Theorem Prover

In Safety critical software failure can have a high price. Such software should be free of errors before it is put into operation. Application of formal methods in the Software Development Life Cycle helps to ensure that the software for safety critical missions are ultra reliable. PVS theorem prover, a formal method tool, can be used for the formal verification of software in ADA Language for Flight Software Application (ALFA.). This paper describes the modeling of ALFA programs for PVS theorem prover. An ALFA2PVS translator is developed which automatically converts the software in ALFA to PVS specification. By this approach the software can be verified formally with respect to underflow/overflow errors and divide by zero conditions without the actual execution of the code.

A Generic Software Architecture for a Domain Specific Distributed Embedded System

In this paper, we have evolved a generic software architecture for a domain specific distributed embedded system. The system under consideration belongs to the Command, Control and Communication systems domain. The systems in such domain have very long operational lifetime. The quality attributes of these systems are equally important as the functional requirements. The main guiding principle followed in this paper for evolving the software architecture has been functional independence of the modules. The quality attributes considered most important for the system are maintainability and modifiability. Architectural styles best suited for the functionally independent modules are proposed with focus on these quality attributes. The software architecture for the system is envisioned as a collection of architecture styles of the functionally independent modules identified

Modeling of ALFA Programs Using PVS Theorem Prover

In Safety critical software failure can have a high price. Such software should be free of errors before it is put into operation. Application of formal methods in the Software Development Life Cycle helps to ensure that the software for safety critical missions are ultra reliable. PVS theorem prover, a formal method tool, can be used for the formal verification of software in ADA Language for Flight Software Application (ALFA.). This paper describes the modeling of ALFA programs for PVS theorem prover. An ALFA2PVS translator is developed which automatically converts the software in ALFA to PVS specification. By this approach the software can be verified formally with respect to underflow/overflow errors and divide by zero conditions without the actual execution of the code

A Compiler Integrated Assistance for Optimum Data Allocation in Banked Memory Embedded Processors

Bank switching in embedded processors having partitioned memory architecture results in code size as well as run time overhead. An algorithm and its application to assist the compiler in eliminating the redundant bank switching codes introduced and deciding the optimum data allocation to banked memory is presented in this work. A relation matrix formed for the memory bank state transition corresponding to each bank selection instruction is used for the detection of redundant codes. Data allocation to memory is done by considering all possible permutation of memory banks and combination of data. The compiler output corresponding to each data mapping scheme is subjected to a static machine code analysis which identifies the one with minimum number of bank switching codes. Even though the method is compiler independent, the algorithm utilizes certain architectural features of the target processor. A prototype based on PIC 16F87X microcontrollers is described. This method scales well into larger number of memory blocks and other architectures so that high performance compilers can integrate this technique for efficient code generation. The technique is illustrated with an example

Entwurf und Betrieb von Regelungs- und Monitoringsystemen für dezentrale Energiesysteme auf der Basis von verteilten Embedded Systems

Nach einem einleitenden ersten Kapitel wird im zweiten Kapitel der Stand der Technik für Regelungs- und Monitoringsysteme mit vernetzten Systemen dargestellt. Daraus wird die Motivation zur Entwicklung neuer, kostengünstiger Systeme abgeleitet. Im dritten Kapitel folgt eine Darstellung der verschiedenen Arten marktverfügbarer Embedded Systems und dafür geeigneter Betriebs­systeme. Anforderungen an verteilte Regelungssysteme, unterschiedliche Strukturen dieser Systeme und deren Vor- und Nachteile sind Gegenstand des vierten Kapitels. Anhand von Beispielen aus den Bereichen Erzeugungsmanagement für den Betrieb von KWK-Anlagen, Energieverbrauchsmonitoring und Smart-Metering wird der Einsatz von verteilten Regelungs- und Monitoringsystemen im fünften Kapitel dargestellt. Im folgenden sechsten Kapitel wird die Bedeutung normierter Kommunikation für den Einsatz in verteilten Systemen sowie dafür vorhandene Standards aus der elektrischen Energieversorgungstechnik und der Automatisierungstechnik behandelt. Der Stand der Internet-Technik für verteilte Systeme ist Gegenstand des siebten Kapitels. Dabei werden zunächst die verschiedenen drahtlosen und drahtgebundenen Kommunikationsmedien vorgestellt und ihre Eigenschaften und die Rand­bedingungen für ihren Einsatz erörtert. Ebenso werden technische Probleme beim Einsatz der Internet-Technik aufgezeigt und Lösungsmöglichkeiten für diese Probleme dargestellt. Es folgt eine Übersicht von Netzwerkdiensten, die für den Betrieb von verteilten Systemen notwendig sind. Außerdem werden Techniken zur Überwachung von verteilten Systemen behandelt. Kapitel acht zeigt Sicherheitsrisiken bei der Nutzung des Internets auf und bewertet verschiedene Techniken zur Absicherung des Netzwerkverkehrs. Kapitel neun stellt ein Internet-basiertes Client-Server-System zur Online-Visualisierung von Anlagendaten im Webbrowser mit Hilfe von Java-Applets und XML-RPC vor. Die Visualisierung von Anlagendaten auf Mobiltelefonen mit Hilfe des Wireless Application Protocol sowie die dafür notwendige Software und Infrastruktur ist Gegenstand des zehnten Kapitels. Im elften Kapitel wird eine neuartige Software für die Simulation von dezentralen Energiesystemen und deren Regelungs­systemen auf Basis von virtuellen Maschinen, virtuellen Netzwerken und einer thermischen Simulationsumgebung vorgestellt sowie deren Anwendung für die Reglerentwicklung erklärt. Verschiedene Techniken für die Installation von Betriebssystemen und Software für die Embedded Systems eines verteilten Systems werden im Kapitel zwölf untersucht. Im Kapitel 13 werden verschiedene Technologien zur Konfiguration und Parametrierung von Regelungssystemen in der industriellen Prozess- und Fertigungs­automatisierung hinsichtlich ihrer Eignung für dezentrale Energiesysteme analysiert. Anschließend wird eine Software zur Installation und Parametrierung von Monitoringsystemen sowie der dazugehörigen Infrastruktur vorgestellt. Kapitel 14 beschäftigt sich mit Anforderungen an die Hardware für verteilte Systeme und mit Maßnahmen zur Erhöhung der Betriebs- und der Datensicherheit. Im 15. Kapitel werden die in den bisherigen Kapiteln vorgestellten Techniken anhand eines großen verteilten Monitoringsystems und anhand eines Power Flow and Power Quality Management Systems auf Basis von verteilten Embedded Systems evaluiert. Kapitel 16 fasst die Ergebnisse der Arbeit zusammen und enthält einen Ausblick auf zukünftige Entwicklungen.

A Compilation Strategy for Numerical Programs Based on Partial Evaluation

This work demonstrates how partial evaluation can be put to practical use in the domain of high-performance numerical computation. I have developed a technique for performing partial evaluation by using placeholders to propagate intermediate results. For an important class of numerical programs, a compiler based on this technique improves performance by an order of magnitude over conventional compilation techniques. I show that by eliminating inherently sequential data-structure references, partial evaluation exposes the low-level parallelism inherent in a computation. I have implemented several parallel scheduling and analysis programs that study the tradeoffs involved in the design of an architecture that can effectively utilize this parallelism. I present these results using the 9- body gravitational attraction problem as an example.

Memory Hierarchy Hardware-Software Co-design in Embedded Systems

The memory hierarchy is the main bottleneck in modern computer systems as the gap between the speed of the processor and the memory continues to grow larger. The situation in embedded systems is even worse. The memory hierarchy consumes a large amount of chip area and energy, which are precious resources in embedded systems. Moreover, embedded systems have multiple design objectives such as performance, energy consumption, and area, etc. Customizing the memory hierarchy for specific applications is a very important way to take full advantage of limited resources to maximize the performance. However, the traditional custom memory hierarchy design methodologies are phase-ordered. They separate the application optimization from the memory hierarchy architecture design, which tend to result in local-optimal solutions. In traditional Hardware-Software co-design methodologies, much of the work has focused on utilizing reconfigurable logic to partition the computation. However, utilizing reconfigurable logic to perform the memory hierarchy design is seldom addressed. In this paper, we propose a new framework for designing memory hierarchy for embedded systems. The framework will take advantage of the flexible reconfigurable logic to customize the memory hierarchy for specific applications. It combines the application optimization and memory hierarchy design together to obtain a global-optimal solution. Using the framework, we performed a case study to design a new software-controlled instruction memory that showed promising potential.

On-the-Fly Maintenance of Series-Parallel Relationships in Fork-Join Multithreaded Programs

A key capability of data-race detectors is to determine whether one thread executes logically in parallel with another or whether the threads must operate in series. This paper provides two algorithms, one serial and one parallel, to maintain series-parallel (SP) relationships "on the fly" for fork-join multithreaded programs. The serial SP-order algorithm runs in O(1) amortized time per operation. In contrast, the previously best algorithm requires a time per operation that is proportional to Tarjan’s functional inverse of Ackermann’s function. SP-order employs an order-maintenance data structure that allows us to implement a more efficient "English-Hebrew" labeling scheme than was used in earlier race detectors, which immediately yields an improved determinacy-race detector. In particular, any fork-join program running in T₁ time on a single processor can be checked on the fly for determinacy races in O(T₁) time. Corresponding improved bounds can also be obtained for more sophisticated data-race detectors, for example, those that use locks. By combining SP-order with Feng and Leiserson’s serial SP-bags algorithm, we obtain a parallel SP-maintenance algorithm, called SP-hybrid. Suppose that a fork-join program has n threads, T₁ work, and a critical-path length of T[subscript ∞]. When executed on P processors, we prove that SP-hybrid runs in O((T₁/P + PT[subscript ∞]) lg n) expected time. To understand this bound, consider that the original program obtains linear speed-up over a 1-processor execution when P = O(T₁/T[subscript ∞]). In contrast, SP-hybrid obtains linear speed-up when P = O(√T₁/T[subscript ∞]), but the work is increased by a factor of O(lg n).

Implementation of training programs in self-regulated learning strategies in Moodle format : Results of a experience in higher education

Resumen tomado de la publicaci??n

The ISSA Pedagogical Standards: a tool to influence quality in early childhood programs

The ISSA Pedagogical Standards were first published in 2001 as a network-developed tool that defined quality in teaching practices and the classroom environment and captured the changes that had occurred in the region since 1994 when the Step by Step Program, an initiative to promote democratic principles in early childhood development and education, was launched. The Program was built on belief that each child has the right to receive maximum support for the development of his or her full potential, and this work should be done in partnership and close cooperation with families, communities and professionals

HLA-A Typing in formalin-fixed paraffin embedded tissue samples : towards potential retrospective analysis

El Antígeno Leucocitario Humano (HLA en inglés) ha sido descrito en muchos casos como factor de pronóstico para cáncer. La característica principal de los genes de HLA, localizados en el cromosoma 6 (6p21.3), son sus numerosos polimorfismos. Los análisis de secuencia de nucleótidos muestran que la variación está restringida predominantemente a los exones que codifican los dominios de unión a péptidos de la proteína. Por lo tanto, el polimorfismo del HLA define el repertorio de péptidos que se unen a los alotipos de HLA y este hecho define la habilidad de un individuo para responder a la exposición a muchos agentes infecciosos durante su vida. La tipificación de HLA se ha convertido en un análisis importante en clínica. Muestras de tejido embebidas en parafina y fijadas con formalina (FFPE en inglés) son recolectadas rutinariamente en oncología. Este procedimiento podría ser utilizado como una buena fuente de ADN, dado que en estudios en el pasado los ensayos de recolección de ADN no eran normalmente llevados a cabo de casi ningún tejido o muestra en procedimientos clínicos regulares. Teniendo en cuenta que el problema más importante con el ADN de muestras FFPE es la fragmentación, nosotros propusimos un nuevo método para la tipificación del alelo HLA-A desde muestras FFPE basado en las secuencias del exón 2, 3 y 4. Nosotros diseñamos un juego de 12 cebadores: cuatro para el exón 2 de HLA-A, tres para el exón 3 de HLA-A y cinco para el exón 4 de HLA-A, cada uno de acuerdo las secuencias flanqueantes de su respectivo exón y la variación en la secuencia entre diferentes alelos. 17 muestran FFPE colectadas en el Hospital Universitario de Karolinska en Estocolmo Suecia fueron sometidas a PCR y los productos fueron secuenciados. Finalmente todas las secuencias obtenidas fueron analizadas y comparadas con la base de datos del IMGT-HLA. Las muestras FFPE habían sido previamente tipificadas para HLA y los resultados fueron comparados con los de este método. De acuerdo con nuestros resultados, las muestras pudieron ser correctamente secuenciadas. Con este procedimiento, podemos concluir que nuestro estudio es el primer método de tipificación basado en secuencia que permite analizar muestras viejas de ADN de las cuales no se tiene otra fuente. Este estudio abre la posibilidad de desarrollar análisis para establecer nuevas relaciones entre HLA y diferentes enfermedades como el cáncer también.

Abstraction: From Transistors to Computers and from Bits to Programs

Takes the Tanenbaum (Structured Computer Organisation) approach to show how application of successive levels of abstraction allow us to understand how computers are made from transitors and how they are programmed.