A voltage-controlled ring oscillator using InP full enhancement-mode HEMT logic

A voltage-controlled ring oscillator (VCO) based on a full enhancement-mode InAIAs/InGaAs/InP high electron mobility transistor (HEMT) logic is proposed. An enhancement-mode HEMT (E-HEMT) is fabricated, whose threshold is demonstrated to be 10 mV. The model of the E-HEMT is established and used in the SPICE simulation of the VCO. The result proves that the full E-HEMT logic technology can be applied to the VCO. And compared with the HEMT DCFL technology, the complexity of our fabrication process is reduced and the reliability is improved.

A Novel 4T nMOS-Only SRAM Cell in 32nm Technology Node

This paper proposes a novel loadless 4T SRAM cell composed of nMOS transistors. The SRAM cell is based on 32nm silicon-on-insulator （SO1） technology node. It consists of two access transistors and two pull-down transistors. The pull-down transistors have larger channel length than the access transistors. Due to the significant short channel effect of small-size MOS transistors, the access transistors have much larger leakage current than the pull-down transistors,enabling the SRAM cell to maintain logic ＂1＂ while in standby. The storage node voltages of the cell are fed back to the back-gates of the access transistors,enabling the stable ＂read＂ operation of the cell. The use of back-gate feedback also helps to im- prove the static noise margin （SNM） of the cell. The proposed SRAM cell has smaller area than conventional bulk 6T SRAM cells and 4T SRAM cells. The speed and power dissipation of the SRAM cell are simulated and discussed. The SRAM cell can operate with a 0. 5V supply voltage.

A High Performance AlGaN/GaN HEMT with a New Method for T-Gate Layout Design

We propose and fabricate an A1GaN/GaN high electron mobility transistor （HEMT） on sapphire substrate using a new kind of electron beam （EB） lithography layout for the T-gate. Using this new layout,we can change the aspect ratio （ratio of top gate dimension to gate length） and modify the shape of the T-gate freely. Therefore, we obtain a 0.18μm gate-length AlGaN/GaN HEMT with a unity current gain cutoff frequency （f_T） of 65GHz. The aspect ratio of the T-gate is 10. These single finger devices also exhibit a peak extrinsic transconductance of 287mS/mm and a maximum drain current as high as 980mA/mm.

Wide-Band Polarization-Independent Semiconductor Optical Amplifier Gate with Tensile-Strained Quasi-Bulk InGaAs

A semiconductor optical amplifier gate based on tensile-strained quasi-bulk InGaAs is developed. At injection current of 80mA,a 3dB optical bandwidth of more than 85nm is achieved due to dominant band-filling effect.Moreover, the most important is that very low polarization dependence of gain (＜0. 7dB),fiber-to-fiber lossless operation current (70～90mA) and a high extinction ratio (＞50dB) are simultaneously obtained over this wide 3dB optical bandwidth (1520～1609nm) which nearly covers the spectral region of the whole C band (1525～1565nm)and the whole L band (1570～ 1610nm). The gating time is also improved by decreasing carrier lifetime. The wideband polarization-insensitive SOA-gate is promising for use in future dense wavelength division multiplexing (DWDM) communication systems.

Photonic AND Gate Based on Hybrid Integration of GaAs VCSEL and GaAs MISS

于2010-11-23批量导入

Dependence of ultra-thin gate oxide reliability on surface cleaning approach

In this paper, we investigate the effect of silicon surface cleaning prior to oxidation on the reliability of ultra-thin oxides. It is demonstrated that chemical preoxide grown in H2SO4/H2O2 (SPM) solution prior to oxidation provides better oxide integrity than both HF-based solution dipping and preoxide grown in RCA SC1 or SC2 solutions. It is also found that the oxides with SPM preoxide exhibit better hot-carrier immunity than the RCA cleaned oxides.

Observation of N-Shaped Negative Differential Resistance in GaAs-Based Modulation-Doped Field Effect Transistor with InAs Quantum Dots

N-shaped negative differential resistance (NDR) with a high peak-to-valley ratio (PVR) is observed in a GaAs-based modulation-doped field effect transistor (MODFET) with InAs quantum dots (QDs) in the barrier layer (QDFET) compared with a GaAs MODFET. The NDR is explained as the real-space transfer (RST) of high-mobility electrons in a channel into nearby barrier layers with low mobility, and the PVR is enhanced dramatically upon inserting the QD layer. It is also revealed that the QD layer traps holes and acts as a positively charged nano-floating gate after a brief optical illumination, while it acts as a negatively charged nano-floating gate and depletes the adjacent channel when charged by the electrons. The NDR suggests a promising application in memory or high-speed logic devices for the QDFET structure.

Origin of flat-band voltage sharp roll-off in metal gate/high-k/ultrathin- SiO2/Si p-channel metal-oxide-semiconductor stacks

The origin of the flat band voltage roll-off (V-FB roll-off) in metal gate/high-k/ultrathin-SiO2/Si metal-oxide-semiconductor stacks is analyzed and a model describing the role of the dipoles at the SiO2/Si interface on the V-FB sharp roll-off is proposed. The V-FB sharp roll-off appears when the thickness of the SiO2 interlayer diminishes to below the oxygen diffusion depth. The results derived using our model agree well with experimental data and provide insights to the mechanism of the V-FB sharp roll-off.

Fermi-Level Pinning at Metal/High-k Interface Influenced by Electron State Density of Metal Gate

The Fermi-level pinning (FLP) at the metal/high-k interface and its dependence on the electron state density of the metal gate are investigated. It is found that the FLP is largely determined by the distortion of the vacuum level of the metal which is quantitatively ruled by the electron state density of the metal. The physical origin of the vacuum level distortion of the metal is attributed to an image charge of the interface charge in the metal. Such results indicate that the effective work function of the metal/high-k stack is also governed by the electron state density of the metal.

In-plane stray field induced spin-filtering in a two-dimensional electron gas under the modulation of surface ferromagnetic dual-gate

Based upon a hybrid ferromagnet/semiconductor structure consisting of two-dimensional electron gas and a pair of surface ferromagnetic stripes on top, we have theoretically investigated the effect of in-plane stray field omitted frequently in previous studies on the spin-dependent ballistic transport properties in hybrid structure. It is demonstrated here that, in combination with an external-controllable electrostatic modulation, the concerned structure shows a similar function as a lateral spin-polarized resonant tunneling device, where the strong spin-filtering effect occurs and nearly single-mode polarization is anticipated for the proper modulation. More importantly, the spin polarity of transmission electron can be easily transferred from one extreme to the other by switching the magnetization of stripes, showing the promising application as an efficient spin aligner in the developing semiconductor spintronics.

Influence of gate dielectrics on charge transport in copper phthalocyanine thin-film transistors

Copper phthalocyanine organic thin-film transistors (OTFTs) were fabricated with top-gate geometry and the effects of different gate dielectrics on the transport proper-ties in OTFTs were studied. The mobility was found to be gate voltage dependent and the results showed that besides the charge density in the accumulation layer, the energetic disorder induced by gate dielectrics played an important role in determining the field-effect mobility in OTFTs.

Effect of the work function of gate electrode on hysteresis characteristics of organic thin-film transistors with Ta2O5/polymer as gate insulator

Organic thin-film transistors (OTFTs) using high dielectric constant material tantalum pentoxide (Ta2O5) and benzocyclobutenone (BCBO) derivatives as double-layer insulator were fabricated. Three metals with different work function, including Al (4.3 eV), Cr (4.5 eV) and Au (5.1 eV), were employed as gate electrodes to study the correlation between work function of gate metals and hysteresis characteristics of OTFTs. The devices with low work function metal Al or Cr as gate electrode exhibited high hysteresis (about 2.5 V threshold voltage shift). However, low hysteresis (about 0.7 V threshold voltage shift) OTFTs were attained based on high work function metal Au as gate electrode.