An analog implementation of radial basis neural networks (RBNN) using BiCMOS technology

This paper describes a analog implementation of radial basis neural networks (RBNN) in BiCMOS technology. The RBNN uses a gaussian function obtained through the characteristic of the bipolar differential pair. The gaussian parameters (gain, center and width) is changed with programmable current source. Results obtained with PSPICE software is showed.

Evolvable hardware applied to voice recognition

This paper presents some results of the application on Evolvable Hardware (EHW) in the area of voice recognition. Evolvable Hardware is able to change inner connections, using genetic learning techniques, adapting its own functionality to external condition changing. This technique became feasible by the improvement of the Programmable Logic Devices. Nowadays, it is possible to have, in a single device, the ability to change, on-line and in real-time, part of its own circuit. This work proposes a reconfigurable architecture of a system that is able to receive voice commands to execute special tasks as, to help handicapped persons in their daily home routines. The idea is to collect several voice samples, process them through algorithms based on Mel - Ceptrais theory to obtain their numerical coefficients for each sample, which, compose the universe of search used by genetic algorithm. The voice patterns considered, are limited to seven sustained Portuguese vowel phonemes (a, eh, e, i, oh, o, u).

A Gm-C bump equalizer for low-voltage low-power applications

A low-voltage low-power 2nd-order CMOS pseudo-differential bump-equalizer is presented. Its topology comprises a bandpass section with adjustable center frequency and quality factor, together with a programmable current amplifier. The basic building blocks are triode-operating transconductors, tunable by means of either a DC voltage or a digitally controlled current divider. The bump-equalizer as part of a battery-operated hearing aid device is designed for a 1.4V-supply and a 0.35μm CMOS fabrication process. The circuit performance is supported by a set of simulation results, which indicates a center frequency from 600Hz to 2.4kHz, 1≤Q≤5, and an adjustable gain within ±6dB at center frequency. The filter dynamic range lies around 40dB. Quiescent consumption is kept below 12μW for any configuration of the filter.

Common architecture for discrete wavelet transform analysis and synthesis with sequential and constant processing elements

This paper adresses the problem on processing biological data such as cardiac beats, audio and ultrasonic range, calculating wavelet coefficients in real time, with processor clock running at frequency of present ASIC's and FPGA. The Paralell Filter Architecture for DWT has been improved, calculating wavelet coefficients in real time with hardware reduced to 60%. The new architecture, which also processes IDWT, is implemented with the Radix-2 or the Booth-Wallace Constant multipliers. Including series memory register banks, one integrated circuit Signal Analyzer, ultrasonic range, is presented.

A petri net based timing model for hardware/software co-design of digital systems

We have recently proposed an extension to Petri nets in order to be able to directly deal with all aspects of embedded digital systems. This extension is meant to be used as an internal model of our co-design environment. After analyzing relevant related work, and presenting a short introduction to our extension as a background material, we describe the details of the timing model we use in our approach, which is mainly based in Merlin's time model. We conclude the paper by discussing an example of its usage. © 2004 IEEE.

An AC voltage regulator with high-power-factor, and control using a FPGA device

This paper presents the analysis, design, simulation, and experimental results for a high frequency high Power-Factor (PF) AC (Alternate Current) voltage regulator, using a Sepic converter as power stage. The control technique employed to impose a sinusoidal input current waveform, with low Total Harmonic Distortion (THD), is the sinusoidal variable hysteresis control. The control technique was implemented in a FPGA (Field Programmable Gate Array) device, using a Hardware Description Language (VHDL). Through the use of the proposed control technique, the AC voltage regulator performs active power-factor correction, and low THD in the input current, for linear and non-linear loads, satisfying the requirements of the EEC61000-3-2 standards. Experimental results from an example prototype, designed for 300W of nominal output power, 50kHz (switching frequency), and 127Vrms of nominal input and output voltages, are presented in order to validate the proposed AC regulator. © 2005 IEEE.

Open and standardized tools for smart transducer networking

IEEE 1451 Standard is intended to address the smart transducer interfacing problematic in network environments. Usually, proprietary hardware and software is a very efficient solution to in planent the IEEE 1451 normative, although can be expensive and inflexible. In contrast, the use of open and standardized tools for implementing the IEEE 1451 normative is proposed in this paper. Tools such as Java and Phyton programming languages, Linux, programmable logic technology, Personal Computer resources and Ethernet architecture were integrated in order to constructa network node based on the IEEE 1451 standards. The node can be applied in systems based on the client-server communication model The evaluation of the employed tools and expermental results are presented. © 2005 IEEE.

Conception of wheeled mobile robots with reconfigurable control using integrate prototyping

With the fast innovation of the hardware and software technologies using rapid prototyping devices, with application in the robotics and automation, more and more it becomes necessary the development of applications based on methodologies that facilitate future modifications, updates and enhancements in the original projected system. This paper presents a conception of mobile robots using rapid prototyping, distributing the several control actions in growing levels of complexity and using resources of reconfigurable computing proposal oriented to embed systems implementation. Software and the hardware are structuralized in independents blocks, with connection through common bus. The study and applications of new structures control that permits good performance in relation to the parameter variations. This kind of controller can be tested on different platform representing the wheeled mobile robots using reprogrammable logic components (FPGA). © 2006 IEEE.

Proposal of architecture for launcher systems of unguided sounding rockets

This work presents a proposal of systemic architecture, to make automatic actions in the positioning of launch rail of unguided sounding rockets, which are based on a supervision system, a programmable logical controller, a sensory and actuators, available in Brazilian national market. Copyright © 2006 Society of Automotive Engineers, Inc.

Discrete wavelet transform signal analyzer

This paper addresses the problem of processing biological data, such as cardiac beats in the audio and ultrasonic range, and on calculating wavelet coefficients in real time, with the processor clock running at a frequency of present application-specified integrated circuits and field programmable gate array. The parallel filter architecture for discrete wavelet transform (DWT) has been improved, calculating the wavelet coefficients in real time with hardware reduced up to 60%. The new architecture, which also processes inverse DWT, is implemented with the Radix-2 or the Booth-Wallace constant multipliers. One integrated circuit signal analyzer in the ultrasonic range, including series memory register banks, is presented. © 2007 IEEE.

An efficient methodological approach in the didatic of automation applied to integrated manufacturing

This work presents challenges and solutions for the teaching and learning of automation applied to integrated manufacturing by means of a methodological approach based on techniques, tools and industrial equipment directly applicable in the industry. The approach was implemented in a control and automation engineering course divided into expositive and laboratory classes. Since the success of the approach is mainly from the practical activities, the article focus more on activities developed in laboratory than theorical classes. Copyright © 2007 IFAC.

Using GPUs for beamforming acceleration on SAFT imaging

SAFT techniques are based on the sequential activation, in emission and reception, of the array elements and the post-processing of all the received signals to compose the image. Thus, the image generation can be divided into two stages: (1) the excitation and acquisition stage, where the signals received by each element or group of elements are stored; and (2) the beamforming stage, where the signals are combined together to obtain the image pixels. The use of Graphics Processing Units (GPUs), which are programmable devices with a high level of parallelism, can accelerate the computations of the beamforming process, that usually includes different functions such as dynamic focusing, band-pass filtering, spatial filtering or envelope detection. This work shows that using GPU technology can accelerate, in more than one order of magnitude with respect to CPU implementations, the beamforming and post-processing algorithms in SAFT imaging. ©2009 IEEE.

Virtual instrumentation: A practical approach to control and supervision process

This work describes a control and supervision application takes into account the virtual instrumentation advantages to control and supervision industrial manufacturing stations belonging to the modular production system MPS® by Festo. These stations integrate sensors, actuators, conveyor belt and other industrial elements. The focus in this approach was to replace the use of programmable logic controllers by a computer equipped with a software application based on Labview and, together, performs the functions of traditional instruments and PLCs. The manufacturing stations had their processes modeled and simulated in Petri nets. After the models were implemented in Labview environment. Tests and previous similar works in MPS® installed in Automation Laboratory, at UNESP Sorocaba campus, showed the materials and methods used in this work allow the successful use of virtual instrumentation. The results indicate the technology as an advantageous approach for the automation of industrial processes, with gains in flexibility and reduction in project cost. © 2011 IEEE.

HW/SW for an intelligent transducer network based on IEEE 1451 standard

This work describes a hardware/software co-design system development, named IEEE 1451 platform, to be used in process automation. This platform intends to make easier the implementation of IEEE standards 1451.0, 1451.1, 1451.2 and 1451.5. The hardware was built using NIOS II processor resources on Alteras Cyclone II FPGA. The software was done using Java technology and C/C++ for the processors programming. This HW/SW system implements the IEEE 1451 based on a control module and supervisory software for industrial automation. © 2011 Elsevier B.V.

Vitrification of immature feline oocytes with a commercial kit for bovine embryo vitrification

The aim of this study was to evaluate the suitability of a commercial kit for bovine embryo vitrification for cryopreserving cat oocytes and to evaluate comparatively the effects of its use with slow freezing procedure on cryotolerance in terms of morphology and oocyte resumption of meiosis. Germinal vesicle stage oocytes isolated from cat ovaries were either vitrified (n=72) using a vitrification kit for bovine embryo or slow frozen (n=69) by exposing oocyte to ethylene glycol solution before being transferred to a programmable embryo freezer. After thawing and warming, oocytes were cultured for 48h and then were examined for meiosis resumption using bisbenzimide fluorescent staining (Hoechst 33342). Fresh immature oocytes (n=92) were used as the control group. The proportion of oocytes recovered in a morphologically normal state after thawing/warming was significantly higher in frozen oocytes (94.5%) than in the vitrified ones (75%, p<0.01). Morphological integrity after culture was similar in vitrified (73.6%) and slow frozen oocytes (76.8%); however, only 37.5% of the morphologically normal oocytes resumed meiosis after vitrification compared to 60.9% of those submitted to slow freezing procedure (p<0.01). Fresh oocytes showed higher morphological integrity (91.3%) and meiosis resumption rates (82.6%, p<0.002) than cryopreserved oocytes, irrespective of the procedure used. These results suggest that immature cat oocytes vitrified with a kit for bovine embryos retain their capacity to resume meiosis after warming and culture, albeit at lower rates than slow frozen oocytes. Vitrification and slow freezing methods show similar proportions of oocytes with normal morphology after culture, which demonstrate that thawed and warmed oocytes that resist to cryodamage have the same chances to maintain their integrity after 48h of culture. © 2012 Blackwell Verlag GmbH.