A production-compatible microelectronic test pattern for evaluating photomask misalignment /

Includes bibliographical references.

A heuristic algorithm to generate test program sequences for moving probe electronic test equipment

The electronics industry, is experiencing two trends one of which is the drive towards miniaturization of electronic products. The in-circuit testing predominantly used for continuity testing of printed circuit boards (PCB) can no longer meet the demands of smaller size circuits. This has lead to the development of moving probe testing equipment. Moving Probe Test opens up the opportunity to test PCBs where the test points are on a small pitch (distance between points). However, since the test uses probes that move sequentially to perform the test, the total test time is much greater than traditional in-circuit test. While significant effort has concentrated on the equipment design and development, little work has examined algorithms for efficient test sequencing. The test sequence has the greatest impact on total test time, which will determine the production cycle time of the product. Minimizing total test time is a NP-hard problem similar to the traveling salesman problem, except with two traveling salesmen that must coordinate their movements. The main goal of this thesis was to develop a heuristic algorithm to minimize the Flying Probe test time and evaluate the algorithm against a "Nearest Neighbor" algorithm. The algorithm was implemented with Visual Basic and MS Access database. The algorithm was evaluated with actual PCB test data taken from Industry. A statistical analysis with 95% C.C. was performed to test the hypothesis that the proposed algorithm finds a sequence which has a total test time less than the total test time found by the "Nearest Neighbor" approach. Findings demonstrated that the proposed heuristic algorithm reduces the total test time of the test and, therefore, production cycle time can be reduced through proper sequencing.

Testing of Interposer-Based 2.5D Integrated Circuits

The unprecedented and relentless growth in the electronics industry is feeding the demand for integrated circuits (ICs) with increasing functionality and performance at minimum cost and power consumption. As predicted by Moore's law, ICs are being aggressively scaled to meet this demand. While the continuous scaling of process technology is reducing gate delays, the performance of ICs is being increasingly dominated by interconnect delays. In an effort to improve submicrometer interconnect performance, to increase packing density, and to reduce chip area and power consumption, the semiconductor industry is focusing on three-dimensional (3D) integration. However, volume production and commercial exploitation of 3D integration are not feasible yet due to significant technical hurdles.

At the present time, interposer-based 2.5D integration is emerging as a precursor to stacked 3D integration. All the dies and the interposer in a 2.5D IC must be adequately tested for product qualification. However, since the structure of 2.5D ICs is different from the traditional 2D ICs, new challenges have emerged: (1) pre-bond interposer testing, (2) lack of test access, (3) limited ability for at-speed testing, (4) high density I/O ports and interconnects, (5) reduced number of test pins, and (6) high power consumption. This research targets the above challenges and effective solutions have been developed to test both dies and the interposer.

The dissertation first introduces the basic concepts of 3D ICs and 2.5D ICs. Prior work on testing of 2.5D ICs is studied. An efficient method is presented to locate defects in a passive interposer before stacking. The proposed test architecture uses e-fuses that can be programmed to connect or disconnect functional paths inside the interposer. The concept of a die footprint is utilized for interconnect testing, and the overall assembly and test flow is described. Moreover, the concept of weighted critical area is defined and utilized to reduce test time. In order to fully determine the location of each e-fuse and the order of functional interconnects in a test path, we also present a test-path design algorithm. The proposed algorithm can generate all test paths for interconnect testing.

In order to test for opens, shorts, and interconnect delay defects in the interposer, a test architecture is proposed that is fully compatible with the IEEE 1149.1 standard and relies on an enhancement of the standard test access port (TAP) controller. To reduce test cost, a test-path design and scheduling technique is also presented that minimizes a composite cost function based on test time and the design-for-test (DfT) overhead in terms of additional through silicon vias (TSVs) and micro-bumps needed for test access. The locations of the dies on the interposer are taken into consideration in order to determine the order of dies in a test path.

To address the scenario of high density of I/O ports and interconnects, an efficient built-in self-test (BIST) technique is presented that targets the dies and the interposer interconnects. The proposed BIST architecture can be enabled by the standard TAP controller in the IEEE 1149.1 standard. The area overhead introduced by this BIST architecture is negligible; it includes two simple BIST controllers, a linear-feedback-shift-register (LFSR), a multiple-input-signature-register (MISR), and some extensions to the boundary-scan cells in the dies on the interposer. With these extensions, all boundary-scan cells can be used for self-configuration and self-diagnosis during interconnect testing. To reduce the overall test cost, a test scheduling and optimization technique under power constraints is described.

In order to accomplish testing with a small number test pins, the dissertation presents two efficient ExTest scheduling strategies that implements interconnect testing between tiles inside an system on chip (SoC) die on the interposer while satisfying the practical constraint that the number of required test pins cannot exceed the number of available pins at the chip level. The tiles in the SoC are divided into groups based on the manner in which they are interconnected. In order to minimize the test time, two optimization solutions are introduced. The first solution minimizes the number of input test pins, and the second solution minimizes the number output test pins. In addition, two subgroup configuration methods are further proposed to generate subgroups inside each test group.

Finally, the dissertation presents a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs. An SoC die in the 2.5D IC is typically composed of several blocks and two neighboring blocks that share the same power rails should not be toggled at the same time during shift. Therefore, the proposed programmable method does not assign the same stagger value to neighboring blocks. The positions of all blocks are first analyzed and the shared boundary length between blocks is then calculated. Based on the position relationships between the blocks, a mathematical model is presented to derive optimal result for small-to-medium sized problems. For larger designs, a heuristic algorithm is proposed and evaluated.

In summary, the dissertation targets important design and optimization problems related to testing of interposer-based 2.5D ICs. The proposed research has led to theoretical insights, experiment results, and a set of test and design-for-test methods to make testing effective and feasible from a cost perspective.

Modélisation des machines par circuits couplés pour l’observation des courants de barres au rotor

Ce travail présente une modélisation rapide d’ordre élévé capable de modéliser une configuration rotorique en cage complète ou en grille, de reproduire les courants de barre et tenir compte des harmoniques d’espace. Le modèle utilise une approche combinée d’éléments finis avec les circuits-couplés. En effet, le calcul des inductances est réalisé avec les éléments finis, ce qui confère une précision avancée au modèle. Cette méthode offre un gain important en temps de calcul sur les éléments finis pour des simulations transitoires. Deux outils de simulation sont développés, un dans le domaine du temps pour des résolutions dynamiques et un autre dans le domaine des phaseurs dont une application sur des tests de réponse en fréquence à l’arrêt (SSFR) est également présentée. La méthode de construction du modèle est décrite en détail de même que la procédure de modélisation de la cage du rotor. Le modèle est validé par l’étude de machines synchrones: une machine de laboratoire de 5.4 KVA et un grand alternateur de 109 MVA dont les mesures expérimentales sont comparées aux résultats de simulation du modèle pour des essais tels que des tests à vide, des courts-circuits triphasés, biphasés et un test en charge.

Security through Obscurity: Layout Obfuscation of Digital Integrated Circuits using Don't Care Conditions

Contemporary integrated circuits are designed and manufactured in a globalized environment leading to concerns of piracy, overproduction and counterfeiting. One class of techniques to combat these threats is circuit obfuscation which seeks to modify the gate-level (or structural) description of a circuit without affecting its functionality in order to increase the complexity and cost of reverse engineering. Most of the existing circuit obfuscation methods are based on the insertion of additional logic (called “key gates”) or camouflaging existing gates in order to make it difficult for a malicious user to get the complete layout information without extensive computations to determine key-gate values. However, when the netlist or the circuit layout, although camouflaged, is available to the attacker, he/she can use advanced logic analysis and circuit simulation tools and Boolean SAT solvers to reveal the unknown gate-level information without exhaustively trying all the input vectors, thus bringing down the complexity of reverse engineering. To counter this problem, some ‘provably secure’ logic encryption algorithms that emphasize methodical selection of camouflaged gates have been proposed previously in literature [1,2,3]. The contribution of this paper is the creation and simulation of a new layout obfuscation method that uses don't care conditions. We also present proof-of-concept of a new functional or logic obfuscation technique that not only conceals, but modifies the circuit functionality in addition to the gate-level description, and can be implemented automatically during the design process. Our layout obfuscation technique utilizes don’t care conditions (namely, Observability and Satisfiability Don’t Cares) inherent in the circuit to camouflage selected gates and modify sub-circuit functionality while meeting the overall circuit specification. Here, camouflaging or obfuscating a gate means replacing the candidate gate by a 4X1 Multiplexer which can be configured to perform all possible 2-input/ 1-output functions as proposed by Bao et al. [4]. It is important to emphasize that our approach not only obfuscates but alters sub-circuit level functionality in an attempt to make IP piracy difficult. The choice of gates to obfuscate determines the effort required to reverse engineer or brute force the design. As such, we propose a method of camouflaged gate selection based on the intersection of output logic cones. By choosing these candidate gates methodically, the complexity of reverse engineering can be made exponential, thus making it computationally very expensive to determine the true circuit functionality. We propose several heuristic algorithms to maximize the RE complexity based on don’t care based obfuscation and methodical gate selection. Thus, the goal of protecting the design IP from malicious end-users is achieved. It also makes it significantly harder for rogue elements in the supply chain to use, copy or replicate the same design with a different logic. We analyze the reverse engineering complexity by applying our obfuscation algorithm on ISCAS-85 benchmarks. Our experimental results indicate that significant reverse engineering complexity can be achieved at minimal design overhead (average area overhead for the proposed layout obfuscation methods is 5.51% and average delay overhead is about 7.732%). We discuss the strengths and limitations of our approach and suggest directions that may lead to improved logic encryption algorithms in the future. References: [1] R. Chakraborty and S. Bhunia, “HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 10, pp. 1493–1502, 2009. [2] J. A. Roy, F. Koushanfar, and I. L. Markov, “EPIC: Ending Piracy of Integrated Circuits,” in 2008 Design, Automation and Test in Europe, 2008, pp. 1069–1074. [3] J. Rajendran, M. Sam, O. Sinanoglu, and R. Karri, “Security Analysis of Integrated Circuit Camouflaging,” ACM Conference on Computer Communications and Security, 2013. [4] Bao Liu, Wang, B., "Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks,"Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 , vol., no., pp.1,6, 24-28 March 2014.

Optimisation of digitally coded test vectors for mixed-signal components

International audience

Adapting The Sniffin' Sticks Olfactory Test To Diagnose Parkinson's Disease In Estonia.

The aim of the study was to develop a culturally adapted translation of the 12-item smell identification test from Sniffin' Sticks (SS-12) for the Estonian population in order to help diagnose Parkinson's disease (PD). A standard translation of the SS-12 was created and 150 healthy Estonians were questioned about the smells used as response options in the test. Unfamiliar smells were replaced by culturally familiar options. The adapted SS-12 was applied to 70 controls in all age groups, and thereafter to 50 PD patients and 50 age- and sex-matched controls. 14 response options from 48 used in the SS-12 were replaced with familiar smells in an adapted version, in which the mean rate of correct response was 87% (range 73-99) compared to 83% with the literal translation (range 50-98). In PD patients, the average adapted SS-12 score (5.4/12) was significantly lower than in controls (average score 8.9/12), p < 0.0001. A multiple linear regression using the score in the SS-12 as the outcome measure showed that diagnosis and age independently influenced the result of the SS-12. A logistic regression using the SS-12 and age as covariates showed that the SS-12 (but not age) correctly classified 79.0% of subjects into the PD and control category, using a cut-off of <7 gave a sensitivity of 76% and specificity of 86% for the diagnosis of PD. The developed SS-12 cultural adaption is appropriate for testing olfaction in Estonia for the purpose of PD diagnosis.

Effect Of Exercise Test On Pulmonary Function Of Obese Adolescents.

to investigate the pulmonary response to exercise of non-morbidly obese adolescents, considering the gender. a prospective cross-sectional study was conducted with 92 adolescents (47 obese and 45 eutrophic), divided in four groups according to obesity and gender. Anthropometric parameters, pulmonary function (spirometry and oxygen saturation [SatO2]), heart rate (HR), blood pressure (BP), respiratory rate (RR), and respiratory muscle strength were measured. Pulmonary function parameters were measured before, during, and after the exercise test. BP and HR were higher in obese individuals during the exercise test (p = 0.0001). SatO2 values decreased during exercise in obese adolescents (p = 0.0001). Obese males had higher levels of maximum inspiratory and expiratory pressures (p = 0.0002) when compared to obese and eutrophic females. Obese males showed lower values of maximum voluntary ventilation, forced vital capacity, and forced expiratory volume in the first second when compared to eutrophic males, before and after exercise (p = 0.0005). Obese females had greater inspiratory capacity compared to eutrophic females (p = 0.0001). Expiratory reserve volume was lower in obese subjects when compared to controls (p ≤ 0,05). obese adolescents presented changes in pulmonary function at rest and these changes remained present during exercise. The spirometric and cardiorespiratory values were different in the four study groups. The present data demonstrated that, in spite of differences in lung growth, the model of fat distribution alters pulmonary function differently in obese female and male adolescents.

Impact Of Pregabalin Treatment On Synaptic Plasticity And Glial Reactivity During The Course Of Experimental Autoimmune Encephalomyelitis.

Multiple sclerosis (MS) is an autoimmune and neurodegenerative disease that affects young adults. It is characterized by generating a chronic demyelinating autoimmune inflammation in the central nervous system. An experimental model for studying MS is the experimental autoimmune encephalomyelitis (EAE), induced by immunization with antigenic proteins from myelin. The present study investigated the evolution of EAE in pregabalin treated animals up to the remission phase. The results demonstrated a delay in the onset of the disease with statistical differences at the 10th and the 16th day after immunization. Additionally, the walking track test (CatWalk) was used to evaluate different parameters related to motor function. Although no difference between groups was obtained for the foot print pressure, the regularity index was improved post treatment, indicating a better motor coordination. The immunohistochemical analysis of putative synapse preservation and glial reactivity revealed that pregabalin treatment improved the overall morphology of the spinal cord. A preservation of circuits was depicted and the glial reaction was downregulated during the course of the disease. qRT-PCR data did not show immunomodulatory effects of pregabalin, indicating that the positive effects were restricted to the CNS environment. Overall, the present data indicate that pregabalin is efficient for reducing the seriousness of EAE, delaying its course as well as reducing synaptic loss and astroglial reaction.

The Lea Grating Test In Assessing Detection Grating Acuity In Normal Infants Less Than 4 Months Of Age.

To assess binocular detection grating acuity using the LEA GRATINGS test to establish age-related norms in healthy infants during their first 3 months of life. In this prospective, longitudinal study of healthy infants with clear red reflex at birth, responses to gratings were measured at 1, 2, and 3 months of age using LEA gratings at a distance of 28 cm. The results were recorded as detection grating acuity values, which were arranged in frequency tables and converted to a one-octave scale for statistical analysis. For the repeated measurements, analysis of variance (ANOVA) was used to compare the detection grating acuity results between ages. A total of 133 infants were included. The binocular responses to gratings showed development toward higher mean values and spatial frequencies, ranging from 0.55 ± 0.70 cycles per degree (cpd), or 1.74 ± 0.21 logMAR, in month 1 to 3.11 ± 0.54 cpd, or 0.98 ± 0.16 logMAR, in month 3. Repeated ANOVA indicated differences among grating acuity values in the three age groups. The LEA GRATINGS test allowed assessment of detection grating acuity and its development in a cohort of healthy infants during their first 3 months of life.

The Geometric Curvature Of The Spine Of Runners During Maximal Incremental Effort Test.

This study sought to analyse the behaviour of the average spinal posture using a novel investigative procedure in a maximal incremental effort test performed on a treadmill. Spine motion was collected via stereo-photogrammetric analysis in thirteen amateur athletes. At each time percentage of the gait cycle, the reconstructed spine points were projected onto the sagittal and frontal planes of the trunk. On each plane, a polynomial was fitted to the data, and the two-dimensional geometric curvature along the longitudinal axis of the trunk was calculated to quantify the geometric shape of the spine. The average posture presented at the gait cycle defined the spine Neutral Curve. This method enabled the lateral deviations, lordosis, and kyphosis of the spine to be quantified noninvasively and in detail. The similarity between each two volunteers was a maximum of 19% on the sagittal plane and 13% on the frontal (p<0.01). The data collected in this study can be considered preliminary evidence that there are subject-specific characteristics in spinal curvatures during running. Changes induced by increases in speed were not sufficient for the Neutral Curve to lose its individual characteristics, instead behaving like a postural signature. The data showed the descriptive capability of a new method to analyse spinal postures during locomotion; however, additional studies, and with larger sample sizes, are necessary for extracting more general information from this novel methodology.

Twin-twin Transfusion Syndrome: Neurodevelopmental Screening Test.

Objective To assess the neurodevelopmental functions (cognition, language and motor function) of survivors of twin-twin transfusion syndrome (TTTS). Method Observational cross-sectional study of a total of 67 monochorionic diamniotic twins who underwent fetoscopic laser coagulation (FLC) for treatment of TTTS. The study was conducted at the Center for Investigation in Pediatrics (CIPED), Universidade Estadual de Campinas. Ages ranged from one month and four days to two years four months. Bayley Scales of Infant and Toddler Development Screening Test-III, were used for evaluation. Results Most children reached the competent category and were classified as having appropriate performance. The preterm children scored worse than term infants for gross motor subtest (p = 0.036). Conclusion The majority of children reached the expected development according to their age. Despite the good neurodevelopment, children classified at risk should be monitored for development throughout childhood.

Evaluation of the cytotoxic and genotoxic potential of water from the River Paraíba do Sul, in Brazil, with the Allium cepa L. test

This work investigated the cytotoxic and genotoxic potential of water from the River Paraíba do Sul (Brazil) using Allium cepa roots. An anatomo-morphological parameter (root length), mitotic indices, and frequency of micronuclei were analysed. Eight bulbs were chosen at random for treatment for 24 to 120 hours with the River water collected in the years of 2005 and 2006 from sites in the cities of Tremembé and Aparecida (São Paulo state, Brazil). Daily measurements of the length of the roots grown from each bulb were carried out throughout the experiment. Mitotic index (MI) and frequency of micronuclei (MN) were determined for 2000 cells per root, using 3-5 root tips from other bulbs (7-10). Only in the roots treated with samples of the River water collected in 2005 in Tremembé city was there a decrease in the root length growth compared to the respective control. However, a reduction in MI values was verified for both sites analysed for that year. Considering the data involving root length growth and especially MI values, a cytotoxic potential is suggested for the water of the River Paraíba do Sul at Tremembé and Aparecida, in the year of 2005. On the other hand, since in this year the MN frequency was not affected with the river water treatments, genotoxicity is not assumed for the river water sampled at the aforementioned places.