SBR technology for wastewater treatment: suitable operational conditions for a nutrient removal

Actualment, la legislació ambiental ha esdevingut més restrictiva pel que fa a la descàrrega d'aigües residuals amb nutrients, especialment en les anomenades àrees sensibles o zones vulnerables. Arran d'aquest fet, s'ha estimulat el coneixement, desenvolupament i millora dels processos d'eliminació de nutrients. El Reactor Discontinu Seqüencial (RDS) o Sequencing Batch Reactor (SBR) en anglès, és un sistema de tractament de fangs actius que opera mitjançant un procediment d'omplerta-buidat. En aquest tipus de reactors, l'aigua residual és addicionada en un sol reactor que treballa per càrregues repetint un cicle (seqüència) al llarg del temps. Una de les característiques dels SBR és que totes les diferents operacions (omplerta, reacció, sedimentació i buidat) es donen en un mateix reactor. La tecnologia SBR no és nova d'ara. El fet, és que va aparèixer abans que els sistema de tractament continu de fangs actius. El precursor dels SBR va ser un sistema d'omplerta-buidat que operava en discontinu. Entre els anys 1914 i 1920, varen sorgir certes dificultats moltes d'elles a nivell d'operació (vàlvules, canvis el cabal d'un reactor a un altre, elevat temps d'atenció per l'operari...) per aquests reactors. Però no va ser fins a finals de la dècada dels '50 principis del '60, amb el desenvolupament de nous equipaments i noves tecnologies, quan va tornar a ressorgir l'interès pels SBRs. Importants millores en el camp del subministrament d'aire (vàlvules motoritzades o d'acció pneumàtica) i en el de control (sondes de nivell, mesuradors de cabal, temporitzadors automàtics, microprocessadors) han permès que avui en dia els SBRs competeixin amb els sistemes convencional de fangs actius. L'objectiu de la present tesi és la identificació de les condicions d'operació adequades per un cicle segons el tipus d'aigua residual a l'entrada, les necessitats del tractament i la qualitat desitjada de la sortida utilitzant la tecnologia SBR. Aquestes tres característiques, l'aigua a tractar, les necessitats del tractament i la qualitat final desitjada determinen en gran mesura el tractament a realitzar. Així doncs, per tal d'adequar el tractament a cada tipus d'aigua residual i les seves necessitats, han estat estudiats diferents estratègies d'alimentació. El seguiment del procés es realitza mitjançant mesures on-line de pH, OD i RedOx, els canvis de les quals donen informació sobre l'estat del procés. Alhora un altre paràmetre que es pot calcular a partir de l'oxigen dissolt és la OUR que és una dada complementària als paràmetres esmentats. S'han avaluat les condicions d'operació per eliminar nitrogen d'una aigua residual sintètica utilitzant una estratègia d'alimentació esglaonada, a través de l'estudi de l'efecte del nombre d'alimentacions, la definició de la llargada i el número de fases per cicle, i la identificació dels punts crítics seguint les sondes de pH, OD i RedOx. S'ha aplicat l'estratègia d'alimentació esglaonada a dues aigües residuals diferents: una procedent d'una indústria tèxtil i l'altra, dels lixiviats d'un abocador. En ambdues aigües residuals es va estudiar l'eficiència del procés a partir de les condicions d'operació i de la velocitat del consum d'oxigen. Mentre que en l'aigua residual tèxtil el principal objectiu era eliminar matèria orgànica, en l'aigua procedent dels lixiviats d'abocador era eliminar matèria orgànica i nitrogen. S'han avaluat les condicions d'operació per eliminar nitrogen i fòsfor d'una aigua residual urbana utilitzant una estratègia d'alimentació esglaonada, a través de la definició del número i la llargada de les fases per cicle, i la identificació dels punts crítics seguint les sondes de pH, OD i RedOx. S'ha analitzat la influència del pH i la font de carboni per tal d'eliminar fòsfor d'una aigua sintètica a partir de l'estudi de l'increment de pH a dos reactors amb diferents fonts de carboni i l'estudi de l'efecte de canviar la font de carboni. Tal i com es pot veure al llarg de la tesi, on s'han tractat diferents aigües residuals per a diferents necessitats, un dels avantatges més importants d'un SBR és la seva flexibilitat.

Integració 3D de detectors de píxels híbrids

La miniaturització de la industria microelectrònica és un fet del tot inqüestionables i la tecnologia CMOS no n'és una excepció. En conseqüència la comunitat científica s'ha plantejat dos grans reptes: En primer lloc portar la tecnologia CMOS el més lluny possible ('Beyond CMOS') tot desenvolupant sistemes d'altes prestacions com microprocessadors, micro - nanosistemes o bé sistemes de píxels. I en segon lloc encetar una nova generació electrònica basada en tecnologies totalment diferents dins l'àmbit de les Nanotecnologies. Tots aquests avanços exigeixen una recerca i innovació constant en la resta d'àrees complementaries com són les d'encapsulat. L'encapsulat ha de satisfer bàsicament tres funcions: Interfície elèctrica del sistema amb l'exterior, Proporcionar un suport mecànic al sistema i Proporcionar un camí de dissipació de calor. Per tant, si tenim en compte que la majoria d'aquests dispositius d'altes prestacions demanden un alt nombre d'entrades i sortides, els mòduls multixip (MCMs) i la tecnologia flip chip es presenten com una solució molt interessant per aquests tipus de dispositiu. L'objectiu d'aquesta tesi és la de desenvolupar una tecnologia de mòduls multixip basada en interconnexions flip chip per a la integració de detectors de píxels híbrids, que inclou: 1) El desenvolupament d'una tecnologia de bumping basada en bumps de soldadura Sn/Ag eutèctics dipositats per electrodeposició amb un pitch de 50µm, i 2) El desenvolupament d'una tecnologia de vies d'or en silici que permet interconnectar i apilar xips verticalment (3D packaging) amb un pitch de 100µm. Finalment aquesta alta capacitat d'interconnexió dels encapsulats flip chip ha permès que sistemes de píxels tradicionalment monolítics puguin evolucionar cap a sistemes híbrids més compactes i complexes, i que en aquesta tesi s'ha vist reflectit transferint la tecnologia desenvolupada al camp de la física d'altes energies, en concret implantant el sistema de bump bonding d'un mamògraf digital. Addicionalment s'ha implantat també un dispositiu detector híbrid modular per a la reconstrucció d'imatges 3D en temps real, que ha donat lloc a una patent.

Decentralized load balancing for highly irregular search problems

In this paper, we present a distributed computing framework for problems characterized by a highly irregular search tree, whereby no reliable workload prediction is available. The framework is based on a peer-to-peer computing environment and dynamic load balancing. The system allows for dynamic resource aggregation, does not depend on any specific meta-computing middleware and is suitable for large-scale, multi-domain, heterogeneous environments, such as computational Grids. Dynamic load balancing policies based on global statistics are known to provide optimal load balancing performance, while randomized techniques provide high scalability. The proposed method combines both advantages and adopts distributed job-pools and a randomized polling technique. The framework has been successfully adopted in a parallel search algorithm for subgraph mining and evaluated on a molecular compounds dataset. The parallel application has shown good calability and close-to linear speedup in a distributed network of workstations.

A comparison-based diagnosis algorithm tailored for crossed cube multiprocessor systems

Comparison-based diagnosis is an effective approach to system-level fault diagnosis. Under the Maeng-Malek comparison model (NM* model), Sengupta and Dahbura proposed an O(N-5) diagnosis algorithm for general diagnosable systems with N nodes. Thanks to lower diameter and better graph embedding capability as compared with a hypercube of the same size, the crossed cube has been a promising candidate for interconnection networks. In this paper, we propose a fault diagnosis algorithm tailored for crossed cube connected multicomputer systems under the MM* model. By introducing appropriate data structures, this algorithm runs in O(Nlog(2)(2) N) time, which is linear in the size of the input. As a result, this algorithm is significantly superior to the Sengupta-Dahbura's algorithm when applied to crossed cube systems. (C) 2004 Elsevier B.V. All rights reserved.

Pancyclicity of Mobius cubes with faulty nodes

An interconnection network with n nodes is four-pancyclic if it contains a cycle of length l for each integer l with 4 <= l <= n. An interconnection network is fault-tolerant four-pancyclic if the surviving network is four-pancyclic in the presence of faults. The fault-tolerant four-pancyclicity of interconnection networks is a desired property because many classical parallel algorithms can be mapped onto such networks in a communication-efficient fashion, even in the presence of failing nodes or edges. Due to some attractive properties as compared with its hypercube counterpart of the same size, the Mobius cube has been proposed as a promising candidate for interconnection topology. Hsieh and Chen [S.Y. Hsieh, C.H. Chen, Pancyclicity on Mobius cubes with maximal edge faults, Parallel Computing, 30(3) (2004) 407-421.] showed that an n-dimensional Mobius cube is four-pancyclic in the presence of up to n-2 faulty edges. In this paper, we show that an n-dimensional Mobius cube is four-pancyclic in the presence of up to n-2 faulty nodes. The obtained result is optimal in that, if n-1 nodes are removed, the surviving network may not be four-pancyclic. (C) 2005 Elsevier B.V. All rights reserved.

Microprocessor systems: an introduction

The aim of this book is to provide and introduction to microprocessor systems, their operation and design. It covers those topics needed by engineers and computer scientists who are interested in applying microprocessors in practical situations, namely computer hardware including logic and interfacing, software, in particular high level and assembly language programming, and the design and testing of such systems. The fundamental principles of micrprocessor systems are described and these are illustrated with reference to two microprocessors, the 32-bit MC68020 from Motorola and a single chip microcomputer, the 8051 from Intel; and in addition, interfacing to the general purpose STE bus is described. The details of the processors and the bus are concentrated in three chapters, thus allowing the presentation of the material to be independent of the microprocessors if that is desired, and permitting the specific details to be found easily.

Hardware development of the Yorick series of active vision systems

This paper presents a review of the design and development of the Yorick series of active stereo camera platforms and their integration into real-time closed loop active vision systems, whose applications span surveillance, navigation of autonomously guided vehicles (AGVs), and inspection tasks for teleoperation, including immersive visual telepresence. The mechatronic approach adopted for the design of the first system, including head/eye platform, local controller, vision engine, gaze controller and system integration, proved to be very successful. The design team comprised researchers with experience in parallel computing, robot control, mechanical design and machine vision. The success of the project has generated sufficient interest to sanction a number of revisions of the original head design, including the design of a lightweight compact head for use on a robot arm, and the further development of a robot head to look specifically at increasing visual resolution for visual telepresence. The controller and vision processing engines have also been upgraded, to include the control of robot heads on mobile platforms and control of vergence through tracking of an operator's eye movement. This paper details the hardware development of the different active vision/telepresence systems.

Parallel pipelined histogram architecture via c-slow retiming

A parallel pipelined array of cells suitable for realtime computation of histograms is proposed. The cell architecture builds on previous work to now allow operating on a stream of data at 1 pixel per clock cycle. This new cell is more suitable for interfacing to camera sensors or to microprocessors of 8-bit data buses which are common in consumer digital cameras. Arrays using the new proposed cells are obtained via C-slow retiming techniques and can be clocked at a 65% faster frequency than previous arrays. This achieves over 80% of the performance of two-pixel per clock cycle parallel pipelined arrays.

C-slow retimed parallel histogram architectures for consumer imaging devices

A parallel pipelined array of cells suitable for real-time computation of histograms is proposed. The cell architecture builds on previous work obtained via C-slow retiming techniques and can be clocked at 65 percent faster frequency than previous arrays. The new arrays can be exploited for higher throughput particularly when dual data rate sampling techniques are used to operate on single streams of data from image sensors. In this way, the new cell operates on a p-bit data bus which is more convenient for interfacing to camera sensors or to microprocessors in consumer digital cameras.

The influence of thermal treatment on the preparation of PNM and PMN-PT thin films

Ferroelectric thin films belong to a class of materials with great technological importance in optic fibers, micro-electromechanical systems, and microprocessors and computers memories.The (1-x)PbMg1/3Nb2/3O3(x)PbTiO3 (PMN-PT) thin films, with x=0, 0.1, 0.35 and 0.5, were prepared by Pechini's process and deposited by spin-coating on Si(100), Pt/Ti/SiO2/Si(100) and quartz substrates. The goal of the present paper is to verify the thermal treatment influence on the perovskite phase formation, which is desirable for these applications. The phase formation was analyzed by X-ray diffraction. The film's surface was characterized by atomic force microscopy to analyze the roughness and the homogeneity. The results of this study indicate that the optimum conditions for obtaining the perovskite phase using a Pt/Ti/SiO2/Si(100) substrate, were drying each deposited layer at 140 degreesC (heating plate), and a final thermal treatment at 600 degreesC for 3 h in a closed system with a lead-rich atmosphere. (C) 2003 Elsevier B.V. All rights reserved.

Virtual simulator for mobile robots navigation systems

This paper presents the virtual environment implementation for project simulation and conception of supervision and control systems for mobile robots, that are capable to operate and adapting in different environments and conditions. This virtual system has as purpose to facilitate the development of embedded architecture systems, emphasizing the implementation of tools that allow the simulation of the kinematic conditions, dynamic and control, with real time monitoring of all important system points. For this, an open control architecture is proposal, integrating the two main techniques of robotic control implementation in the hardware level: systems microprocessors and reconfigurable hardware devices. The implemented simulator system is composed of a trajectory generating module, a kinematic and dynamic simulator module and of a analysis module of results and errors. All the kinematic and dynamic results shown during the simulation can be evaluated and visualized in graphs and tables formats, in the results analysis module, allowing an improvement in the system, minimizing the errors with the necessary adjustments optimization. For controller implementation in the embedded system, it uses the rapid prototyping, that is the technology that allows, in set with the virtual simulation environment, the development of a controller project for mobile robots. The validation and tests had been accomplish with nonholonomics mobile robots models with diferencial transmission. © 2008 IEEE.

El Salvador: evolución económica durante 2005 y perspectivas para 2006

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Costa Rica: evolución económica durante 2005 y perspectivas para 2006

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Ubiquitous Computing: Any Ethical Implications?

In this article, the authors investigate, from an interdisciplinary perspective, possible ethical implications of the presence of ubiquitous computing systems in human perception/action. The term ubiquitous computing is used to characterize information-processing capacity from computers that are available everywhere and all the time, integrated into everyday objects and activities. The contrast in approach to aspects of ubiquitous computing between traditional considerations of ethical issues and the Ecological Philosophy view concerning its possible consequences in the context of perception/action are the underlying themes of this paper. The focus is on an analysis of how the generalized dissemination of microprocessors in embedded systems, commanded by a ubiquitous computing system, can affect the behaviour of people considered as embodied embedded agents.

Design and Performance Evaluation of Network-on-Chip Communication Protocols and Architectures

The scale down of transistor technology allows microelectronics manufacturers such as Intel and IBM to build always more sophisticated systems on a single microchip. The classical interconnection solutions based on shared buses or direct connections between the modules of the chip are becoming obsolete as they struggle to sustain the increasing tight bandwidth and latency constraints that these systems demand. The most promising solution for the future chip interconnects are the Networks on Chip (NoC). NoCs are network composed by routers and channels used to inter- connect the different components installed on the single microchip. Examples of advanced processors based on NoC interconnects are the IBM Cell processor, composed by eight CPUs that is installed on the Sony Playstation III and the Intel Teraflops pro ject composed by 80 independent (simple) microprocessors. On chip integration is becoming popular not only in the Chip Multi Processor (CMP) research area but also in the wider and more heterogeneous world of Systems on Chip (SoC). SoC comprehend all the electronic devices that surround us such as cell-phones, smart-phones, house embedded systems, automotive systems, set-top boxes etc... SoC manufacturers such as ST Microelectronics , Samsung, Philips and also Universities such as Bologna University, M.I.T., Berkeley and more are all proposing proprietary frameworks based on NoC interconnects. These frameworks help engineers in the switch of design methodology and speed up the development of new NoC-based systems on chip. In this Thesis we propose an introduction of CMP and SoC interconnection networks. Then focusing on SoC systems we propose: • a detailed analysis based on simulation of the Spidergon NoC, a ST Microelectronics solution for SoC interconnects. The Spidergon NoC differs from many classical solutions inherited from the parallel computing world. Here we propose a detailed analysis of this NoC topology and routing algorithms. Furthermore we propose aEqualized a new routing algorithm designed to optimize the use of the resources of the network while also increasing its performance; • a methodology flow based on modified publicly available tools that combined can be used to design, model and analyze any kind of System on Chip; • a detailed analysis of a ST Microelectronics-proprietary transport-level protocol that the author of this Thesis helped developing; • a simulation-based comprehensive comparison of different network interface designs proposed by the author and the researchers at AST lab, in order to integrate shared-memory and message-passing based components on a single System on Chip; • a powerful and flexible solution to address the time closure exception issue in the design of synchronous Networks on Chip. Our solution is based on relay stations repeaters and allows to reduce the power and area demands of NoC interconnects while also reducing its buffer needs; • a solution to simplify the design of the NoC by also increasing their performance and reducing their power and area consumption. We propose to replace complex and slow virtual channel-based routers with multiple and flexible small Multi Plane ones. This solution allows us to reduce the area and power dissipation of any NoC while also increasing its performance especially when the resources are reduced. This Thesis has been written in collaboration with the Advanced System Technology laboratory in Grenoble France, and the Computer Science Department at Columbia University in the city of New York.