Design of fast core node processor for packet forwarding without header modification in optical networks

We present a design of a fast all-optical core-node processor that performs packet-forwarding in optical networks without header-modification. The design is based on bit-serial architecture using TOADs as logic-gates that perform modulo-arithmetic to forward packets.

Computing with the Square Root of NOT

To the two classical reversible 1-bit logic gates, i.e. the identity gate (a.k.a. the follower) and the NOT gate (a.k.a. the inverter), we add an extra gate, the square root of NOT. Similarly, we add to the 24 classical reversible 2-bit circuits, both the square root of NOT and the controlled square root of NOT. This leads to a new kind of calculus, situated between classical reversible computing and quantum computing.

Ecological indicators for assessing and communicating seagrass status and trends in Florida Bay

A suite of seagrass indicator metrics is developed to evaluate four essential measures of seagrass community status for Florida Bay. The measures are based on several years of monitoring data using the Braun-Blanquet Cover Abundance (BBCA) scale to derive information about seagrass spatial extent, abundance, species diversity and presence of target species. As ecosystem restoration proceeds in south Florida, additional freshwater will be discharged to Florida Bay as a means to restore the bay's hydrology and salinity regime. Primary hypotheses about restoring ecological function of the keystone seagrass community are based on the premise that hydrologic restoration will increase environmental variability and reduce hypersalinity. This will create greater niche space and permit multiple seagrass species to co-exist while maintaining good environmental conditions for Thalassia testudinum, the dominant climax seagrass species. Greater species diversity is considered beneficial to habitat for desired higher trophic level species such as forage fish and shrimp. It is also important to maintenance of a viable seagrass community that will avoid die-off events observed in the past. Indicator metrics are assigned values at the basin spatial scale and are aggregated to five larger zones. Three index metrics are derived by combining the four indicators through logic gates at the zone spatial scale and aggregated to derive a single bay-wide system status score standardized on the System-wide Indicator protocol. The indicators will provide a way to assess progress toward restoration goals or reveal areas of concern. Reporting for each indicator, index and overall system status score is presented in a red–yellow–green format that summarizes information in a readily accessible form for mangers, policy-makers and stakeholders in planning and implementing an adaptive management strategy.

Micro-Fabricated Surface Trap and Cavity Integration for Trapped Ion Quantum Computing

Atomic ions trapped in micro-fabricated surface traps can be utilized as a physical platform with which to build a quantum computer. They possess many of the desirable qualities of such a device, including high fidelity state preparation and readout, universal logic gates, long coherence times, and can be readily entangled with each other through photonic interconnects. The use of optical cavities integrated with trapped ion qubits as a photonic interface presents the possibility for order of magnitude improvements in performance in several key areas of their use in quantum computation. The first part of this thesis describes the design and fabrication of a novel surface trap for integration with an optical cavity. The trap is custom made on a highly reflective mirror surface and includes the capability of moving the ion trap location along all three trap axes with nanometer scale precision. The second part of this thesis demonstrates the suitability of small micro-cavities formed from laser ablated fused silica substrates with radii of curvature in the 300-500 micron range for use with the mirror trap as part of an integrated ion trap cavity system. Quantum computing applications for such a system include dramatic improvements in the photonic entanglement rate up to 10 kHz, the qubit measurement time down to 1 microsecond, and the measurement error rates down to the 10e-5 range. The final part of this thesis details a performance simulator for exploring the physical resource requirements and performance demands to scale such a quantum computer to sizes capable of performing quantum algorithms beyond the limits of classical computation.

Improving the freshman electrical and computer engineering lab

This thesis covers the challenges of creating and maintaining an introductory engineering laboratory. The history of the University of Illinois Electrical and Computer Engineering department’s introductory course, ECE 110, is recounted. The current state of the course, as of Fall 2008, is discussed along with current challenges arising from the use of a hand-wired prototyping board with logic gates. A plan for overcoming these issues using a new microcontroller-based board with a pseudo hardware description language is discussed. The new microcontroller based system implementation is extensively detailed along with its new accompanying description language. This new system was tried in several sections of the Fall 2008 semester alongside the old system; the students’ final performances with the two different approaches are compared in terms of design, performance, complexity, and enjoyment. The system in its first run shows great promise, increasing the students’ enjoyment, and improving the performance of their designs.

Nondeterministic gates for photonic single-rail quantum logic

We discuss techniques for producing, manipulating, and measuring qubits encoded optically as vacuum- and single-photon states. We show that a universal set of nondeterministic gates can be constructed using linear optics and photon counting. We investigate the efficacy of a test gate given realistic detector efficiencies.

Optimal networks with NOR-OR gates and Wired OR logic /

Originally presented as the author's thesis (M.S.), University of Illinois at Urbana-Champaign.

Synthesis of optimal double-rail logic networks using NOR-OR gates by integer programming.

"Supported in part by ... Grant no. NSF GJ-503."

Optoelectronic Logic Functions Based on Reconfigurable SiC Multilayer Devices

WDM multilayered SiC/Si devices based on a-Si:H and a-SiC:H filter design are approached from a reconfigurable point of view. Results show that the devices, under appropriated optical bias, act as reconfigurable active filters that allow optical switching and optoelectronic logic functions development. Under front violet irradiation the magnitude of the red and green channels are amplified and the blue and violet reduced. Violet back irradiation cuts the red channel, slightly influences the magnitude of the green and blue ones and strongly amplifies de violet channel. This nonlinearity provides the possibility for selective removal of useless wavelengths. Particular attention is given to the amplification coefficient weights, which allow taking into account the wavelength background effects when a band needs to be filtered from a wider range of mixed signals, or when optical active filter gates are used to select and filter input signals to specific output ports in WDM communication systems. A truth table of an encoder that performs 8-to-1 multiplexer (MUX) function is presented.

Fault Tolerant Error Coding and Detection using Reversible Gates

In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, quantum computing and nanotechnology. Low power circuits implemented using reversible logic that provides single error correction – double error detection (SEC-DED) is proposed in this paper. The design is done using a new 4 x 4 reversible gate called ‘HCG’ for implementing hamming error coding and detection circuits. A parity preserving HCG (PPHCG) that preserves the input parity at the output bits is used for achieving fault tolerance for the hamming error coding and detection circuits.

Quick Addition of Decimals Using Reversible Conservative Logic

In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, nanotechnology and quantum computing. This research proposes quick addition of decimals (QAD) suitable for multi-digit BCD addition, using reversible conservative logic. The design makes use of reversible fault tolerant Fredkin gates only. The implementation strategy is to reduce the number of levels of delay there by increasing the speed, which is the most important factor for high speed circuits.

Strange attractor in optical logic cells

Optical logic cells, employed in several tasks as optical computing or optically controlled switches for photonic switching, offer a very particular behavior when the working conditions are slightly modified. One of the more striking changes occurs when some delayed feedback is applied between one of the possible output gates and a control input. Some of these new phenomena have been studied by us and reported in previous papers. A chaotic behavior is one of the more characteristic results and its possible applications range from communications to cryptography. But the main problem related with this behavior is the binary character of the resulting signal. Most of the nowadays-employed techniques to analyze chaotic signals concern to analogue signals where algebraic equations are possible to obtain. There are no specific tools to study digital chaotic signals. Some methods have been proposed. One of the more used is equivalent to the phase diagram in analogue chaos. The binary signal is converted to hexadecimal and then analyzed. We represented the fractal characteristics of the signal. It has the characteristics of a strange attractor and gives more information than the obtained from previous methods. A phase diagram, as the one obtained by previous techniques, may fully cover its surface with the trajectories and almost no information may be obtained from it. Now, this new method offers the evolution around just a certain area being this lines the strange attractor.

Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis

Conventional dual-rail precharge logic suffers from difficult implementations of dual-rail structure for obtaining strict compensation between the counterpart rails. As a light-weight and high-speed dual-rail style, balanced cell-based dual-rail logic (BCDL) uses synchronised compound gates with global precharge signal to provide high resistance against differential power or electromagnetic analyses. BCDL can be realised from generic field programmable gate array (FPGA) design flows with constraints. However, routings still exist as concerns because of the deficient flexibility on routing control, which unfavourably results in bias between complementary nets in security-sensitive parts. In this article, based on a routing repair technique, novel verifications towards routing effect are presented. An 8 bit simplified advanced encryption processing (AES)-co-processor is executed that is constructed on block random access memory (RAM)-based BCDL in Xilinx Virtex-5 FPGAs. Since imbalanced routing are major defects in BCDL, the authors can rule out other influences and fairly quantify the security variants. A series of asymptotic correlation electromagnetic (EM) analyses are launched towards a group of circuits with consecutive routing schemes to be able to verify routing impact on side channel analyses. After repairing the non-identical routings, Mutual information analyses are executed to further validate the concrete security increase obtained from identical routing pairs in BCDL.

NOR network transduction procedures : "merging of gates" and "substitution of gates" for fan-in and fan-out restricted networks, NETTRA-G3-FIFO and NETTRA-PG1-FIFO /

"December 1974."--T.p.

Results of the synthesis of optimal networks of AND and OR gates for four-variable switching functions by a branch-and-bound computer program /

Bibliography: p. 39 (2d group)