A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches

A fully-differential switched-capacitor sample-and-hold (S/H) circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter (ADC) was designed and fabricated using a 0.35-μm CMOS process. Capacitor fliparound architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier (OTA) was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range (SFDR) of 67 dB and a signal-to-noise ratio (SNR) of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12 mm~2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.

A Compact Direct Digital Frequency Synthesizer for the Rubidium Atomic Frequency Standard

A compact direct digital frequency synthesizer （DDFS） for system-on-chip implementation of the high precision rubidium atomic frequency standard is developed. For small chip size and low power consumption, the phase to sine mapping data is compressed using sine symmetry technique, sine-phase difference technique, quad line approximation technique,and quantization and error read only memory （QE-ROM） technique. The ROM size is reduced by 98% using these techniques. A compact DDFS chip with 32bit phase storage depth and a 10bit on-chip digital to analog converter has been successfully implemented using a standard 0.35μm CMOS process. The core area of the DDFS is 1.6mm^2. It consumes 167mW at 3.3V,and its spurious free dynamic range is 61dB.

基于MAX5307和DSP的多回路测控系统设计

提出了一种多回路测控系统的设计方案。该方案仅使用一个DSP(数字信号处理器)及一个多通道集成的D/A转换器件MAX5307,不仅同时保证了多个测控回路的实时性及控制精度,而且实现简单,成本低廉。文中结合实际系统,给出了其具体的硬件和软件实现。该方法具有广泛的适用性,对类似系统的设计具有参考价值。

多路温度测控系统的设计

目的利用单片机技术设计多路温度测控系统,实现多路温度的测量和控制.方法系统以单片机AT89C52为核心,利用多路转换器和新型数字器件MAX6675构成8路K型热电偶温度测量电路,利用D/A转换器AD7528和驱动电路构成输出电路,实现8路一一对应的闭环温度测量控制.系统软件采用PID控制器.结果实践证明,可根据需要增减系统温度信号采样通道的数目,使用软件抗干扰措施,提高了采样数据的可靠性.简化了输入输出硬件结构,使系统具有低成本高速度和较好的测量控制精度.结论多路温度测控系统作为整机适用于现场测量控制应用,也可作为多路温度控制模块应用在体积小、温度测量精度要求较高的大型系统中.

宽频带地震数据采集系统的研制

The seismic data acquisition system is the most important equipment for seismic prospecting. The geophysicists have been paying high attention to the specification of the equipment used in seismic prospecting. Its specification and performance are of great concerned to acquire precisely and accurately seismic data, which show us stratum frame. But, by this time, limited by the technology, most of the Broad-band Seismic Recorder (BSR) for lithosphere research of our country were bought from fremdness which were very costliness and maintained discommodiously. So it is very important to study the seismic data acquisition system.The subject of the thesis is the research of the BSR, several items were included, such as: seismic data digitizer and its condition monitor design.In the first chapter, the author explained the significance of the implement of BSR, expatiated the requirement to the device and introduced the actuality of the BSR in our country.In the second chapter, the collectivity architecture of the BSR system was illustrated. Whereafter, the collectivity target and guideline of the performance of the system design were introduced. The difficulty of the system design and some key technology were analyzed, such as the Electro Magnetic Compatibility (EMC), system reliability technology and so on.In the third chapter, some design details of BSR were introduced. In the recorder, the former analog to digital converter (ADC) was separated from the later data transition module. According to the characteristic of seismic data acquisition system, a set high-resolution 24-bit ADC chip was chosen to the recorder design scheme. As the following part, the noise performance of the seismic data channel was analyzed.In the fourth chapter, the embedded software design of each board and the software design of the workstation were introduced. At the same time the communication protocol of the each module was recommendedAt the last part of this thesis, the advantages and the practicability of the BSR system design were summarized, and the next development items were suggested.

Resonant power conversion topologies for inductive charging of electrical vehicle batteries

This thesis is concerned with inductive charging of electric vehicle batteries. Rectified power form the 50/60 Hz utility feeds a dc-ac converter which delivers high-frequency ac power to the electric vehicle inductive coupling inlet. The inlet configuration has been defined by the Society of Automotive Engineers in Recommended Practice J-1773. This thesis studies converter topologies related to the series resonant converter. When coupled to the vehicle inlet, the frequency-controlled series-resonant converter results in a capacitively-filtered series-parallel LCLC (SP-LCLC) resonant converter topology with zero voltage switching and many other desirable features. A novel time-domain transformation analysis, termed Modal Analysis, is developed, using a state variable transformation, to analyze and characterize this multi-resonant fourth-orderconverter. Next, Fundamental Mode Approximation (FMA) Analysis, based on a voltage-source model of the load, and its novel extension, Rectifier-Compensated FMA (RCFMA) Analysis, are developed and applied to the SP-LCLC converter. The RCFMA Analysis is a simpler and more intuitive analysis than the Modal Analysis, and provides a relatively accurate closed-form solution for the converter behavior. Phase control of the SP-LCLC converter is investigated as a control option. FMA and RCFMA Analyses are used for detailed characterization. The analyses identify areas of operation, which are also validated experimentally, where it is advantageous to phase control the converter. A novel hybrid control scheme is proposed which integrates frequency and phase control and achieves reduced operating frequency range and improved partial-load efficiency. The phase-controlled SP-LCLC converter can also be configured with a parallel load and is an excellent option for the application. The resulting topology implements soft-switching over the entire load range and has high full-load and partial-load efficiencies. RCFMA Analysis is used to analyze and characterize the new converter topology, and good correlation is shown with experimental results. Finally, a novel single-stage power-factor-corrected ac-dc converter is introduced, which uses the current-source characteristic of the SP-LCLC topology to provide power factor correction over a wide output power range from zero to full load. This converter exhibits all the advantageous characteristics of its dc-dc counterpart, with a reduced parts count and cost. Simulation and experimental results verify the operation of the new converter.

A 76-84 GHz SiGe power amplifier array employing low-loss four-way differential combining transformer

This paper presents holistic design of a novel four-way differential power-combining transformer for use in millimeter-wave power-amplifier (PA). The combiner with an inner radius of 25 µm exhibits a record low insertion loss of 1.25 dB at 83.5 GHz. It is designed to simultaneously act as a balanced-to-unbalanced converter, removing the need for additional BALUNs typically required in differential circuits. A complete circuit comprised of a power splitter, two-stage differential cascode PA array, a power combiner as well as input and output matching elements was designed and realized in SiGe technology with f/f 170/250 GHz. Measured small-signal gain of at least 16.8 dB was obtained from 76.4 to 85.3 GHz with a peak 19.5 dB at 83 GHz. The prototype delivered 12.5 dBm output referred 1 dB compression point and 14 dBm saturated output power when operated from a 3.2 V dc supply voltage at 78 GHz.

Q-enhancement with on-chip inductor optimization for reconfigurable Δ-Σ radio-frequency ADC

The paper details on-chip inductor optimization for a reconfigurable continuous-time delta-sigma (Δ-Σ) modulator based radio-frequency analog-to-digital converter. Inductor optimisation enables the Δ-Σ modulator with Q enhanced LC tank circuits employing a single high Q-factor on-chip inductor and lesser quantizer levels thereby reducing the circuit complexity for excess loop delay, power dissipation and dynamic element matching. System level simulations indicate at a Q-factor of 75 Δ- Σ modulator with a 3-level quantizer achieves dynamic ranges of 106, 82 dB and 84 dB for RFID, TETRA, and Galileo over bandwidths of 200 kHz, 10 MHz and 40 MHz respectively.

Comando de ondulador de tensão trifásico por PWM e técnica U/F com implementação por microcontrolador

Dissertação para obtenção do grau de Mestre em Engenharia Electrotécnica Ramo de Automação e Electrónica Industrial

Retificador trifásico controlado com fator de potência quase unitário

Dissertação de Mestrado para obtenção do grau de Mestre em Engenharia Eletrotécnica Ramo Automação e Eletrónica Industrial

PV inverters for module level applications

Dissertação para obtenção do Grau de Mestre em Energias Renováveis – Conversão Eléctrica e Utilização Sustentáveis

Efficient Transmitter/Receiver Architectures for High Performance Wireless Applications

The thesis focuses on efficient design methods and reconfiguration architectures suitable for higher performance wireless communication .The work presented in this thesis describes the development of compact,inexpensive and low power communication devices that are robust,testable and capable of handling multiple communication standards.A new multistandard Decimation Filter Design Toolbox is developed in MATLAB GUIDE environment.RNS based dual-mode decimation filters reconfigurable for WCDMA/WiMAX and WCDMA/WLANa standards are designed and implemented.It offers high speed operation with lesser area requirement and lower dynamic power dissipation.A novel sigma-delta based direct analog-to-residue converter that reduces the complexity of RNS conversion circuitry is presented.The performance of an OFDM communication system with a new RRNS-convolutional concatenated coding is analysed and improved BER performance is obtained under different channel conditions. Easily testable MAC units for filters are presented using Reed-Muller logic for realization.

Wideband Low-Distortion Sigma-Delta ADC for WLAN

This work presents a wideband low-distortion sigmadelta analog-to-digital converter (ADC) for Wireless Local Area Network (WLAN) standard. The proposed converter makes use of low-distortion swing suppression SDM architecture which is highly suitable for low oversampling ratios to attain high linearity over a wide bandwidth. The modulator employs a 2-2 cascaded sigma-delta modulator with feedforward path with a single-bit quantizer in the first stage and 4-bit in the second stage. The modulator is designed in TSMC 0.18um CMOS technology and operates at 1.8V supply voltage. Simulation results show that, a peak SNDR of 57dB and a spurious free dynamic range (SFDR) of 66dB is obtained for a 10MHz signal bandwidth, and an oversampling ratio of 8.

Fine wire resistance thermometer amplifier for atmospheric measurements

An improved amplifier for atmospheric fine wire resistance thermometry is described. The amplifier uses a low excitation current (50 mu A). This is shown to ensure negligible self-heating of the low mass fine wire resistance sensor, compared with measured nocturnal surface air temperature fluctuations. The system provides sufficient amplification for a +/- 50 degrees C span using a +/- 5 V dynamic range analog-to-digital converter, with a noise level of less than 0.01 degrees C. A Kelvin four-wire connection cancels the effect of long lead resistances: a 50 m length of screened cable connecting the Reading design of fine wire thermometer to the amplifier produced no measurable temperature change at 12 bit resolution.

Uma fonte chaveada de 50kW com correção de fator de potência para alimentação de uma tocha de plasma Indutiva utilizando técnicas de controle digital

This work deals with the development of an experimental study on a power supply of high frequency that provides the toch plasmica to be implemented in PLASPETRO project, which consists of two static converters developed by using Insulated Gate Bipolar Transistor (IGBT). The drivers used to control these keys are triggered by Digital Signal Processor (DSP) through optical fibers to reduce problems with electromagnetic interference (EMI). The first stage consists of a pre-regulator in the form of an AC to DC converter with three-phase boost power factor correction which is the main theme of this work, while the second is the source of high frequency itself. A series-resonant inverter consists of four (4) cell inverters operating in a frequency around 115 kHz each one in soft switching mode, alternating itself to supply the load (plasma torch) an alternating current with a frequency of 450 kHz. The first stage has the function of providing the series-resonant inverter a DC voltage, with the value controlled from the power supply provided by the electrical system of the utility, and correct the power factor of the system as a whole. This level of DC bus voltage at the output of the first stage will be used to control the power transferred by the inverter to the load, and it may vary from 550 VDC to a maximum of 800 VDC. To control the voltage level of DC bus driver used a proportional integral (PI) controller and to achieve the unity power factor it was used two other proportional integral currents controllers. Computational simulations were performed to assist in sizing and forecasting performance. All the control and communications needed to stage supervisory were implemented on a DSP