Lipophilic nucleosides: studies toward self-assembled functional materials

Molecular self-assembly takes advantage of supramolecular non-covalent interactions (ionic, hydrophobic, van der Waals, hydrogen and coordination bonds) for the construction of organized and tunable systems. In this field, lipophilic guanosines can represent powerful building blocks thanks to their aggregation proprieties in organic solvents, which can be controlled by addition or removal of cations. For example, potassium ion can template the formation of piled G-quartets structures, while in its absence ribbon-like G aggregates are generated in solution. In this thesis we explored the possibility of using guanosines as scaffolds to direct the construction of ordered and self-assembled architectures, one of the main goals of bottom-up approach in nanotechnology. In Chapter III we will describe Langmuir-Blodgett films obtained from guanosines and other lipophilic nucleosides, revealing the “special” behavior of guanine in comparison with the other nucleobases. In Chapter IV we will report the synthesis of several thiophene-functionalized guanosines and the studies towards their possible use in organic electronics: the pre-programmed organization of terthiophene residues in ribbon aggregates could allow charge conduction through π-π stacked oligothiophene functionalities. The construction and the behavior of some simple electronic nanodevices based on these organized thiopehene-guanosine hybrids has been explored.

Photophysical investigation of light-harvesting systems for solar-to-fuel conversion

In recent years, an increasing attention has been given to the optimization of the performances of new supramolecular systems, as antennas for light collection. In such background, the aim of this thesis was the study of multichromophoric architectures capable of performing such basic action. A synthetic antenna should consist of a structure with large UV-Vis absorption cross-section, panchromatic absorption, fixed orientation of the components and suitable energy gradients between them, in order to funnel absorbed energy towards a specific site, through fast energy-transfer processes. Among the systems investigated in this thesis, three suitable classes of compounds can be identified: 1) transition metal-based multichromophoric arrays, as models for antenna construction, 2) free-base trans-A2B-phenylcorroles, as self-assembling systems to make effective mimics of the photosynthetic system, and 3) a natural harvester, the Photosystem I, immobilized on the photoanode of a solar-to-fuel conversion device. The discussion starts with the description of the photophysical properties of dinuclear quinonoid organometallic systems, able to fulfil some of the above mentioned absorption requirements, displaying in some cases panchromatic absorption. The investigation is extended to the efficient energy transfer processes occurring in supramolecular architectures, suitably organized around rigid organic scaffolds, such as spiro-bifluorene and triptycene. Furthermore, the photophysical characterization of three trans-A2B-phenylcorroles with different substituents on the meso-phenyl ring is introduced, revealing the tendency of such macrocycles to self-organize into dimers, by mimicking natural self-aggregates antenna systems. In the end, the photophysical analysis moved towards the natural super-complex PSI-LHCI, immobilized on the hematite surface of the photoanode of a bio-hybrid dye-sensitized solar cell. The importance of the entire work is related to the need for a deep understanding of the energy transfer mechanisms occurring in supramolecules, to gain insights and improve the strategies for governing the directionality of the energy flow in the construction of well-performing antenna systems.

How different is water crystallization from polymer crystallization under confinement?

Ziel der vorliegenden Dissertation war es, Einblicke in das Kristallisationsverhalten weicher Materie („soft matter“), wie verschiedener Polymere oder Wasser, unter räumlicher Einschränkung („confinement“) zu erlangen. Dabei sollte untersucht werden, wie, weshalb und wann die Kristallisation in nanoporösen Strukturen eintritt. Desweiteren ist Kristallisation weicher Materie in nanoporösen Strukturen nicht nur aus Aspekten der Grundlagenforschung von großem Interesse, sondern es ergeben sich zahlreiche praktische Anwendungen. Durch die gezielte Steuerung der Kristallinität von Polymeren könnten somit Materialien mit verschiendenen mechanischen und optischen Eigenschaften erhalten werden. Desweiteren wurde auch räumlich eingeschränktes Wasser untersucht. Dieses spielt eine wichtige Rolle in der Molekularbiologie, z.B. für das globuläre Protein, und als Wolkenkondensationskeime in der Atmosphärenchemie und Physik. Auch im interstellaren Raum ist eingeschränktes Wasser in Form von Eispartikeln anzutreffen. Die Kristallisation von eingeschränktem Wasser zu verstehen und zu beeinflussen ist letztlich auch für die Haltbarkeit von Baumaterialien wie etwa Zement von großem Interesse.rnUm dies zu untersuchen wird Wasser in der Regel stark abgekühlt und das Kristallisationsverhalten in Abhängigkeit des Volumens untersucht. Dabei wurde beobachtet, dass Mikro- bzw. Nanometer große Volumina erst ab -38 °C bzw. -70 °C kristallisieren. Wasser unterliegt dabei in der Regel dem Prozess der homogenen Nukleation. In der Regel gefriert Wasser aber bei höheren Temperaturen, da durch Verunreinigungen eine vorzeitige, heterogene Nukleation eintritt.rnDie vorliegende Arbeit untersucht die sachdienlichen Phasendiagramme von kristallisierbaren Polymeren und Wasser unter räumlich eingeschränkten Bedingungen. Selbst ausgerichtetes Aluminiumoxid (AAO) mit Porengrößen im Bereich von 25 bis 400 nm wurden als räumliche Einschränkung sowohl für Polymere als auch für Wasser gewählt. Die AAO Nanoporen sind zylindrisch und parallel ausgerichtet. Außerdem besitzen sie eine gleichmäßige Porenlänge und einen gleichmäßigen Durchmesser. Daher eignen sie sich als Modelsystem um Kristallisationsprozesse unter wohldefinierter räumlicher Einschränkung zu untersuchen.rnEs wurden verschiedene halbkristalline Polymere verwendet, darunter Poly(ethylenoxid), Poly(ɛ-Caprolacton) und Diblockcopolymere aus PEO-b-PCL. Der Einfluss der Porengröße auf die Nukleation wurde aus verschiedenen Gesichtspunkten untersucht: (i) Einfluss auf den Nukleationmechanismus (heterogene gegenüber homogener Nukleation), (ii) Kristallorientierung und Kristallinitätsgrad und (iii) Zusammenhang zwischen Kristallisationstemperatur bei homogener Kristallisation und Glasübergangstemperatur.rnEs konnte gezeigt werden, dass die Kristallisation von Polymeren in Bulk durch heterogene Nukleation induziert wird und das die Kristallisation in kleinen Poren hauptsächlich über homogene Nukleation mit reduzierter und einstellbarer Kristallinität verläuft und eine hohe Kristallorientierung aufweist. Durch die AAOs konnte außerdem die kritische Keimgröße für die Kristallisation der Polymere abgeschätzt werden. Schließlich wurde der Einfluss der Polydispersität, von Oligomeren und anderen Zusatzstoffen auf den Nukleationsmechanismus untersucht.rn4rnDie Nukleation von Eis wurde in den selben AAOs untersucht und ein direkter Zusammenhang zwischen dem Nukleationstyp (heterogen bzw. homogen) und der gebildeten Eisphase konnte beobachtet werden. In größeren Poren verlief die Nukleation heterogen, wohingegen sie in kleineren Poren homogen verlief. Außerdem wurde eine Phasenumwandlung des Eises beobachtet. In den größeren Poren wurde hexagonales Eis nachgewiesen und unter einer Porengröße von 35 nm trat hauptsächlich kubisches Eis auf. Nennenswerter Weise handelte es sich bei dem kubischem Eis nicht um eine metastabile sondern eine stabile Phase. Abschließend wird ein Phasendiagramm für räumlich eingeschränktes Wasser vorgeschlagen. Dieses Phasendiagramm kann für technische Anwendungen von Bedeutung sein, so z.B. für Baumaterial wie Zement. Als weiteres Beispiel könnten AAOs, die die heterogene Nukleation unterdrücken (Porendurchmesser ≤ 35 nm) als Filter für Reinstwasser zum Einsatz kommen.rnNun zur Anfangs gestellten Frage: Wie unterschiedlich sind Wasser und Polymerkristallisation voneinander unter räumlicher Einschränkung? Durch Vergleich der beiden Phasendiagramme kommen wir zu dem Schluss, dass beide nicht fundamental verschieden sind. Dies ist zunächst verwunderlich, da Wasser ein kleines Molekül ist und wesentlich kleiner als die kleinste Porengröße ist. Wasser verfügt allerdings über starke Wasserstoffbrückenbindungen und verhält sich daher wie ein Polymer. Daher auch der Name „Polywasser“.

Preparation of highly-ordered TiO₂ nanotube arrays and their applications in Dye-sensitized solar cells

Titanium oxide is an important semiconductor, which is widely applied for solar cells. In this research, titanium oxide nanotube arrays were synthesized by anodization of Ti foil in the electrolyte composed of ethylene glycol containing 2 vol % H2O and 0.3 wt % NH4F. The voltages of 40V-50V were employed for the anodizing process. Pore diameters and lengths of the TiO2 nanotubes were evaluated by field emission scanning electron microscope (FESEM). The obtained highly-ordered titanium nanotube arrays were exploited to fabricate photoelectrode for the Dye-sensitized solar cells (DSSCS). The TiO2 nanotubes based DSSCS exhibited an excellent performance with a high short circuit current and open circuit voltage as well as a good power conversion efficiency. Those can be attributed to the high surface area and one dimensional structure of TiO2 nanotubes, which could hold a large amount of dyes to absorb light and help electron percolation process to hinder the recombination during the electrons diffusion in the electrolyte.

Self-Absorption and Luminescence Quantum Yields of Dye-Zeolite L Composites

Electronic absorption and fluorescence spectra based on transmission measurements of thin layers obtained from new perylene−zeolite L composites and new dye1,dye2−zeolite L sandwich composites, the latter acting as antenna systems, have been investigated and analyzed. The influence of extra- and intraparticle self-absorption on the spectral shape and fluorescence quantum yield is discussed in detail. Due to its intraparticle origin, self-absorption and re-emission can often not be avoided in organized systems such as dye−zeolite L composites where a high density of chromophores is a prerequisite for obtaining the desired photophysical properties. We show, however, that it can be avoided or at least minimized by preparing dye1,dye2−zeolite L sandwich composites where donors are present in a much larger amount than the acceptors because they act as antenna systems.

Two-Dimensional Supramolecular Electron Spin Arrays

A bottom-up approach is introduced to fabricate two-dimensional self-assembled layers of molecular spin-systems containing Mn and Fe ions arranged in a chessboard lattice. We demonstrate that the Mn and Fe spin states can be reversibly operated by their selective response to coordination/decoordination of volatile ligands like ammonia (NH3).

Self-Assessment in a Competency-Based Curriculum: Preliminary Findings

Introduction: The introduction of the ACGME core competency framework brought challenges of developing appropriate evaluation tools (i.e. self assessment) to provide evidence of competency. Baylor College of Medicine has 43 competency goals organized within the 6 ACGME domains, each domain having 4-10 goals. [See PDF for complete abstract]

Surface patterned polymer micro-cantilever arrays for sensing

Microinjection molding was employed to fabricate low-cost polymer cantilever arrays for sensor applications. Cantilevers with micrometer dimensions and aspect ratios as large as 10 were successfully manufactured from polymers, including polypropylene and polyvinylidenfluoride. The cantilevers perform similar to the established silicon cantilevers, with Q-factors in the range of 10–20. Static deflection of gold coated polymer cantilevers was characterized with heat cycling and self-assembled monolayer formation of mercaptohexanols. A hybrid mold concept allows easy modification of the surface topography, enabling customized mechanical properties of individual cantilevers. Combined with functionalization and surface patterning, the cantilever arrays are qualified for biomedical applications

High-density metallic nano-emitter arrays and their field emission characteristics

We report the fabrication and field emission properties of high-density nano-emitter arrays with on-chip electron extraction gate electrodes and up to 106 metallic nanotips that have an apex curvature radius of a few nanometers and a the tip density exceeding 108 cm−2. The gate electrode was fabricated on top of the nano-emitter arrays using a self-aligned polymer mask method. By applying a hot-press step for the polymer planarization, gate–nanotip alignment precision below 10 nm was achieved. Fabricated devices exhibited stable field electron emission with a current density of 0.1 A cm−2, indicating that these are promising for applications that require a miniature high-brightness electron source.

Substrate nanopatterning by e-beam lithography to growth ordered arrays of III-nitride nanodetectors, white light emitters, and solar cells

III-nitride nanorods have attracted much scientific interest during the last decade because of their unique optical and electrical properties [1,2]. The high crystal quality and the absence of extended defects make them ideal candidates for the fabrication of high efficiency opto-electronic devices such as nano-photodetectors, light-emitting diodes, and solar cells [1-3]. Nitride nanorods are commonly grown in the self-assembled mode by plasma-assisted molecular beam epitaxy (MBE) [4]. However, self-assembled nanorods are characterized by inhomogeneous heights and diameters, which render the device processing very difficult and negatively affect the electronic transport properties of the final device. For this reason, the selective area growth (SAG) mode has been proposed, where the nanorods preferentially grow with high order on pre-defined sites on a pre-patterned substrate

Response threshold models, stochastic learning automata and ant colony optimization-based decentralized self-coordination algorithms for heterogeneous multi-tasks distribution in multi-robot systems

In recent decades, there has been an increasing interest in systems comprised of several autonomous mobile robots, and as a result, there has been a substantial amount of development in the eld of Articial Intelligence, especially in Robotics. There are several studies in the literature by some researchers from the scientic community that focus on the creation of intelligent machines and devices capable to imitate the functions and movements of living beings. Multi-Robot Systems (MRS) can often deal with tasks that are dicult, if not impossible, to be accomplished by a single robot. In the context of MRS, one of the main challenges is the need to control, coordinate and synchronize the operation of multiple robots to perform a specic task. This requires the development of new strategies and methods which allow us to obtain the desired system behavior in a formal and concise way. This PhD thesis aims to study the coordination of multi-robot systems, in particular, addresses the problem of the distribution of heterogeneous multi-tasks. The main interest in these systems is to understand how from simple rules inspired by the division of labor in social insects, a group of robots can perform tasks in an organized and coordinated way. We are mainly interested on truly distributed or decentralized solutions in which the robots themselves, autonomously and in an individual manner, select a particular task so that all tasks are optimally distributed. In general, to perform the multi-tasks distribution among a team of robots, they have to synchronize their actions and exchange information. Under this approach we can speak of multi-tasks selection instead of multi-tasks assignment, which means, that the agents or robots select the tasks instead of being assigned a task by a central controller. The key element in these algorithms is the estimation ix of the stimuli and the adaptive update of the thresholds. This means that each robot performs this estimate locally depending on the load or the number of pending tasks to be performed. In addition, it is very interesting the evaluation of the results in function in each approach, comparing the results obtained by the introducing noise in the number of pending loads, with the purpose of simulate the robot's error in estimating the real number of pending tasks. The main contribution of this thesis can be found in the approach based on self-organization and division of labor in social insects. An experimental scenario for the coordination problem among multiple robots, the robustness of the approaches and the generation of dynamic tasks have been presented and discussed. The particular issues studied are: Threshold models: It presents the experiments conducted to test the response threshold model with the objective to analyze the system performance index, for the problem of the distribution of heterogeneous multitasks in multi-robot systems; also has been introduced additive noise in the number of pending loads and has been generated dynamic tasks over time. Learning automata methods: It describes the experiments to test the learning automata-based probabilistic algorithms. The approach was tested to evaluate the system performance index with additive noise and with dynamic tasks generation for the same problem of the distribution of heterogeneous multi-tasks in multi-robot systems. Ant colony optimization: The goal of the experiments presented is to test the ant colony optimization-based deterministic algorithms, to achieve the distribution of heterogeneous multi-tasks in multi-robot systems. In the experiments performed, the system performance index is evaluated by introducing additive noise and dynamic tasks generation over time.

Epitaxial self-alignment: A new route to hybrid active plasmonic nanostructures

Concepts of lateral ordering of epitaxial semiconductor quantum dots (QDs) are for the first time transferred to hybrid nanostructures for active plasmonics. We review our recent research on the self-alignment of epitaxial nanocrystals of In and Ag on ordered one-dimensional In(Ga)As QD arrays and isolated QDs by molecular beam epitaxy. By changing the growth conditions the size and density of the metal nanocrystals are easily controlled and the surface plasmon resonance wavelength is tuned over a wide range in order to match the emission wavelength of the QDs. Photoluminescence measurements reveal large enhancement of the emitted light intensity due to plasmon enhanced emission and absorption down to the single QD level.

Ordered gan/ingan nanorods arrays grown by molecular beam epitaxy for phosphor-free white light emission

The basics of the self-assembled growth of GaN nanorods on Si(111) are reviewed. Morphology differences and optical properties are compared to those of GaN layers grown directly on Si(111). The effects of the growth temperature on the In incorporation in self-assembled InGaN nanorods grown on Si(111) is described. In addition, the inclusion of InGaN quantum disk structures into selfassembled GaN nanorods show clear confinement effects as a function of the quantum disk thickness. In order to overcome the properties dispersion and the intrinsic inhomogeneous nature of the self-assembled growth, the selective area growth of GaN nanorods on both, c-plane and a-plane GaN on sapphire templates, is addressed, with special emphasis on optical quality and morphology differences. The analysis of the optical emission from a single InGaN quantum disk is shown for both polar and non-polar nanorod orientations

Run-Time Scalable Hardware for Reconfigurable Systems

La optimización de parámetros tales como el consumo de potencia, la cantidad de recursos lógicos empleados o la ocupación de memoria ha sido siempre una de las preocupaciones principales a la hora de diseñar sistemas embebidos. Esto es debido a que se trata de sistemas dotados de una cantidad de recursos limitados, y que han sido tradicionalmente empleados para un propósito específico, que permanece invariable a lo largo de toda la vida útil del sistema. Sin embargo, el uso de sistemas embebidos se ha extendido a áreas de aplicación fuera de su ámbito tradicional, caracterizadas por una mayor demanda computacional. Así, por ejemplo, algunos de estos sistemas deben llevar a cabo un intenso procesado de señales multimedia o la transmisión de datos mediante sistemas de comunicaciones de alta capacidad. Por otra parte, las condiciones de operación del sistema pueden variar en tiempo real. Esto sucede, por ejemplo, si su funcionamiento depende de datos medidos por el propio sistema o recibidos a través de la red, de las demandas del usuario en cada momento, o de condiciones internas del propio dispositivo, tales como la duración de la batería. Como consecuencia de la existencia de requisitos de operación dinámicos es necesario ir hacia una gestión dinámica de los recursos del sistema. Si bien el software es inherentemente flexible, no ofrece una potencia computacional tan alta como el hardware. Por lo tanto, el hardware reconfigurable aparece como una solución adecuada para tratar con mayor flexibilidad los requisitos variables dinámicamente en sistemas con alta demanda computacional. La flexibilidad y adaptabilidad del hardware requieren de dispositivos reconfigurables que permitan la modificación de su funcionalidad bajo demanda. En esta tesis se han seleccionado las FPGAs (Field Programmable Gate Arrays) como los dispositivos más apropiados, hoy en día, para implementar sistemas basados en hardware reconfigurable De entre todas las posibilidades existentes para explotar la capacidad de reconfiguración de las FPGAs comerciales, se ha seleccionado la reconfiguración dinámica y parcial. Esta técnica consiste en substituir una parte de la lógica del dispositivo, mientras el resto continúa en funcionamiento. La capacidad de reconfiguración dinámica y parcial de las FPGAs es empleada en esta tesis para tratar con los requisitos de flexibilidad y de capacidad computacional que demandan los dispositivos embebidos. La propuesta principal de esta tesis doctoral es el uso de arquitecturas de procesamiento escalables espacialmente, que son capaces de adaptar su funcionalidad y rendimiento en tiempo real, estableciendo un compromiso entre dichos parámetros y la cantidad de lógica que ocupan en el dispositivo. A esto nos referimos con arquitecturas con huellas escalables. En particular, se propone el uso de arquitecturas altamente paralelas, modulares, regulares y con una alta localidad en sus comunicaciones, para este propósito. El tamaño de dichas arquitecturas puede ser modificado mediante la adición o eliminación de algunos de los módulos que las componen, tanto en una dimensión como en dos. Esta estrategia permite implementar soluciones escalables, sin tener que contar con una versión de las mismas para cada uno de los tamaños posibles de la arquitectura. De esta manera se reduce significativamente el tiempo necesario para modificar su tamaño, así como la cantidad de memoria necesaria para almacenar todos los archivos de configuración. En lugar de proponer arquitecturas para aplicaciones específicas, se ha optado por patrones de procesamiento genéricos, que pueden ser ajustados para solucionar distintos problemas en el estado del arte. A este respecto, se proponen patrones basados en esquemas sistólicos, así como de tipo wavefront. Con el objeto de poder ofrecer una solución integral, se han tratado otros aspectos relacionados con el diseño y el funcionamiento de las arquitecturas, tales como el control del proceso de reconfiguración de la FPGA, la integración de las arquitecturas en el resto del sistema, así como las técnicas necesarias para su implementación. Por lo que respecta a la implementación, se han tratado distintos aspectos de bajo nivel dependientes del dispositivo. Algunas de las propuestas realizadas a este respecto en la presente tesis doctoral son un router que es capaz de garantizar el correcto rutado de los módulos reconfigurables dentro del área destinada para ellos, así como una estrategia para la comunicación entre módulos que no introduce ningún retardo ni necesita emplear recursos configurables del dispositivo. El flujo de diseño propuesto se ha automatizado mediante una herramienta denominada DREAMS. La herramienta se encarga de la modificación de las netlists correspondientes a cada uno de los módulos reconfigurables del sistema, y que han sido generadas previamente mediante herramientas comerciales. Por lo tanto, el flujo propuesto se entiende como una etapa de post-procesamiento, que adapta esas netlists a los requisitos de la reconfiguración dinámica y parcial. Dicha modificación la lleva a cabo la herramienta de una forma completamente automática, por lo que la productividad del proceso de diseño aumenta de forma evidente. Para facilitar dicho proceso, se ha dotado a la herramienta de una interfaz gráfica. El flujo de diseño propuesto, y la herramienta que lo soporta, tienen características específicas para abordar el diseño de las arquitecturas dinámicamente escalables propuestas en esta tesis. Entre ellas está el soporte para el realojamiento de módulos reconfigurables en posiciones del dispositivo distintas a donde el módulo es originalmente implementado, así como la generación de estructuras de comunicación compatibles con la simetría de la arquitectura. El router has sido empleado también en esta tesis para obtener un rutado simétrico entre nets equivalentes. Dicha posibilidad ha sido explotada para aumentar la protección de circuitos con altos requisitos de seguridad, frente a ataques de canal lateral, mediante la implantación de lógica complementaria con rutado idéntico. Para controlar el proceso de reconfiguración de la FPGA, se propone en esta tesis un motor de reconfiguración especialmente adaptado a los requisitos de las arquitecturas dinámicamente escalables. Además de controlar el puerto de reconfiguración, el motor de reconfiguración ha sido dotado de la capacidad de realojar módulos reconfigurables en posiciones arbitrarias del dispositivo, en tiempo real. De esta forma, basta con generar un único bitstream por cada módulo reconfigurable del sistema, independientemente de la posición donde va a ser finalmente reconfigurado. La estrategia seguida para implementar el proceso de realojamiento de módulos es diferente de las propuestas existentes en el estado del arte, pues consiste en la composición de los archivos de configuración en tiempo real. De esta forma se consigue aumentar la velocidad del proceso, mientras que se reduce la longitud de los archivos de configuración parciales a almacenar en el sistema. El motor de reconfiguración soporta módulos reconfigurables con una altura menor que la altura de una región de reloj del dispositivo. Internamente, el motor se encarga de la combinación de los frames que describen el nuevo módulo, con la configuración existente en el dispositivo previamente. El escalado de las arquitecturas de procesamiento propuestas en esta tesis también se puede beneficiar de este mecanismo. Se ha incorporado también un acceso directo a una memoria externa donde se pueden almacenar bitstreams parciales. Para acelerar el proceso de reconfiguración se ha hecho funcionar el ICAP por encima de la máxima frecuencia de reloj aconsejada por el fabricante. Así, en el caso de Virtex-5, aunque la máxima frecuencia del reloj deberían ser 100 MHz, se ha conseguido hacer funcionar el puerto de reconfiguración a frecuencias de operación de hasta 250 MHz, incluyendo el proceso de realojamiento en tiempo real. Se ha previsto la posibilidad de portar el motor de reconfiguración a futuras familias de FPGAs. Por otro lado, el motor de reconfiguración se puede emplear para inyectar fallos en el propio dispositivo hardware, y así ser capaces de evaluar la tolerancia ante los mismos que ofrecen las arquitecturas reconfigurables. Los fallos son emulados mediante la generación de archivos de configuración a los que intencionadamente se les ha introducido un error, de forma que se modifica su funcionalidad. Con el objetivo de comprobar la validez y los beneficios de las arquitecturas propuestas en esta tesis, se han seguido dos líneas principales de aplicación. En primer lugar, se propone su uso como parte de una plataforma adaptativa basada en hardware evolutivo, con capacidad de escalabilidad, adaptabilidad y recuperación ante fallos. En segundo lugar, se ha desarrollado un deblocking filter escalable, adaptado a la codificación de vídeo escalable, como ejemplo de aplicación de las arquitecturas de tipo wavefront propuestas. El hardware evolutivo consiste en el uso de algoritmos evolutivos para diseñar hardware de forma autónoma, explotando la flexibilidad que ofrecen los dispositivos reconfigurables. En este caso, los elementos de procesamiento que componen la arquitectura son seleccionados de una biblioteca de elementos presintetizados, de acuerdo con las decisiones tomadas por el algoritmo evolutivo, en lugar de definir la configuración de las mismas en tiempo de diseño. De esta manera, la configuración del core puede cambiar cuando lo hacen las condiciones del entorno, en tiempo real, por lo que se consigue un control autónomo del proceso de reconfiguración dinámico. Así, el sistema es capaz de optimizar, de forma autónoma, su propia configuración. El hardware evolutivo tiene una capacidad inherente de auto-reparación. Se ha probado que las arquitecturas evolutivas propuestas en esta tesis son tolerantes ante fallos, tanto transitorios, como permanentes y acumulativos. La plataforma evolutiva se ha empleado para implementar filtros de eliminación de ruido. La escalabilidad también ha sido aprovechada en esta aplicación. Las arquitecturas evolutivas escalables permiten la adaptación autónoma de los cores de procesamiento ante fluctuaciones en la cantidad de recursos disponibles en el sistema. Por lo tanto, constituyen un ejemplo de escalabilidad dinámica para conseguir un determinado nivel de calidad, que puede variar en tiempo real. Se han propuesto dos variantes de sistemas escalables evolutivos. El primero consiste en un único core de procesamiento evolutivo, mientras que el segundo está formado por un número variable de arrays de procesamiento. La codificación de vídeo escalable, a diferencia de los codecs no escalables, permite la decodificación de secuencias de vídeo con diferentes niveles de calidad, de resolución temporal o de resolución espacial, descartando la información no deseada. Existen distintos algoritmos que soportan esta característica. En particular, se va a emplear el estándar Scalable Video Coding (SVC), que ha sido propuesto como una extensión de H.264/AVC, ya que este último es ampliamente utilizado tanto en la industria, como a nivel de investigación. Para poder explotar toda la flexibilidad que ofrece el estándar, hay que permitir la adaptación de las características del decodificador en tiempo real. El uso de las arquitecturas dinámicamente escalables es propuesto en esta tesis con este objetivo. El deblocking filter es un algoritmo que tiene como objetivo la mejora de la percepción visual de la imagen reconstruida, mediante el suavizado de los "artefactos" de bloque generados en el lazo del codificador. Se trata de una de las tareas más intensivas en procesamiento de datos de H.264/AVC y de SVC, y además, su carga computacional es altamente dependiente del nivel de escalabilidad seleccionado en el decodificador. Por lo tanto, el deblocking filter ha sido seleccionado como prueba de concepto de la aplicación de las arquitecturas dinámicamente escalables para la compresión de video. La arquitectura propuesta permite añadir o eliminar unidades de computación, siguiendo un esquema de tipo wavefront. La arquitectura ha sido propuesta conjuntamente con un esquema de procesamiento en paralelo del deblocking filter a nivel de macrobloque, de tal forma que cuando se varía del tamaño de la arquitectura, el orden de filtrado de los macrobloques varia de la misma manera. El patrón propuesto se basa en la división del procesamiento de cada macrobloque en dos etapas independientes, que se corresponden con el filtrado horizontal y vertical de los bloques dentro del macrobloque. Las principales contribuciones originales de esta tesis son las siguientes: - El uso de arquitecturas altamente regulares, modulares, paralelas y con una intensa localidad en sus comunicaciones, para implementar cores de procesamiento dinámicamente reconfigurables. - El uso de arquitecturas bidimensionales, en forma de malla, para construir arquitecturas dinámicamente escalables, con una huella escalable. De esta forma, las arquitecturas permiten establecer un compromiso entre el área que ocupan en el dispositivo, y las prestaciones que ofrecen en cada momento. Se proponen plantillas de procesamiento genéricas, de tipo sistólico o wavefront, que pueden ser adaptadas a distintos problemas de procesamiento. - Un flujo de diseño y una herramienta que lo soporta, para el diseño de sistemas reconfigurables dinámicamente, centradas en el diseño de las arquitecturas altamente paralelas, modulares y regulares propuestas en esta tesis. - Un esquema de comunicaciones entre módulos reconfigurables que no introduce ningún retardo ni requiere el uso de recursos lógicos propios. - Un router flexible, capaz de resolver los conflictos de rutado asociados con el diseño de sistemas reconfigurables dinámicamente. - Un algoritmo de optimización para sistemas formados por múltiples cores escalables que optimice, mediante un algoritmo genético, los parámetros de dicho sistema. Se basa en un modelo conocido como el problema de la mochila. - Un motor de reconfiguración adaptado a los requisitos de las arquitecturas altamente regulares y modulares. Combina una alta velocidad de reconfiguración, con la capacidad de realojar módulos en tiempo real, incluyendo el soporte para la reconfiguración de regiones que ocupan menos que una región de reloj, así como la réplica de un módulo reconfigurable en múltiples posiciones del dispositivo. - Un mecanismo de inyección de fallos que, empleando el motor de reconfiguración del sistema, permite evaluar los efectos de fallos permanentes y transitorios en arquitecturas reconfigurables. - La demostración de las posibilidades de las arquitecturas propuestas en esta tesis para la implementación de sistemas de hardware evolutivos, con una alta capacidad de procesamiento de datos. - La implementación de sistemas de hardware evolutivo escalables, que son capaces de tratar con la fluctuación de la cantidad de recursos disponibles en el sistema, de una forma autónoma. - Una estrategia de procesamiento en paralelo para el deblocking filter compatible con los estándares H.264/AVC y SVC que reduce el número de ciclos de macrobloque necesarios para procesar un frame de video. - Una arquitectura dinámicamente escalable que permite la implementación de un nuevo deblocking filter, totalmente compatible con los estándares H.264/AVC y SVC, que explota el paralelismo a nivel de macrobloque. El presente documento se organiza en siete capítulos. En el primero se ofrece una introducción al marco tecnológico de esta tesis, especialmente centrado en la reconfiguración dinámica y parcial de FPGAs. También se motiva la necesidad de las arquitecturas dinámicamente escalables propuestas en esta tesis. En el capítulo 2 se describen las arquitecturas dinámicamente escalables. Dicha descripción incluye la mayor parte de las aportaciones a nivel arquitectural realizadas en esta tesis. Por su parte, el flujo de diseño adaptado a dichas arquitecturas se propone en el capítulo 3. El motor de reconfiguración se propone en el 4, mientras que el uso de dichas arquitecturas para implementar sistemas de hardware evolutivo se aborda en el 5. El deblocking filter escalable se describe en el 6, mientras que las conclusiones finales de esta tesis, así como la descripción del trabajo futuro, son abordadas en el capítulo 7. ABSTRACT The optimization of system parameters, such as power dissipation, the amount of hardware resources and the memory footprint, has been always a main concern when dealing with the design of resource-constrained embedded systems. This situation is even more demanding nowadays. Embedded systems cannot anymore be considered only as specific-purpose computers, designed for a particular functionality that remains unchanged during their lifetime. Differently, embedded systems are now required to deal with more demanding and complex functions, such as multimedia data processing and high-throughput connectivity. In addition, system operation may depend on external data, the user requirements or internal variables of the system, such as the battery life-time. All these conditions may vary at run-time, leading to adaptive scenarios. As a consequence of both the growing computational complexity and the existence of dynamic requirements, dynamic resource management techniques for embedded systems are needed. Software is inherently flexible, but it cannot meet the computing power offered by hardware solutions. Therefore, reconfigurable hardware emerges as a suitable technology to deal with the run-time variable requirements of complex embedded systems. Adaptive hardware requires the use of reconfigurable devices, where its functionality can be modified on demand. In this thesis, Field Programmable Gate Arrays (FPGAs) have been selected as the most appropriate commercial technology existing nowadays to implement adaptive hardware systems. There are different ways of exploiting reconfigurability in reconfigurable devices. Among them is dynamic and partial reconfiguration. This is a technique which consists in substituting part of the FPGA logic on demand, while the rest of the device continues working. The strategy followed in this thesis is to exploit the dynamic and partial reconfiguration of commercial FPGAs to deal with the flexibility and complexity demands of state-of-the-art embedded systems. The proposal of this thesis to deal with run-time variable system conditions is the use of spatially scalable processing hardware IP cores, which are able to adapt their functionality or performance at run-time, trading them off with the amount of logic resources they occupy in the device. This is referred to as a scalable footprint in the context of this thesis. The distinguishing characteristic of the proposed cores is that they rely on highly parallel, modular and regular architectures, arranged in one or two dimensions. These architectures can be scaled by means of the addition or removal of the composing blocks. This strategy avoids implementing a full version of the core for each possible size, with the corresponding benefits in terms of scaling and adaptation time, as well as bitstream storage memory requirements. Instead of providing specific-purpose architectures, generic architectural templates, which can be tuned to solve different problems, are proposed in this thesis. Architectures following both systolic and wavefront templates have been selected. Together with the proposed scalable architectural templates, other issues needed to ensure the proper design and operation of the scalable cores, such as the device reconfiguration control, the run-time management of the architecture and the implementation techniques have been also addressed in this thesis. With regard to the implementation of dynamically reconfigurable architectures, device dependent low-level details are addressed. Some of the aspects covered in this thesis are the area constrained routing for reconfigurable modules, or an inter-module communication strategy which does not introduce either extra delay or logic overhead. The system implementation, from the hardware description to the device configuration bitstream, has been fully automated by modifying the netlists corresponding to each of the system modules, which are previously generated using the vendor tools. This modification is therefore envisaged as a post-processing step. Based on these implementation proposals, a design tool called DREAMS (Dynamically Reconfigurable Embedded and Modular Systems) has been created, including a graphic user interface. The tool has specific features to cope with modular and regular architectures, including the support for module relocation and the inter-module communications scheme based on the symmetry of the architecture. The core of the tool is a custom router, which has been also exploited in this thesis to obtain symmetric routed nets, with the aim of enhancing the protection of critical reconfigurable circuits against side channel attacks. This is achieved by duplicating the logic with an exactly equal routing. In order to control the reconfiguration process of the FPGA, a Reconfiguration Engine suited to the specific requirements set by the proposed architectures was also proposed. Therefore, in addition to controlling the reconfiguration port, the Reconfiguration Engine has been enhanced with the online relocation ability, which allows employing a unique configuration bitstream for all the positions where the module may be placed in the device. Differently to the existing relocating solutions, which are based on bitstream parsers, the proposed approach is based on the online composition of bitstreams. This strategy allows increasing the speed of the process, while the length of partial bitstreams is also reduced. The height of the reconfigurable modules can be lower than the height of a clock region. The Reconfiguration Engine manages the merging process of the new and the existing configuration frames within each clock region. The process of scaling up and down the hardware cores also benefits from this technique. A direct link to an external memory where partial bitstreams can be stored has been also implemented. In order to accelerate the reconfiguration process, the ICAP has been overclocked over the speed reported by the manufacturer. In the case of Virtex-5, even though the maximum frequency of the ICAP is reported to be 100 MHz, valid operations at 250 MHz have been achieved, including the online relocation process. Portability of the reconfiguration solution to today's and probably, future FPGAs, has been also considered. The reconfiguration engine can be also used to inject faults in real hardware devices, and this way being able to evaluate the fault tolerance offered by the reconfigurable architectures. Faults are emulated by introducing partial bitstreams intentionally modified to provide erroneous functionality. To prove the validity and the benefits offered by the proposed architectures, two demonstration application lines have been envisaged. First, scalable architectures have been employed to develop an evolvable hardware platform with adaptability, fault tolerance and scalability properties. Second, they have been used to implement a scalable deblocking filter suited to scalable video coding. Evolvable Hardware is the use of evolutionary algorithms to design hardware in an autonomous way, exploiting the flexibility offered by reconfigurable devices. In this case, processing elements composing the architecture are selected from a presynthesized library of processing elements, according to the decisions taken by the algorithm, instead of being decided at design time. This way, the configuration of the array may change as run-time environmental conditions do, achieving autonomous control of the dynamic reconfiguration process. Thus, the self-optimization property is added to the native self-configurability of the dynamically scalable architectures. In addition, evolvable hardware adaptability inherently offers self-healing features. The proposal has proved to be self-tolerant, since it is able to self-recover from both transient and cumulative permanent faults. The proposed evolvable architecture has been used to implement noise removal image filters. Scalability has been also exploited in this application. Scalable evolvable hardware architectures allow the autonomous adaptation of the processing cores to a fluctuating amount of resources available in the system. Thus, it constitutes an example of the dynamic quality scalability tackled in this thesis. Two variants have been proposed. The first one consists in a single dynamically scalable evolvable core, and the second one contains a variable number of processing cores. Scalable video is a flexible approach for video compression, which offers scalability at different levels. Differently to non-scalable codecs, a scalable video bitstream can be decoded with different levels of quality, spatial or temporal resolutions, by discarding the undesired information. The interest in this technology has been fostered by the development of the Scalable Video Coding (SVC) standard, as an extension of H.264/AVC. In order to exploit all the flexibility offered by the standard, it is necessary to adapt the characteristics of the decoder to the requirements of each client during run-time. The use of dynamically scalable architectures is proposed in this thesis with this aim. The deblocking filter algorithm is the responsible of improving the visual perception of a reconstructed image, by smoothing blocking artifacts generated in the encoding loop. This is one of the most computationally intensive tasks of the standard, and furthermore, it is highly dependent on the selected scalability level in the decoder. Therefore, the deblocking filter has been selected as a proof of concept of the implementation of dynamically scalable architectures for video compression. The proposed architecture allows the run-time addition or removal of computational units working in parallel to change its level of parallelism, following a wavefront computational pattern. Scalable architecture is offered together with a scalable parallelization strategy at the macroblock level, such that when the size of the architecture changes, the macroblock filtering order is modified accordingly. The proposed pattern is based on the division of the macroblock processing into two independent stages, corresponding to the horizontal and vertical filtering of the blocks within the macroblock. The main contributions of this thesis are: - The use of highly parallel, modular, regular and local architectures to implement dynamically reconfigurable processing IP cores, for data intensive applications with flexibility requirements. - The use of two-dimensional mesh-type arrays as architectural templates to build dynamically reconfigurable IP cores, with a scalable footprint. The proposal consists in generic architectural templates, which can be tuned to solve different computational problems. •A design flow and a tool targeting the design of DPR systems, focused on highly parallel, modular and local architectures. - An inter-module communication strategy, which does not introduce delay or area overhead, named Virtual Borders. - A custom and flexible router to solve the routing conflicts as well as the inter-module communication problems, appearing during the design of DPR systems. - An algorithm addressing the optimization of systems composed of multiple scalable cores, which size can be decided individually, to optimize the system parameters. It is based on a model known as the multi-dimensional multi-choice Knapsack problem. - A reconfiguration engine tailored to the requirements of highly regular and modular architectures. It combines a high reconfiguration throughput with run-time module relocation capabilities, including the support for sub-clock reconfigurable regions and the replication in multiple positions. - A fault injection mechanism which takes advantage of the system reconfiguration engine, as well as the modularity of the proposed reconfigurable architectures, to evaluate the effects of transient and permanent faults in these architectures. - The demonstration of the possibilities of the architectures proposed in this thesis to implement evolvable hardware systems, while keeping a high processing throughput. - The implementation of scalable evolvable hardware systems, which are able to adapt to the fluctuation of the amount of resources available in the system, in an autonomous way. - A parallelization strategy for the H.264/AVC and SVC deblocking filter, which reduces the number of macroblock cycles needed to process the whole frame. - A dynamically scalable architecture that permits the implementation of a novel deblocking filter module, fully compliant with the H.264/AVC and SVC standards, which exploits the macroblock level parallelism of the algorithm. This document is organized in seven chapters. In the first one, an introduction to the technology framework of this thesis, specially focused on dynamic and partial reconfiguration, is provided. The need for the dynamically scalable processing architectures proposed in this work is also motivated in this chapter. In chapter 2, dynamically scalable architectures are described. Description includes most of the architectural contributions of this work. The design flow tailored to the scalable architectures, together with the DREAMs tool provided to implement them, are described in chapter 3. The reconfiguration engine is described in chapter 4. The use of the proposed scalable archtieectures to implement evolvable hardware systems is described in chapter 5, while the scalable deblocking filter is described in chapter 6. Final conclusions of this thesis, and the description of future work, are addressed in chapter 7.

A novel FPGA-based evolvable hardware system based on multiple processing arrays

In this paper, an architecture based on a scalable and flexible set of Evolvable Processing arrays is presented. FPGA-native Dynamic Partial Reconfiguration (DPR) is used for evolution, which is done intrinsically, letting the system to adapt autonomously to variable run-time conditions, including the presence of transient and permanent faults. The architecture supports different modes of operation, namely: independent, parallel, cascaded or bypass mode. These modes of operation can be used during evolution time or during normal operation. The evolvability of the architecture is combined with fault-tolerance techniques, to enhance the platform with self-healing features, making it suitable for applications which require both high adaptability and reliability. Experimental results show that such a system may benefit from accelerated evolution times, increased performance and improved dependability, mainly by increasing fault tolerance for transient and permanent faults, as well as providing some fault identification possibilities. The evolvable HW array shown is tailored for window-based image processing applications.