Solder doped polycaprolactone scaffold enables reproducible laser tissue soldering

BACKGROUND AND OBJECTIVES: In this in vitro feasibility study we analyzed tissue fusion using bovine serum albumin (BSA) and Indocyanine green (ICG) doped polycaprolactone (PCL) scaffolds in combination with a diode laser as energy source while focusing on the influence of irradiation power and albumin concentration on the resulting tensile strength and induced tissue damage. MATERIALS AND METHODS: A porous PCL scaffold doped with either 25% or 40% (w/w) of BSA in combination with 0.1% (w/w) ICG was used to fuse rabbit aortas. Soldering energy was delivered through the vessel from the endoluminal side using a continuous wave diode laser at 808 nm via a 400 microm core fiber. Scaffold surface temperatures were analyzed with an infrared camera. Optimum parameters such as irradiation time, radiation power and temperature were determined in view of maximum tensile strength but simultaneously minimum thermally induced tissue damage. Differential scanning calorimetry (DSC) was performed to measure the influence of PCL on the denaturation temperature of BSA. RESULTS: Optimum parameter settings were found to be 60 seconds irradiation time and 1.5 W irradiation power resulting in tensile strengths of around 2,000 mN. Corresponding scaffold surface temperature was 117.4+/- 12 degrees C. Comparison of the two BSA concentration revealed that 40% BSA scaffold resulted in significant higher tensile strength compared to the 25%. At optimum parameter settings, thermal damage was restricted to the adventitia and its interface with the outermost layer of the tunica media. The DSC showed two endothermic peaks in BSA containing samples, both strongly depending on the water content and the presence of PCL and/or ICG. CONCLUSIONS: Diode laser soldering of vascular tissue using BSA-ICG-PCL-scaffolds leads to strong and reproducible tissue bonds, with vessel damage limited to the adventitia. Higher BSA content results in higher tensile strengths. The DSC-measurements showed that BSA denaturation temperature is lowered by addition of water and/or ICG-PCL.

Optimal game theoretic distributed control methodologies in small scale power systems

This dissertation presents the competitive control methodologies for small-scale power system (SSPS). A SSPS is a collection of sources and loads that shares a common network which can be isolated during terrestrial disturbances. Micro-grids, naval ship electric power systems (NSEPS), aircraft power systems and telecommunication system power systems are typical examples of SSPS. The analysis and development of control systems for small-scale power systems (SSPS) lacks a defined slack bus. In addition, a change of a load or source will influence the real time system parameters of the system. Therefore, the control system should provide the required flexibility, to ensure operation as a single aggregated system. In most of the cases of a SSPS the sources and loads must be equipped with power electronic interfaces which can be modeled as a dynamic controllable quantity. The mathematical formulation of the micro-grid is carried out with the help of game theory, optimal control and fundamental theory of electrical power systems. Then the micro-grid can be viewed as a dynamical multi-objective optimization problem with nonlinear objectives and variables. Basically detailed analysis was done with optimal solutions with regards to start up transient modeling, bus selection modeling and level of communication within the micro-grids. In each approach a detail mathematical model is formed to observe the system response. The differential game theoretic approach was also used for modeling and optimization of startup transients. The startup transient controller was implemented with open loop, PI and feedback control methodologies. Then the hardware implementation was carried out to validate the theoretical results. The proposed game theoretic controller shows higher performances over traditional the PI controller during startup. In addition, the optimal transient surface is necessary while implementing the feedback controller for startup transient. Further, the experimental results are in agreement with the theoretical simulation. The bus selection and team communication was modeled with discrete and continuous game theory models. Although players have multiple choices, this controller is capable of choosing the optimum bus. Next the team communication structures are able to optimize the players’ Nash equilibrium point. All mathematical models are based on the local information of the load or source. As a result, these models are the keys to developing accurate distributed controllers.

Space-qualified laser system for the BepiColombo Laser Altimeter

The space-qualified design of a miniaturized laser for pulsed operation at a wavelength of 1064 nm and at repetition rates up to 10 Hz is presented. This laser consists of a pair of diode-laser pumped, actively q-switched Nd:YAG rod oscillators hermetically sealed and encapsulated in an environment of dry synthetic air. The system delivers at least 300 million laser pulses with 50 mJ energy and 5 ns pulse width (FWHM). It will be launched in 2017 aboard European Space Agency’s Mercury Planetary Orbiter as part of the BepiColombo Laser Altimeter, which, after a 6-years cruise, will start recording topographic data from orbital altitudes between 400 and 1500 km above Mercury’s surface.

Periodontal and peri-implant wound healing following laser therapy

Laser irradiation has numerous favorable characteristics, such as ablation or vaporization, hemostasis, biostimulation (photobiomodulation) and microbial inhibition and destruction, which induce various beneficial therapeutic effects and biological responses. Therefore, the use of lasers is considered effective and suitable for treating a variety of inflammatory and infectious oral conditions. The CO2 , neodymium-doped yttrium-aluminium-garnet (Nd:YAG) and diode lasers have mainly been used for periodontal soft-tissue management. With development of the erbium-doped yttrium-aluminium-garnet (Er:YAG) and erbium, chromium-doped yttrium-scandium-gallium-garnet (Er,Cr:YSGG) lasers, which can be applied not only on soft tissues but also on dental hard tissues, the application of lasers dramatically expanded from periodontal soft-tissue management to hard-tissue treatment. Currently, various periodontal tissues (such as gingiva, tooth roots and bone tissue), as well as titanium implant surfaces, can be treated with lasers, and a variety of dental laser systems are being employed for the management of periodontal and peri-implant diseases. In periodontics, mechanical therapy has conventionally been the mainstream of treatment; however, complete bacterial eradication and/or optimal wound healing may not be necessarily achieved with conventional mechanical therapy alone. Consequently, in addition to chemotherapy consisting of antibiotics and anti-inflammatory agents, phototherapy using lasers and light-emitting diodes has been gradually integrated with mechanical therapy to enhance subsequent wound healing by achieving thorough debridement, decontamination and tissue stimulation. With increasing evidence of benefits, therapies with low- and high-level lasers play an important role in wound healing/tissue regeneration in the treatment of periodontal and peri-implant diseases. This article discusses the outcomes of laser therapy in soft-tissue management, periodontal nonsurgical and surgical treatment, osseous surgery and peri-implant treatment, focusing on postoperative wound healing of periodontal and peri-implant tissues, based on scientific evidence from currently available basic and clinical studies, as well as on case reports.

Entwicklung eines deutschsprachigen Fragebogens zur Durchführung von Multisource-Feedback in der ärztlichen Weiterbildung

Fragestellung/Einleitung: Multisource-Feedback (MSF) ist ein anerkanntes Instrument zur Überprüfung und Verbesserung der ärztlichen Tätigkeit [1]. Es beinhaltet Feedback, das von MitarbeiterInnen verschiedener Tätigkeitsbereiche und verschiedener Hierarchiestufen gegeben wird. Das Feedback wird anonym mithilfe eines Fragebogens gegeben, der verschiedene Kriterien der ärztlichen Kompetenz beschreibt. Das Feedback wird anschlieβend für die zu beurteilenden ÄrztInnen in einem Gespräch von einer/m SupervisorIn zusammengefasst. Bislang existiert kein deutschsprachiger Fragebogen für Multisource-Feedback für die ärztliche Tätigkeit. Unsere Zielsetzung war es daher, einen deutschsprachigen Fragebogen zu erstellen und diesen bzgl. relevanter Validitätskriterien zu untersuchen. Methoden: Zur Erstellung des Fragebogens sammelten wir die beste verfügbare Evidenz der entsprechenden Literatur. Wir wählten einen validierten englischen Fragebogen, der bereits in der Weiterbildung in Groβbritannien angewendet wird [2] und den wichtigsten Kriterien entspricht. Dieser wurde übersetzt und in einigen Bereichen erweitert, um ihn sprachlichen Gegebenheiten und lokalen Bedürfnissen anzupassen. Bezüglich der Validität wurden zwei Kriterien untersucht: Inhaltsvalidität (content validity evidence) und Antwortprozesse (response process validity evidence). Um die Inhaltsvalidität zu untersuchen, wurde in einer Expertenrunde diskutiert, ob der übersetzte Fragebogen die erwarteten Kompetenzen widerspiegelt. Im Anschluss wurden die Antwortprozesse mithilfe eines sog. „think-alouds“ mit ÄrztInnen in Weiterbildung und ihren AusbilderInnen untersucht. Ergebnisse: Der resultierende Fragebogen umfasst 20 Fragen. Davon sind 15 Items den Bereichen „Klinische Fähigkeiten“, „Umgang mit Patienten“, „Umgang mit Kollegen“ und „Arbeitsweise“ zuzuordnen. Diese Fragen werden auf einer fünfstufigen Likert-Skala beantwortet. Zusätzlich bietet jede Frage die Möglichkeit, einen Freitext zu besonderen Stärken und Schwächen der KandidatInnen aufzuführen. Weiterhin gibt es fünf globale Fragen zu Stärken und Verbesserungsmöglichkeiten, äuβeren Einflüssen, den Arbeitsbedingungen und nach Zweifeln an der Gesundheit oder Integrität des Arztes/ der Ärztin. In der Expertenrunde wurde der Fragebogen als für den deutschsprachigen Raum ohne Einschränkungen anwendbar eingeschätzt. Die Analyse der Antwortprozesse führte zu kleineren sprachlichen Anpassungen und bestätigt, dass der Fragebogen verständlich und eindeutig zu beantworten ist und das gewählte Konstrukt der ärztlichen Tätigkeit vollständig umschreibt. Diskussion/Schlussfolgerung: Wir entwickelten einen deutschsprachigen Fragebogen zur Durchführung von Multisource-Feedback in der ärztlichen Weiterbildung. Wir fanden Hinweise für die Validität dieses Fragebogens bzgl. des Inhalts und der Antwortprozesse. Zusätzliche Untersuchungen zur Validität wie z.B. die durch den Fragebogen entstehenden Auswirkungen (consequences) sind vorgesehen. Dieser Fragebogen könnte zum breiteren Einsatz von MSF in der ärztlichen Weiterbildung auch im deutschsprachigen Raum beitragen. This is an Open Access article distributed under the terms of the Creative Commons Attribution License. You are free: to Share - to copy, distribute and transmit the work, provided the original author and source are credited. See license information at http://creativecommons.org/licenses/by-nc-nd/3.0/.

The Comprehensive Assessment of Leadership for Learning: A Next Generation Formative Evaluation and Feedback System

Recent developments in federal policy have prompted the creation of state evaluation frameworks for principals and teachers that hold educators accountable for effective practices and student outcomes. These changes have created a demand for formative evaluation instruments that reflect current accountability pressures and can be used by schools to focus school improvement and leadership development efforts. The Comprehensive Assessment of Leadership for Learning (CALL) is a next generation, 360-degree on-line assessment and feedback system that reflect best practices in feedback design. Some unique characteristics of CALL include a focus on: leadership distributed throughout the school rather than as carried out by an individual leader; assessment of leadership tasks rather than perceptions of leadership practice; a focus on larger complex systems of middle and high school; and transparency of assessment design. This paper describes research contributing to the design and validation of the CALL survey instrument.

Assessing Distributed Leadership and the Successful Implementation of Evidence-Based Practices

Kelly and Halverson are to be congratulated on their contribution to the field of education. Their efforts in designing The Comprehensive Assessment of Leadership forLearning (CALL) represents a step forward inm the fomative assessment of distributed leadership in schools and their work is noteworthy in its rapid linking of survey assessment data to specific feedback and recommendations for users. Issues relevant to evidence-based practices, implementation, and professional common language are addressed in this commentary.

New laser-based approaches to improve the passivation and rear contact quality in high effiency crystalline silicon solar cells

Laser processing has been the tool of choice last years to develop improved concepts in contact formation for high efficiency crystalline silicon (c-Si) solar cells. New concepts based on standard laser fired contacts (LFC) or advanced laser doping (LD) techniques are optimal solutions for both the front and back contacts of a number of structures with growing interest in the c-Si PV industry. Nowadays, substantial efforts are underway to optimize these processes in order to be applied industrially in high efficiency concepts. However a critical issue in these devices is that, most of them, demand a very low thermal input during the fabrication sequence and a minimal damage of the structure during the laser irradiation process. Keeping these two objectives in mind, in this work we discuss the possibility of using laser-based processes to contact the rear side of silicon heterojunction (SHJ) solar cells in an approach fully compatible with the low temperature processing associated to these devices. First we discuss the possibility of using standard LFC techniques in the fabrication of SHJ cells on p-type substrates, studying in detail the effect of the laser wavelength on the contact quality. Secondly, we present an alternative strategy bearing in mind that a real challenge in the rear contact formation is to reduce the damage induced by the laser irradiation. This new approach is based on local laser doping techniques previously developed by our groups, to contact the rear side of p-type c-Si solar cells by means of laser processing before rear metallization of dielectric stacks containing Al2O3. In this work we demonstrate the possibility of using this new approach in SHJ cells with a distinct advantage over other standard LFC techniques.

Bit noise from an optical logic gate with laser diodes

Output bits from an optical logic cell present noise due to the type of technique used to obtain the Boolean functions of two input data bits. We have simulated the behavior of an optically programmable logic cell working with Fabry Perot-laser diodes of the same type employed in optical communications (1550nm) but working here as amplifiers. We will report in this paper a study of the bit noise generated from the optical non-linearity process allowing the Boolean function operation of two optical input data signals. Two types of optical logic cells will be analyzed. Firstly, a classical "on-off" behavior, with transmission operation of LD amplifier and, secondly, a more complicated configuration with two LD amplifiers, one working on transmission and the other one in reflection mode. This last configuration has nonlinear behavior emulating SEED-like properties. In both cases, depending on the value of a "1" input data signals to be processed, a different logic function can be obtained. Also a CW signal, known as control signal, may be apply to fix the type of logic function. The signal to noise ratio will be analyzed for different parameters, as wavelength signals and the hysteresis cycles regions associated to the device, in relation with the signals power level applied. With this study we will try to obtain a better understanding of the possible effects present on an optical logic gate with Laser Diodes.

Laser pulse shaping with liquid crystals (1982)

In this paper we report a new method of laser pulse shaping by the use of liquid crystals as non linear materials. The basis of this method is similar to the one reported by us for an hybrid optical bistable device, but with a different electronic circuitry and feedback.

Dynamic gamma frequency feedback coupling between higher and lower order visual cortices underlies perceptual completion in humans

To perceive a coherent environment, incomplete or overlapping visual forms must be integrated into meaningful coherent percepts, a process referred to as ?Gestalt? formation or perceptual completion. Increasing evidence suggests that this process engages oscillatory neuronal activity in a distributed neuronal assembly. A separate line of evidence suggests that Gestalt formation requires top-down feedback from higher order brain regions to early visual cortex. Here we combine magnetoencephalography (MEG) and effective connectivity analysis in the frequency domain to specifically address the effective coupling between sources of oscillatory brain activity during Gestalt formation. We demonstrate that perceptual completion of two-tone ?Mooney? faces induces increased gamma frequency band power (55?71 Hz) in human early visual, fusiform and parietal cortices. Within this distributed neuronal assembly fusiform and parietal gamma oscillators are coupled by forward and backward connectivity during Mooney face perception, indicating reciprocal influences of gamma activity between these higher order visual brain regions. Critically, gamma band oscillations in early visual cortex are modulated by top-down feedback connectivity from both fusiform and parietal cortices. Thus, we provide a mechanistic account of Gestalt perception in which gamma oscillations in feature sensitive and spatial attention-relevant brain regions reciprocally drive one another and convey global stimulus aspects to local processing units at low levels of the sensory hierarchy by top-down feedback. Our data therefore support the notion of inverse hierarchical processing within the visual system underlying awareness of coherent percepts.

High-Power High-Efficiency Laser Power Transmission at 100m Using Optimized Multi-Cell GaAs Converter

A high-power high-efficiency laser power transmission system at 100m based on an optimized multi-cell GaAs converter capable of supplying 9.7W of electricity is demonstrated. An I-V testing system integrated with a data acquisition circuit and an analysis software is designed to measure the efficiency and the I-V characteristics of the laser power converter (LPC). The dependencies of the converter’s efficiency with respect to wavelength, laser intensity and temperature are analyzed. A diode laser with 793nm of wavelength and 24W of power is used to test the LPC and the software. The maximum efficiency of the LPC is 48.4% at an input laser power of 8W at room temperature. When the input laser power is 24W (laser intensity of 60000W/m2), the efficiency is 40.4% and the output voltage is 4 V. The overall efficiency from electricity to electricity is 11.6%.

Experimental implementation of a biometric laser synaptic sensor

We fabricate a biometric laser fiber synaptic sensor to transmit information from one neuron cell to the other by an optical way. The optical synapse is constructed on the base of an erbium-doped fiber laser, whose pumped diode current is driven by a pre-synaptic FitzHugh–Nagumo electronic neuron, and the laser output controls a post-synaptic FitzHugh–Nagumo electronic neuron. The implemented laser synapse displays very rich dynamics, including fixed points, periodic orbits with different frequency-locking ratios and chaos. These regimes can be beneficial for efficient biorobotics, where behavioral flexibility subserved by synaptic connectivity is a challenge.

Run-Time Dynamically-Adaptable FPGA-Based Architecture for High-Performance Autonomous Distributed Systems

Esta tesis doctoral se enmarca dentro del campo de los sistemas embebidos reconfigurables, redes de sensores inalámbricas para aplicaciones de altas prestaciones, y computación distribuida. El documento se centra en el estudio de alternativas de procesamiento para sistemas embebidos autónomos distribuidos de altas prestaciones (por sus siglas en inglés, High-Performance Autonomous Distributed Systems (HPADS)), así como su evolución hacia el procesamiento de alta resolución. El estudio se ha llevado a cabo tanto a nivel de plataforma como a nivel de las arquitecturas de procesamiento dentro de la plataforma con el objetivo de optimizar aspectos tan relevantes como la eficiencia energética, la capacidad de cómputo y la tolerancia a fallos del sistema. Los HPADS son sistemas realimentados, normalmente formados por elementos distribuidos conectados o no en red, con cierta capacidad de adaptación, y con inteligencia suficiente para llevar a cabo labores de prognosis y/o autoevaluación. Esta clase de sistemas suele formar parte de sistemas más complejos llamados sistemas ciber-físicos (por sus siglas en inglés, Cyber-Physical Systems (CPSs)). Los CPSs cubren un espectro enorme de aplicaciones, yendo desde aplicaciones médicas, fabricación, o aplicaciones aeroespaciales, entre otras muchas. Para el diseño de este tipo de sistemas, aspectos tales como la confiabilidad, la definición de modelos de computación, o el uso de metodologías y/o herramientas que faciliten el incremento de la escalabilidad y de la gestión de la complejidad, son fundamentales. La primera parte de esta tesis doctoral se centra en el estudio de aquellas plataformas existentes en el estado del arte que por sus características pueden ser aplicables en el campo de los CPSs, así como en la propuesta de un nuevo diseño de plataforma de altas prestaciones que se ajuste mejor a los nuevos y más exigentes requisitos de las nuevas aplicaciones. Esta primera parte incluye descripción, implementación y validación de la plataforma propuesta, así como conclusiones sobre su usabilidad y sus limitaciones. Los principales objetivos para el diseño de la plataforma propuesta se enumeran a continuación: • Estudiar la viabilidad del uso de una FPGA basada en RAM como principal procesador de la plataforma en cuanto a consumo energético y capacidad de cómputo. • Propuesta de técnicas de gestión del consumo de energía en cada etapa del perfil de trabajo de la plataforma. •Propuestas para la inclusión de reconfiguración dinámica y parcial de la FPGA (por sus siglas en inglés, Dynamic Partial Reconfiguration (DPR)) de forma que sea posible cambiar ciertas partes del sistema en tiempo de ejecución y sin necesidad de interrumpir al resto de las partes. Evaluar su aplicabilidad en el caso de HPADS. Las nuevas aplicaciones y nuevos escenarios a los que se enfrentan los CPSs, imponen nuevos requisitos en cuanto al ancho de banda necesario para el procesamiento de los datos, así como en la adquisición y comunicación de los mismos, además de un claro incremento en la complejidad de los algoritmos empleados. Para poder cumplir con estos nuevos requisitos, las plataformas están migrando desde sistemas tradicionales uni-procesador de 8 bits, a sistemas híbridos hardware-software que incluyen varios procesadores, o varios procesadores y lógica programable. Entre estas nuevas arquitecturas, las FPGAs y los sistemas en chip (por sus siglas en inglés, System on Chip (SoC)) que incluyen procesadores embebidos y lógica programable, proporcionan soluciones con muy buenos resultados en cuanto a consumo energético, precio, capacidad de cómputo y flexibilidad. Estos buenos resultados son aún mejores cuando las aplicaciones tienen altos requisitos de cómputo y cuando las condiciones de trabajo son muy susceptibles de cambiar en tiempo real. La plataforma propuesta en esta tesis doctoral se ha denominado HiReCookie. La arquitectura incluye una FPGA basada en RAM como único procesador, así como un diseño compatible con la plataforma para redes de sensores inalámbricas desarrollada en el Centro de Electrónica Industrial de la Universidad Politécnica de Madrid (CEI-UPM) conocida como Cookies. Esta FPGA, modelo Spartan-6 LX150, era, en el momento de inicio de este trabajo, la mejor opción en cuanto a consumo y cantidad de recursos integrados, cuando además, permite el uso de reconfiguración dinámica y parcial. Es importante resaltar que aunque los valores de consumo son los mínimos para esta familia de componentes, la potencia instantánea consumida sigue siendo muy alta para aquellos sistemas que han de trabajar distribuidos, de forma autónoma, y en la mayoría de los casos alimentados por baterías. Por esta razón, es necesario incluir en el diseño estrategias de ahorro energético para incrementar la usabilidad y el tiempo de vida de la plataforma. La primera estrategia implementada consiste en dividir la plataforma en distintas islas de alimentación de forma que sólo aquellos elementos que sean estrictamente necesarios permanecerán alimentados, cuando el resto puede estar completamente apagado. De esta forma es posible combinar distintos modos de operación y así optimizar enormemente el consumo de energía. El hecho de apagar la FPGA para ahora energía durante los periodos de inactividad, supone la pérdida de la configuración, puesto que la memoria de configuración es una memoria volátil. Para reducir el impacto en el consumo y en el tiempo que supone la reconfiguración total de la plataforma una vez encendida, en este trabajo, se incluye una técnica para la compresión del archivo de configuración de la FPGA, de forma que se consiga una reducción del tiempo de configuración y por ende de la energía consumida. Aunque varios de los requisitos de diseño pueden satisfacerse con el diseño de la plataforma HiReCookie, es necesario seguir optimizando diversos parámetros tales como el consumo energético, la tolerancia a fallos y la capacidad de procesamiento. Esto sólo es posible explotando todas las posibilidades ofrecidas por la arquitectura de procesamiento en la FPGA. Por lo tanto, la segunda parte de esta tesis doctoral está centrada en el diseño de una arquitectura reconfigurable denominada ARTICo3 (Arquitectura Reconfigurable para el Tratamiento Inteligente de Cómputo, Confiabilidad y Consumo de energía) para la mejora de estos parámetros por medio de un uso dinámico de recursos. ARTICo3 es una arquitectura de procesamiento para FPGAs basadas en RAM, con comunicación tipo bus, preparada para dar soporte para la gestión dinámica de los recursos internos de la FPGA en tiempo de ejecución gracias a la inclusión de reconfiguración dinámica y parcial. Gracias a esta capacidad de reconfiguración parcial, es posible adaptar los niveles de capacidad de procesamiento, energía consumida o tolerancia a fallos para responder a las demandas de la aplicación, entorno, o métricas internas del dispositivo mediante la adaptación del número de recursos asignados para cada tarea. Durante esta segunda parte de la tesis se detallan el diseño de la arquitectura, su implementación en la plataforma HiReCookie, así como en otra familia de FPGAs, y su validación por medio de diferentes pruebas y demostraciones. Los principales objetivos que se plantean la arquitectura son los siguientes: • Proponer una metodología basada en un enfoque multi-hilo, como las propuestas por CUDA (por sus siglas en inglés, Compute Unified Device Architecture) u Open CL, en la cual distintos kernels, o unidades de ejecución, se ejecuten en un numero variable de aceleradores hardware sin necesidad de cambios en el código de aplicación. • Proponer un diseño y proporcionar una arquitectura en la que las condiciones de trabajo cambien de forma dinámica dependiendo bien de parámetros externos o bien de parámetros que indiquen el estado de la plataforma. Estos cambios en el punto de trabajo de la arquitectura serán posibles gracias a la reconfiguración dinámica y parcial de aceleradores hardware en tiempo real. • Explotar las posibilidades de procesamiento concurrente, incluso en una arquitectura basada en bus, por medio de la optimización de las transacciones en ráfaga de datos hacia los aceleradores. •Aprovechar las ventajas ofrecidas por la aceleración lograda por módulos puramente hardware para conseguir una mejor eficiencia energética. • Ser capaces de cambiar los niveles de redundancia de hardware de forma dinámica según las necesidades del sistema en tiempo real y sin cambios para el código de aplicación. • Proponer una capa de abstracción entre el código de aplicación y el uso dinámico de los recursos de la FPGA. El diseño en FPGAs permite la utilización de módulos hardware específicamente creados para una aplicación concreta. De esta forma es posible obtener rendimientos mucho mayores que en el caso de las arquitecturas de propósito general. Además, algunas FPGAs permiten la reconfiguración dinámica y parcial de ciertas partes de su lógica en tiempo de ejecución, lo cual dota al diseño de una gran flexibilidad. Los fabricantes de FPGAs ofrecen arquitecturas predefinidas con la posibilidad de añadir bloques prediseñados y poder formar sistemas en chip de una forma más o menos directa. Sin embargo, la forma en la que estos módulos hardware están organizados dentro de la arquitectura interna ya sea estática o dinámicamente, o la forma en la que la información se intercambia entre ellos, influye enormemente en la capacidad de cómputo y eficiencia energética del sistema. De la misma forma, la capacidad de cargar módulos hardware bajo demanda, permite añadir bloques redundantes que permitan aumentar el nivel de tolerancia a fallos de los sistemas. Sin embargo, la complejidad ligada al diseño de bloques hardware dedicados no debe ser subestimada. Es necesario tener en cuenta que el diseño de un bloque hardware no es sólo su propio diseño, sino también el diseño de sus interfaces, y en algunos casos de los drivers software para su manejo. Además, al añadir más bloques, el espacio de diseño se hace más complejo, y su programación más difícil. Aunque la mayoría de los fabricantes ofrecen interfaces predefinidas, IPs (por sus siglas en inglés, Intelectual Property) comerciales y plantillas para ayudar al diseño de los sistemas, para ser capaces de explotar las posibilidades reales del sistema, es necesario construir arquitecturas sobre las ya establecidas para facilitar el uso del paralelismo, la redundancia, y proporcionar un entorno que soporte la gestión dinámica de los recursos. Para proporcionar este tipo de soporte, ARTICo3 trabaja con un espacio de soluciones formado por tres ejes fundamentales: computación, consumo energético y confiabilidad. De esta forma, cada punto de trabajo se obtiene como una solución de compromiso entre estos tres parámetros. Mediante el uso de la reconfiguración dinámica y parcial y una mejora en la transmisión de los datos entre la memoria principal y los aceleradores, es posible dedicar un número variable de recursos en el tiempo para cada tarea, lo que hace que los recursos internos de la FPGA sean virtualmente ilimitados. Este variación en el tiempo del número de recursos por tarea se puede usar bien para incrementar el nivel de paralelismo, y por ende de aceleración, o bien para aumentar la redundancia, y por lo tanto el nivel de tolerancia a fallos. Al mismo tiempo, usar un numero óptimo de recursos para una tarea mejora el consumo energético ya que bien es posible disminuir la potencia instantánea consumida, o bien el tiempo de procesamiento. Con el objetivo de mantener los niveles de complejidad dentro de unos límites lógicos, es importante que los cambios realizados en el hardware sean totalmente transparentes para el código de aplicación. A este respecto, se incluyen distintos niveles de transparencia: • Transparencia a la escalabilidad: los recursos usados por una misma tarea pueden ser modificados sin que el código de aplicación sufra ningún cambio. • Transparencia al rendimiento: el sistema aumentara su rendimiento cuando la carga de trabajo aumente, sin cambios en el código de aplicación. • Transparencia a la replicación: es posible usar múltiples instancias de un mismo módulo bien para añadir redundancia o bien para incrementar la capacidad de procesamiento. Todo ello sin que el código de aplicación cambie. • Transparencia a la posición: la posición física de los módulos hardware es arbitraria para su direccionamiento desde el código de aplicación. • Transparencia a los fallos: si existe un fallo en un módulo hardware, gracias a la redundancia, el código de aplicación tomará directamente el resultado correcto. • Transparencia a la concurrencia: el hecho de que una tarea sea realizada por más o menos bloques es transparente para el código que la invoca. Por lo tanto, esta tesis doctoral contribuye en dos líneas diferentes. En primer lugar, con el diseño de la plataforma HiReCookie y en segundo lugar con el diseño de la arquitectura ARTICo3. Las principales contribuciones de esta tesis se resumen a continuación. • Arquitectura de la HiReCookie incluyendo: o Compatibilidad con la plataforma Cookies para incrementar las capacidades de esta. o División de la arquitectura en distintas islas de alimentación. o Implementación de los diversos modos de bajo consumo y políticas de despertado del nodo. o Creación de un archivo de configuración de la FPGA comprimido para reducir el tiempo y el consumo de la configuración inicial. • Diseño de la arquitectura reconfigurable para FPGAs basadas en RAM ARTICo3: o Modelo de computación y modos de ejecución inspirados en el modelo de CUDA pero basados en hardware reconfigurable con un número variable de bloques de hilos por cada unidad de ejecución. o Estructura para optimizar las transacciones de datos en ráfaga proporcionando datos en cascada o en paralelo a los distinto módulos incluyendo un proceso de votado por mayoría y operaciones de reducción. o Capa de abstracción entre el procesador principal que incluye el código de aplicación y los recursos asignados para las diferentes tareas. o Arquitectura de los módulos hardware reconfigurables para mantener la escalabilidad añadiendo una la interfaz para las nuevas funcionalidades con un simple acceso a una memoria RAM interna. o Caracterización online de las tareas para proporcionar información a un módulo de gestión de recursos para mejorar la operación en términos de energía y procesamiento cuando además se opera entre distintos nieles de tolerancia a fallos. El documento está dividido en dos partes principales formando un total de cinco capítulos. En primer lugar, después de motivar la necesidad de nuevas plataformas para cubrir las nuevas aplicaciones, se detalla el diseño de la plataforma HiReCookie, sus partes, las posibilidades para bajar el consumo energético y se muestran casos de uso de la plataforma así como pruebas de validación del diseño. La segunda parte del documento describe la arquitectura reconfigurable, su implementación en varias FPGAs, y pruebas de validación en términos de capacidad de procesamiento y consumo energético, incluyendo cómo estos aspectos se ven afectados por el nivel de tolerancia a fallos elegido. Los capítulos a lo largo del documento son los siguientes: El capítulo 1 analiza los principales objetivos, motivación y aspectos teóricos necesarios para seguir el resto del documento. El capítulo 2 está centrado en el diseño de la plataforma HiReCookie y sus posibilidades para disminuir el consumo de energía. El capítulo 3 describe la arquitectura reconfigurable ARTICo3. El capítulo 4 se centra en las pruebas de validación de la arquitectura usando la plataforma HiReCookie para la mayoría de los tests. Un ejemplo de aplicación es mostrado para analizar el funcionamiento de la arquitectura. El capítulo 5 concluye esta tesis doctoral comentando las conclusiones obtenidas, las contribuciones originales del trabajo y resultados y líneas futuras. ABSTRACT This PhD Thesis is framed within the field of dynamically reconfigurable embedded systems, advanced sensor networks and distributed computing. The document is centred on the study of processing solutions for high-performance autonomous distributed systems (HPADS) as well as their evolution towards High performance Computing (HPC) systems. The approach of the study is focused on both platform and processor levels to optimise critical aspects such as computing performance, energy efficiency and fault tolerance. HPADS are considered feedback systems, normally networked and/or distributed, with real-time adaptive and predictive functionality. These systems, as part of more complex systems known as Cyber-Physical Systems (CPSs), can be applied in a wide range of fields such as military, health care, manufacturing, aerospace, etc. For the design of HPADS, high levels of dependability, the definition of suitable models of computation, and the use of methodologies and tools to support scalability and complexity management, are required. The first part of the document studies the different possibilities at platform design level in the state of the art, together with description, development and validation tests of the platform proposed in this work to cope with the previously mentioned requirements. The main objectives targeted by this platform design are the following: • Study the feasibility of using SRAM-based FPGAs as the main processor of the platform in terms of energy consumption and performance for high demanding applications. • Analyse and propose energy management techniques to reduce energy consumption in every stage of the working profile of the platform. • Provide a solution with dynamic partial and wireless remote HW reconfiguration (DPR) to be able to change certain parts of the FPGA design at run time and on demand without interrupting the rest of the system. • Demonstrate the applicability of the platform in different test-bench applications. In order to select the best approach for the platform design in terms of processing alternatives, a study of the evolution of the state-of-the-art platforms is required to analyse how different architectures cope with new more demanding applications and scenarios: security, mixed-critical systems for aerospace, multimedia applications, or military environments, among others. In all these scenarios, important changes in the required processing bandwidth or the complexity of the algorithms used are provoking the migration of the platforms from single microprocessor architectures to multiprocessing and heterogeneous solutions with more instant power consumption but higher energy efficiency. Within these solutions, FPGAs and Systems on Chip including FPGA fabric and dedicated hard processors, offer a good trade of among flexibility, processing performance, energy consumption and price, when they are used in demanding applications where working conditions are very likely to vary over time and high complex algorithms are required. The platform architecture proposed in this PhD Thesis is called HiReCookie. It includes an SRAM-based FPGA as the main and only processing unit. The FPGA selected, the Xilinx Spartan-6 LX150, was at the beginning of this work the best choice in terms of amount of resources and power. Although, the power levels are the lowest of these kind of devices, they can be still very high for distributed systems that normally work powered by batteries. For that reason, it is necessary to include different energy saving possibilities to increase the usability of the platform. In order to reduce energy consumption, the platform architecture is divided into different power islands so that only those parts of the systems that are strictly needed are powered on, while the rest of the islands can be completely switched off. This allows a combination of different low power modes to decrease energy. In addition, one of the most important handicaps of SRAM-based FPGAs is that they are not alive at power up. Therefore, recovering the system from a switch-off state requires to reload the FPGA configuration from a non-volatile memory device. For that reason, this PhD Thesis also proposes a methodology to compress the FPGA configuration file in order to reduce time and energy during the initial configuration process. Although some of the requirements for the design of HPADS are already covered by the design of the HiReCookie platform, it is necessary to continue improving energy efficiency, computing performance and fault tolerance. This is only possible by exploiting all the opportunities provided by the processing architectures configured inside the FPGA. Therefore, the second part of the thesis details the design of the so called ARTICo3 FPGA architecture to enhance the already intrinsic capabilities of the FPGA. ARTICo3 is a DPR-capable bus-based virtual architecture for multiple HW acceleration in SRAM-based FPGAs. The architecture provides support for dynamic resource management in real time. In this way, by using DPR, it will be possible to change the levels of computing performance, energy consumption and fault tolerance on demand by increasing or decreasing the amount of resources used by the different tasks. Apart from the detailed design of the architecture and its implementation in different FPGA devices, different validation tests and comparisons are also shown. The main objectives targeted by this FPGA architecture are listed as follows: • Provide a method based on a multithread approach such as those offered by CUDA (Compute Unified Device Architecture) or OpenCL kernel executions, where kernels are executed in a variable number of HW accelerators without requiring application code changes. • Provide an architecture to dynamically adapt working points according to either self-measured or external parameters in terms of energy consumption, fault tolerance and computing performance. Taking advantage of DPR capabilities, the architecture must provide support for a dynamic use of resources in real time. • Exploit concurrent processing capabilities in a standard bus-based system by optimizing data transactions to and from HW accelerators. • Measure the advantage of HW acceleration as a technique to boost performance to improve processing times and save energy by reducing active times for distributed embedded systems. • Dynamically change the levels of HW redundancy to adapt fault tolerance in real time. • Provide HW abstraction from SW application design. FPGAs give the possibility of designing specific HW blocks for every required task to optimise performance while some of them include the possibility of including DPR. Apart from the possibilities provided by manufacturers, the way these HW modules are organised, addressed and multiplexed in area and time can improve computing performance and energy consumption. At the same time, fault tolerance and security techniques can also be dynamically included using DPR. However, the inherent complexity of designing new HW modules for every application is not negligible. It does not only consist of the HW description, but also the design of drivers and interfaces with the rest of the system, while the design space is widened and more complex to define and program. Even though the tools provided by the majority of manufacturers already include predefined bus interfaces, commercial IPs, and templates to ease application prototyping, it is necessary to improve these capabilities. By adding new architectures on top of them, it is possible to take advantage of parallelization and HW redundancy while providing a framework to ease the use of dynamic resource management. ARTICo3 works within a solution space where working points change at run time in a 3D space defined by three different axes: Computation, Consumption, and Fault Tolerance. Therefore, every working point is found as a trade-off solution among these three axes. By means of DPR, different accelerators can be multiplexed so that the amount of available resources for any application is virtually unlimited. Taking advantage of DPR capabilities and a novel way of transmitting data to the reconfigurable HW accelerators, it is possible to dedicate a dynamically-changing number of resources for a given task in order to either boost computing speed or adding HW redundancy and a voting process to increase fault-tolerance levels. At the same time, using an optimised amount of resources for a given task reduces energy consumption by reducing instant power or computing time. In order to keep level complexity under certain limits, it is important that HW changes are transparent for the application code. Therefore, different levels of transparency are targeted by the system: • Scalability transparency: a task must be able to expand its resources without changing the system structure or application algorithms. • Performance transparency: the system must reconfigure itself as load changes. • Replication transparency: multiple instances of the same task are loaded to increase reliability and performance. • Location transparency: resources are accessed with no knowledge of their location by the application code. • Failure transparency: task must be completed despite a failure in some components. • Concurrency transparency: different tasks will work in a concurrent way transparent to the application code. Therefore, as it can be seen, the Thesis is contributing in two different ways. First with the design of the HiReCookie platform and, second with the design of the ARTICo3 architecture. The main contributions of this PhD Thesis are then listed below: • Architecture of the HiReCookie platform including: o Compatibility of the processing layer for high performance applications with the Cookies Wireless Sensor Network platform for fast prototyping and implementation. o A division of the architecture in power islands. o All the different low-power modes. o The creation of the partial-initial bitstream together with the wake-up policies of the node. • The design of the reconfigurable architecture for SRAM FPGAs: ARTICo3: o A model of computation and execution modes inspired in CUDA but based on reconfigurable HW with a dynamic number of thread blocks per kernel. o A structure to optimise burst data transactions providing coalesced or parallel data to HW accelerators, parallel voting process and reduction operation. o The abstraction provided to the host processor with respect to the operation of the kernels in terms of the number of replicas, modes of operation, location in the reconfigurable area and addressing. o The architecture of the modules representing the thread blocks to make the system scalable by adding functional units only adding an access to a BRAM port. o The online characterization of the kernels to provide information to a scheduler or resource manager in terms of energy consumption and processing time when changing among different fault-tolerance levels, as well as if a kernel is expected to work in the memory-bounded or computing-bounded areas. The document of the Thesis is divided into two main parts with a total of five chapters. First, after motivating the need for new platforms to cover new more demanding applications, the design of the HiReCookie platform, its parts and several partial tests are detailed. The design of the platform alone does not cover all the needs of these applications. Therefore, the second part describes the architecture inside the FPGA, called ARTICo3, proposed in this PhD Thesis. The architecture and its implementation are tested in terms of energy consumption and computing performance showing different possibilities to improve fault tolerance and how this impact in energy and time of processing. Chapter 1 shows the main goals of this PhD Thesis and the technology background required to follow the rest of the document. Chapter 2 shows all the details about the design of the FPGA-based platform HiReCookie. Chapter 3 describes the ARTICo3 architecture. Chapter 4 is focused on the validation tests of the ARTICo3 architecture. An application for proof of concept is explained where typical kernels related to image processing and encryption algorithms are used. Further experimental analyses are performed using these kernels. Chapter 5 concludes the document analysing conclusions, comments about the contributions of the work, and some possible future lines for the work.

INFLUÊNCIA DO LASER DE BAIXA INTENSIDADE NA VELOCIDADE DA MOVIMENTAÇÃO ORTODÔNTICA

Este estudo investigou os efeitos do laser de baixa intensidade na velocidade da movimentação ortodôntica de caninos submetidos à retração inicial. A amostra constou de 26 caninos superiores e inferiores, submetidos à retração inicial realizada com mola Niti, com força de 150g. Um dos caninos foi irradiado com laser de diodo, seguindo o protocolo de aplicação: 780nm/20mW/5Jcm2/0,2J por ponto/Et=2J, nos dias 0, 3 e 7 pós-ativação, sendo que o contralateral foi considerado placebo. A retração durou em média 4 meses, num total de 9 aplicações de laser. Os modelos de cada mês foram escaneados com scanner 3D (3Shape) e as imagens tridimensionais foram analisadas por meio do Software Geomagic Studio 5, para a mensuração da quantidade de movimentação dos caninos retraídos. Foi empregada a Análise de Variância a três critérios, seguida pelo teste de Tukey (p<0,05). Para verificação da integridade tecidual, foram efetuadas radiografias periapicais iniciais e finais dos caninos retraídos e dos molares, nas quais foram avaliados uma possível reabsorção na crista alveolar, por meio da distância da crista óssea alveolar até a junção cemento-esmalte e os níveis de reabsorção radicular, por meio do índice de Levander e Malmgreen, sendo este último avaliado somente nos caninos retraídos. Para isto, foi empregado o teste não paramétrico de Wilcoxon (p<0,05). Os resultados indicaram que houve um aumento estatisticamente significante na velocidade da movimentação dos caninos irradiados comparados ao seu contralateral, em todos os tempos avaliados, como também a preservação da integridade tecidual. Com isso, concluiu-se que o laser de diodo pode acelerar a movimentação ortodôntica, podendo contribuir para a diminuição do tempo de tratamento.(AU)