Operating infrastructure for an FPGA and ARM system

Advances in FPGA technology and higher processing capabilities requirements have pushed to the emerge of All Programmable Systems-on-Chip, which incorporate a hard designed processing system and a programmable logic that enable the development of specialized computer systems for a wide range of practical applications, including data and signal processing, high performance computing, embedded systems, among many others. To give place to an infrastructure that is capable of using the benefits of such a reconfigurable system, the main goal of the thesis is to implement an infrastructure composed of hardware, software and network resources, that incorporates the necessary services for the operation, management and interface of peripherals, that coompose the basic building blocks for the execution of applications. The project will be developed using a chip from the Zynq-7000 All Programmable Systems-on-Chip family.

Arquitetura híbrida com DSP e FPGA para implementação de controladores de filtros ativos de potência

The presence of non-linear loads at a point in the distribution system may deform voltage waveform due to the consumption of non-sinusoidal currents. The use of active power filters allows significant reduction of the harmonic content in the supply current. However, the processing of digital control structures for these filters may require high performance hardware, particularly for reference currents calculation. This work describes the development of hardware structures with high processing capability for application in active power filters. In this sense, it considers an architecture that allows parallel processing using programmable logic devices. The developed structure uses a hybrid model using a DSP and an FPGA. The DSP is used for the acquisition of current and voltage signals, calculation of fundamental current related controllers and PWM generation. The FPGA is used for intensive signal processing, such as the harmonic compensators. In this way, from the experimental analysis, significant reductions of the processing time are achieved when compared to traditional approaches using only DSP. The experimental results validate the designed structure and these results are compared with other ones from architectures reported in the literature.

Principios del FPGA y aplicaciones en el control de procesos industriales

La presente investigación muestra los pasos sugeridos para introducirse a la creación de sistemas electrónicos programables a través de la tecnología FPGA. Un FPGA es un dispositivo programable de alta capacidad que puede ser utilizado para la creación de sistemas digitales de control y automatización de procesos. La investigación se divide en cuatro capítulos estructurados de la siguiente forma: Capítulo I- Teoría general: Abarca las características básicas de los FPGA en general y las del equipo a utilizar; Capítulo II-Software: Consta de un manual de usuario sobre el software utilizado en la investigación; Capítulo III-Laboratorios: Una serie de laboratorios prácticos; Capítulo IV- Aplicaciones: Metodología y ejemplo

Diseño e implementación en FPGA de un filtro de partículas para aplicaciones biomédicas

La diabetes mellitus tipo 1 (DM1) es una enfermedad crónica caracterizada por la incapacidad del páncreas de producir insulina. Esta hormona regula la absorción de la glucosa del torrente sanguíneo por parte de las células. Debido a la ausencia de insulina en el cuerpo, la glucosa se acumula en el torrente sanguíneo provocando problemas a corto y largo plazo, como por ejemplo deterioro celular. Los pacientes con esta enfermedad necesitan controlar su glucemia (concentración de glucosa en sangre) midiendo la misma de forma regular e inyectándose insulina subcutánea de por vida. Para conocer la glucemia se pueden utilizar Monitores Continuos de Glucosa (MCG), que proporcionan el valor de la glucosa intersticial en un rango entre uno y cinco minutos. Los MCG actuales presentan los siguientes problemas: Por un lado, el sensor que lleva incorporado introduce ruidos asociados a la medición obtenida. Y, por otro lado, el sensor se degrada a lo largo de su vida útil, lo que dificulta la interpretación de los datos obtenidos. La solución propuesta en este trabajo consiste en la utilización de filtros de partículas. Este tipo de filtros consta de cuatro fases: inicialización, predicción, corrección y remuestreo. Son capaces de identificar los estados ocultos del sistema (glucosa en sangre y degeneración del sensor), a partir de medidas indirectas del mismo (como por ejemplo la glucosa intersticial) teniendo en cuenta el ruido de las mediciones del MCG. En este proyecto se va a aplicar un filtro de partículas de cuatro estados (glucosa, velocidad de variación de la glucosa, degeneración del sensor y velocidad de variación de la degeneración del sensor.). En primera instancia, se utilizará la herramienta Matlab para analizar el correcto funcionamiento de este algoritmo frente a los problemas mencionados anteriormente de los MCG. Y, en segundo lugar, se realizará una implementación hardware sobre una FPGA.

A Study of the Robustness Against SEUs of Digital Circuits Implemented with FPGA DSPs

In this paper we present an experimental validation of the reliability increase of digital circuits implemented in XilinxTMFPGAs when they are implemented using the DSPs (Digital Signal Processors) that are available in the reconfigurable device. For this purpose, we have used a fault-injection platform developed by our research group, NESSY [1]. The presented experiments demonstrate that the probability of occurrence of a SEU effect is similar both in the circuits implemented with and without using embedded DSPs. However, the former are more efficient in terms of area usage, which leads to a decrease in the probability of a SEU occurrence.

Implémentation sur FPGA de l’algorithme MUSIC sur antenne-réseau expérimentale à 10 GHz

Les techniques des directions d’arrivée (DOA) sont une voie prometteuse pour accroitre la capacité des systèmes et les services de télécommunications en permettant de mieux estimer le canal radio-mobile. Elles permettent aussi de suivre précisément des usagers cellulaires pour orienter les faisceaux d’antennes dans leur direction. S’inscrivant dans ce contexte, ce présent mémoire décrit étape par étape l’implémentation de l’algorithme de haut niveau MUSIC (MUltiple SIgnal Classification) sur une plateforme FPGA afin de déterminer en temps réel l’angle d’arrivée d’une ou des sources incidentes à un réseau d’antennes. Le concept du prototypage rapide des lois de commande (RCP) avec les outils de XilinxTM System generator (XSG) et du MBDK (Model Based Design Kit) de NutaqTM est le concept de développement utilisé. Ce concept se base sur une programmation de code haut niveau à travers des modèles, pour générer automatiquement un code de bas niveau. Une attention particulière est portée sur la méthode choisie pour résoudre le problème de la décomposition en valeurs et vecteurs propres de la matrice complexe de covariance par l’algorithme de Jacobi. L’architecture mise en place implémentant cette dernière dans le FPGA (Field Programmable Gate Array) est détaillée. Par ailleurs, il est prouvé que MUSIC ne peut effectuer une estimation intéressante de la position des sources sans une calibration préalable du réseau d’antennes. Ainsi, la technique de calibration par matrice G utilisée dans ce projet est présentée, en plus de son modèle d’implémentation. Enfin, les résultats expérimentaux du système mis à l’épreuve dans un environnement réel en présence d’une source puis de deux sources fortement corrélées sont illustrés et analysés.

Characteristic analysis for multisampled digital implementation of fixed-switching-frequency closed-loop modulation of voltage-source inverter

In this paper, a fixed-switching-frequency closed-loop modulation of a voltage-source inverter (VSI), upon the digital implementation of the modulation process, is analyzed and characterized. The sampling frequency of the digital processor is considered as an integer multiple of the modulation switching frequency. An expression for the determination of the modulation design parameter is developed for smooth modulation at a fixed switching frequency. The variation of the sampling frequency, switching frequency, and modulation index has been analyzed for the determination of the switching condition under closed loop. It is shown that the switching condition determined based on the continuous-time analysis of the closed-loop modulation will ensure smooth modulation upon the digital implementation of the modulation process. However, the stability properties need to be tested prior to digital implementation as they get deteriorated at smaller sampling frequencies. The closed-loop modulation index needs to be considered maximum while determining the design parameters for smooth modulation. In particular, a detailed analysis has been carried out by varying the control gain in the sliding-mode control of a two-level VSI. The proposed analysis of the closed-loop modulation of the VSI has been verified for the operation of a distribution static compensator. The theoretical results are validated experimentally on both single- and three-phase systems.

Vision-based topological mapping and localisation

Competent navigation in an environment is a major requirement for an autonomous mobile robot to accomplish its mission. Nowadays, many successful systems for navigating a mobile robot use an internal map which represents the environment in a detailed geometric manner. However, building, maintaining and using such environment maps for navigation is difficult because of perceptual aliasing and measurement noise. Moreover, geometric maps require the processing of huge amounts of data which is computationally expensive. This thesis addresses the problem of vision-based topological mapping and localisation for mobile robot navigation. Topological maps are concise and graphical representations of environments that are scalable and amenable to symbolic manipulation. Thus, they are well-suited for basic robot navigation applications, and also provide a representational basis for the procedural and semantic information needed for higher-level robotic tasks. In order to make vision-based topological navigation suitable for inexpensive mobile robots for the mass market we propose to characterise key places of the environment based on their visual appearance through colour histograms. The approach for representing places using visual appearance is based on the fact that colour histograms change slowly as the field of vision sweeps the scene when a robot moves through an environment. Hence, a place represents a region of the environment rather than a single position. We demonstrate in experiments using an indoor data set, that a topological map in which places are characterised using visual appearance augmented with metric clues provides sufficient information to perform continuous metric localisation which is robust to the kidnapped robot problem. Many topological mapping methods build a topological map by clustering visual observations to places. However, due to perceptual aliasing observations from different places may be mapped to the same place representative in the topological map. A main contribution of this thesis is a novel approach for dealing with the perceptual aliasing problem in topological mapping. We propose to incorporate neighbourhood relations for disambiguating places which otherwise are indistinguishable. We present a constraint based stochastic local search method which integrates the approach for place disambiguation in order to induce a topological map. Experiments show that the proposed method is capable of mapping environments with a high degree of perceptual aliasing, and that a small map is found quickly. Moreover, the method of using neighbourhood information for place disambiguation is integrated into a framework for topological off-line simultaneous localisation and mapping which does not require an initial categorisation of visual observations. Experiments on an indoor data set demonstrate the suitability of our method to reliably localise the robot while building a topological map.

Low-cost hardware speech enhancement for improved speech recognition in automotive environments

Voice recognition is one of the key enablers to reduce driver distraction as in-vehicle systems become more and more complex. With the integration of voice recognition in vehicles, safety and usability are improved as the driver’s eyes and hands are not required to operate system controls. Whilst speaker independent voice recognition is well developed, performance in high noise environments (e.g. vehicles) is still limited. La Trobe University and Queensland University of Technology have developed a low-cost hardware-based speech enhancement system for automotive environments based on spectral subtraction and delay–sum beamforming techniques. The enhancement algorithms have been optimised using authentic Australian English collected under typical driving conditions. Performance tests conducted using speech data collected under variety of vehicle noise conditions demonstrate a word recognition rate improvement in the order of 10% or more under the noisiest conditions. Currently developed to a proof of concept stage there is potential for even greater performance improvement.

A hardware-based multi-disciplinary design optimization method for aeronautical applications

There are many applications in aeronautics where there exist strong couplings between disciplines. One practical example is within the context of Unmanned Aerial Vehicle(UAV) automation where there exists strong coupling between operation constraints, aerodynamics, vehicle dynamics, mission and path planning. UAV path planning can be done either online or offline. The current state of path planning optimisation online UAVs with high performance computation is not at the same level as its ground-based offline optimizer's counterpart, this is mainly due to the volume, power and weight limitations on the UAV; some small UAVs do not have the computational power needed for some optimisation and path planning task. In this paper, we describe an optimisation method which can be applied to Multi-disciplinary Design Optimisation problems and UAV path planning problems. Hardware-based design optimisation techniques are used. The power and physical limitations of UAV, which may not be a problem in PC-based solutions, can be approached by utilizing a Field Programmable Gate Array (FPGA) as an algorithm accelerator. The inevitable latency produced by the iterative process of an Evolutionary Algorithm (EA) is concealed by exploiting the parallelism component within the dataflow paradigm of the EA on an FPGA architecture. Results compare software PC-based solutions and the hardware-based solutions for benchmark mathematical problems as well as a simple real world engineering problem. Results also indicate the practicality of the method which can be used for more complex single and multi objective coupled problems in aeronautical applications.

Experiences with implementing common mathematical operations using field programmable gate arrays

Many computationally intensive scientific applications involve repetitive floating point operations other than addition and multiplication which may present a significant performance bottleneck due to the relatively large latency or low throughput involved in executing such arithmetic primitives on commod- ity processors. A promising alternative is to execute such primitives on Field Programmable Gate Array (FPGA) hardware acting as an application-specific custom co-processor in a high performance reconfig- urable computing platform. The use of FPGAs can provide advantages such as fine-grain parallelism but issues relating to code development in a hardware description language and efficient data transfer to and from the FPGA chip can present significant application development challenges. In this paper, we discuss our practical experiences in developing a selection of floating point hardware designs to be implemented using FPGAs. Our designs include some basic mathemati cal library functions which can be implemented for user defined precisions suitable for novel applications requiring non-standard floating point represen- tation. We discuss the details of our designs along with results from performance and accuracy analysis tests.

Frame-rate stereopsis using non-parametric transforms and programmable logic

A frame-rate stereo vision system, based on non-parametric matching metrics, is described. Traditional metrics, such as normalized cross-correlation, are expensive in terms of logic. Non-parametric measures require only simple, parallelizable, functions such as comparators, counters and exclusive-or, and are thus very well suited to implementation in reprogrammable logic.

Calculation of engine parameters using reconfigurable hardware

The feasibility of real-time calculation of parameters for an internal combustion engine via reconfigurable hardware implementation is investigated as an alternative to software computation. A detailed in-hardware field programmable gate array (FPGA)-based design is developed and evaluated using input crank angle and in-cylinder pressure data from fully instrumented diesel engines in the QUT Biofuel Engine Research Facility (BERF). Results indicate the feasibility of employing a hardware-based implementation for real-time processing for speeds comparable to the data sampling rate currently used in the facility, with acceptably low level of discrepancies between hardware and software-based calculation of key engine parameters.

The Spartan-3E tutorial 3 : using the LCD display [version 1.0]

This tutorial is designed to assist users who wish to use the LCD screen on the Spartan-3E board. In this tutorial, the PicoBlaze microcontroller is used to control the LCD. The tutorial is organised into three Parts. In Part A, code is written to display the message "Hello World" on the LCD. Part B demonstrates how to define and display custom characters. Finally, Part C shows how the display can be shifted and flashed. Shifting is done by using a delay in the main PicoBlaze program loop, while flashing is done using the PicoBlaze interrupt. The slider switches can be used to select the shifting direction, and to turn shifting and flashing on and off.