A voltage disturbances prototype for testing electrical generators connected to microgrids

The search for new energy models arises as a necessity to have a sustainable power supply. The inclusion of distributed generation sources (DG) allows to reduce the cost of facilities, increase the security of the grid or alleviate problems of congestion through the redistribution of power flows. In remote microgrids it is needed in a particular way a safe and reliable supply, which can cover the demand for a low cost; due to this, distributed generation is an alternative that is being widely introduced in these grids. But the remote microgrids are especially weak grids because of their small size, low voltage level, reduced network mesh and distribution lines with a high ratio R/X. This ratio affects the coupling between grid voltages and phase shifts, and stability becomes an issue of greater importance than in interconnected systems. To ensure the appropriate behavior of generation sources inserted in remote microgrids -and, in general, any electrical equipment-, it is essential to have devices for testing and certification. These devices must, not only faithfully reproduce disturbances occurring in remote microgrids, but also to behave against the equipment under test (EUT) as a real weak grid. This also makes the device commercially competitive. To meet these objectives and based on the aforementioned, it has been designed, built and tested a voltage disturbances generator, in order to provide a simple, versatile, full and easily scalable device to manufacturers and laboratories in the sector.

A methodology to analyze, design and implement very fast and robust controls of Buck-type converters

La electrónica digital moderna presenta un desafío a los diseñadores de sistemas de potencia. El creciente alto rendimiento de microprocesadores, FPGAs y ASICs necesitan sistemas de alimentación que cumplan con requirimientos dinámicos y estáticos muy estrictos. Específicamente, estas alimentaciones son convertidores DC-DC de baja tensión y alta corriente que necesitan ser diseñados para tener un pequeño rizado de tensión y una pequeña desviación de tensión de salida bajo transitorios de carga de una alta pendiente. Además, dependiendo de la aplicación, se necesita cumplir con otros requerimientos tal y como proveer a la carga con ”Escalado dinámico de tensión”, donde el convertidor necesitar cambiar su tensión de salida tan rápidamente posible sin sobreoscilaciones, o ”Posicionado Adaptativo de la Tensión” donde la tensión de salida se reduce ligeramente cuanto más grande sea la potencia de salida. Por supuesto, desde el punto de vista de la industria, las figuras de mérito de estos convertidores son el coste, la eficiencia y el tamaño/peso. Idealmente, la industria necesita un convertidor que es más barato, más eficiente, más pequeño y que aún así cumpla con los requerimienos dinámicos de la aplicación. En este contexto, varios enfoques para mejorar la figuras de mérito de estos convertidores se han seguido por la industria y la academia tales como mejorar la topología del convertidor, mejorar la tecnología de semiconducores y mejorar el control. En efecto, el control es una parte fundamental en estas aplicaciones ya que un control muy rápido hace que sea más fácil que una determinada topología cumpla con los estrictos requerimientos dinámicos y, consecuentemente, le da al diseñador un margen de libertar más amplio para mejorar el coste, la eficiencia y/o el tamaño del sistema de potencia. En esta tesis, se investiga cómo diseñar e implementar controles muy rápidos para el convertidor tipo Buck. En esta tesis se demuestra que medir la tensión de salida es todo lo que se necesita para lograr una respuesta casi óptima y se propone una guía de diseño unificada para controles que sólo miden la tensión de salida Luego, para asegurar robustez en controles muy rápidos, se proponen un modelado y un análisis de estabilidad muy precisos de convertidores DC-DC que tienen en cuenta circuitería para sensado y elementos parásitos críticos. También, usando este modelado, se propone una algoritmo de optimización que tiene en cuenta las tolerancias de los componentes y sensados distorsionados. Us ando este algoritmo, se comparan controles muy rápidos del estado del arte y su capacidad para lograr una rápida respuesta dinámica se posiciona según el condensador de salida utilizado. Además, se propone una técnica para mejorar la respuesta dinámica de los controladores. Todas las propuestas se han corroborado por extensas simulaciones y prototipos experimentales. Con todo, esta tesis sirve como una metodología para ingenieros para diseñar e implementar controles rápidos y robustos de convertidores tipo Buck. ABSTRACT Modern digital electronics present a challenge to designers of power systems. The increasingly high-performance of microprocessors, FPGAs (Field Programmable Gate Array) and ASICs (Application-Specific Integrated Circuit) require power supplies to comply with very demanding static and dynamic requirements. Specifically, these power supplies are low-voltage/high-current DC-DC converters that need to be designed to exhibit low voltage ripple and low voltage deviation under high slew-rate load transients. Additionally, depending on the application, other requirements need to be met such as to provide to the load ”Dynamic Voltage Scaling” (DVS), where the converter needs to change the output voltage as fast as possible without underdamping, or ”Adaptive Voltage Positioning” (AVP) where the output voltage is slightly reduced the greater the output power. Of course, from the point of view of the industry, the figures of merit of these converters are the cost, efficiency and size/weight. Ideally, the industry needs a converter that is cheaper, more efficient, smaller and that can still meet the dynamic requirements of the application. In this context, several approaches to improve the figures of merit of these power supplies are followed in the industry and academia such as improving the topology of the converter, improving the semiconductor technology and improving the control. Indeed, the control is a fundamental part in these applications as a very fast control makes it easier for the topology to comply with the strict dynamic requirements and, consequently, gives the designer a larger margin of freedom to improve the cost, efficiency and/or size of the power supply. In this thesis, how to design and implement very fast controls for the Buck converter is investigated. This thesis proves that sensing the output voltage is all that is needed to achieve an almost time-optimal response and a unified design guideline for controls that only sense the output voltage is proposed. Then, in order to assure robustness in very fast controls, a very accurate modeling and stability analysis of DC-DC converters is proposed that takes into account sensing networks and critical parasitic elements. Also, using this modeling approach, an optimization algorithm that takes into account tolerances of components and distorted measurements is proposed. With the use of the algorithm, very fast analog controls of the state-of-the-art are compared and their capabilities to achieve a fast dynamic response are positioned de pending on the output capacitor. Additionally, a technique to improve the dynamic response of controllers is also proposed. All the proposals are corroborated by extensive simulations and experimental prototypes. Overall, this thesis serves as a methodology for engineers to design and implement fast and robust controls for Buck-type converters.

Output Impedance Correction Circuit (OICC): A New Concept to Improve the Dynamic Response of DC/DC Converters with Additional Energy Path

El desarrollo da las nuevas tecnologías permite a los ingenieros llevar al límite el funcionamiento de los circuitos integrados (Integrated Circuits, IC). Las nuevas generaciones de procesadores, DSPs o FPGAs son capaces de procesar la información a una alta velocidad, con un alto consumo de energía, o esperar en modo de baja potencia con el mínimo consumo posible. Esta gran variación en el consumo de potencia y el corto tiempo necesario para cambiar de un nivel al otro, afecta a las especificaciones del Módulo de Regulador de Tensión (Voltage Regulated Module, VRM) que alimenta al IC. Además, las características adicionales obligatorias, tales como adaptación del nivel de tensión (Adaptive Voltage Positioning, AVP) y escalado dinámico de la tensión (Dynamic Voltage Scaling, DVS), imponen requisitos opuestas en el diseño de la etapa de potencia del VRM. Para poder soportar las altas variaciones de los escalones de carga, el condensador de filtro de salida del VRM se ha de sobredimensionar, penalizando la densidad de energía y el rendimiento durante la operación de DVS. Por tanto, las actuales tendencias de investigación se centran en mejorar la respuesta dinámica del VRM, mientras se reduce el tamaño del condensador de salida. La reducción del condensador de salida lleva a menor coste y una prolongación de la vida del sistema ya que se podría evitar el uso de condensadores voluminosos, normalmente implementados con condensadores OSCON. Una ventaja adicional es que reduciendo el condensador de salida, el DVS se puede realizar más rápido y con menor estrés de la etapa de potencia, ya que la cantidad de carga necesaria para cambiar la tensión de salida es menor. El comportamiento dinámico del sistema con un control lineal (Control Modo Tensión, VMC, o Control Corriente de Pico, Peak Current Mode Control, PCMC,…) está limitado por la frecuencia de conmutación del convertidor y por el tamaño del filtro de salida. La reducción del condensador de salida se puede lograr incrementando la frecuencia de conmutación, así como incrementando el ancho de banda del sistema, y/o aplicando controles avanzados no-lineales. Usando esos controles, las variables del estado se saturan para conseguir el nuevo régimen permanente en un tiempo mínimo, así como el filtro de salida, más específicamente la pendiente de la corriente de la bobina, define la respuesta de la tensión de salida. Por tanto, reduciendo la inductancia de la bobina de salida, la corriente de bobina llega más rápido al nuevo régimen permanente, por lo que una menor cantidad de carga es tomada del condensador de salida durante el tránsito. El inconveniente de esa propuesta es que el rendimiento del sistema es penalizado debido al incremento de pérdidas de conmutación y las corrientes RMS. Para conseguir tanto la reducción del condensador de salida como el alto rendimiento del sistema, mientras se satisfacen las estrictas especificaciones dinámicas, un convertidor multifase es adoptado como estándar para aplicaciones VRM. Para asegurar el reparto de las corrientes entre fases, el convertidor multifase se suele implementar con control de modo de corriente. Para superar la limitación impuesta por el filtro de salida, la segunda posibilidad para reducir el condensador de salida es aplicar alguna modificación topológica (Topologic modifications) de la etapa básica de potencia para incrementar la pendiente de la corriente de bobina y así reducir la duración de tránsito. Como el transitorio se ha reducido, una menor cantidad de carga es tomada del condensador de salida bajo el mismo escalón de la corriente de salida, con lo cual, el condensador de salida se puede reducir para lograr la misma desviación de la tensión de salida. La tercera posibilidad para reducir el condensador de salida del convertidor es introducir un camino auxiliar de energía (additional energy path, AEP) para compensar el desequilibrio de la carga del condensador de salida reduciendo consecuentemente la duración del transitorio y la desviación de la tensión de salida. De esta manera, durante el régimen permanente, el sistema tiene un alto rendimiento debido a que el convertidor principal con bajo ancho de banda es diseñado para trabajar con una frecuencia de conmutación moderada para conseguir requisitos estáticos. Por otro lado, el comportamiento dinámico durante los transitorios es determinado por el AEP con un alto ancho de banda. El AEP puede ser implementado como un camino resistivo, como regulador lineal (Linear regulator, LR) o como un convertidor conmutado. Las dos primeras implementaciones proveen un mayor ancho de banda, acosta del incremento de pérdidas durante el transitorio. Por otro lado, la implementación del convertidor computado presenta menor ancho de banda, limitado por la frecuencia de conmutación, aunque produce menores pérdidas comparado con las dos anteriores implementaciones. Dependiendo de la aplicación, la implementación y la estrategia de control del sistema, hay una variedad de soluciones propuestas en el Estado del Arte (State-of-the-Art, SoA), teniendo diferentes propiedades donde una solución ofrece más ventajas que las otras, pero también unas desventajas. En general, un sistema con AEP ideal debería tener las siguientes propiedades: 1. El impacto del AEP a las pérdidas del sistema debería ser mínimo. A lo largo de la operación, el AEP genera pérdidas adicionales, con lo cual, en el caso ideal, el AEP debería trabajar por un pequeño intervalo de tiempo, solo durante los tránsitos; la otra opción es tener el AEP constantemente activo pero, por la compensación del rizado de la corriente de bobina, se generan pérdidas innecesarias. 2. El AEP debería ser activado inmediatamente para minimizar la desviación de la tensión de salida. Para conseguir una activación casi instantánea, el sistema puede ser informado por la carga antes del escalón o el sistema puede observar la corriente del condensador de salida, debido a que es la primera variable del estado que actúa a la perturbación de la corriente de salida. De esa manera, el AEP es activado con casi cero error de la tensión de salida, logrando una menor desviación de la tensión de salida. 3. El AEP debería ser desactivado una vez que el nuevo régimen permanente es detectado para evitar los transitorios adicionales de establecimiento. La mayoría de las soluciones de SoA estiman la duración del transitorio, que puede provocar un transitorio adicional si la estimación no se ha hecho correctamente (por ejemplo, si la corriente de bobina del convertidor principal tiene un nivel superior o inferior al necesitado, el regulador lento del convertidor principal tiene que compensar esa diferencia una vez que el AEP es desactivado). Otras soluciones de SoA observan las variables de estado, asegurando que el sistema llegue al nuevo régimen permanente, o pueden ser informadas por la carga. 4. Durante el transitorio, como mínimo un subsistema, o bien el convertidor principal o el AEP, debería operar en el lazo cerrado. Implementando un sistema en el lazo cerrado, preferiblemente el subsistema AEP por su ancho de banda elevado, se incrementa la robustez del sistema a los parásitos. Además, el AEP puede operar con cualquier tipo de corriente de carga. Las soluciones que funcionan en el lazo abierto suelen preformar el control de balance de carga con mínimo tiempo, así reducen la duración del transitorio y tienen un impacto menor a las pérdidas del sistema. Por otro lado, esas soluciones demuestran una alta sensibilidad a las tolerancias y parásitos de los componentes. 5. El AEP debería inyectar la corriente a la salida en una manera controlada, así se reduce el riesgo de unas corrientes elevadas y potencialmente peligrosas y se incrementa la robustez del sistema bajo las perturbaciones de la tensión de entrada. Ese problema suele ser relacionado con los sistemas donde el AEP es implementado como un convertidor auxiliar. El convertidor auxiliar es diseñado para una potencia baja, con lo cual, los dispositivos elegidos son de baja corriente/potencia. Si la corriente no es controlada, bajo un pico de tensión de entrada provocada por otro parte del sistema (por ejemplo, otro convertidor conectado al mismo bus), se puede llegar a un pico en la corriente auxiliar que puede causar la perturbación de tensión de salida e incluso el fallo de los dispositivos del convertidor auxiliar. Sin embargo, cuando la corriente es controlada, usando control del pico de corriente o control con histéresis, la corriente auxiliar tiene el control con prealimentación (feed-forward) de tensión de entrada y la corriente es definida y limitada. Por otro lado, si la solución utiliza el control de balance de carga, el sistema puede actuar de forma deficiente si la tensión de entrada tiene un valor diferente del nominal, provocando que el AEP inyecta/toma más/menos carga que necesitada. 6. Escalabilidad del sistema a convertidores multifase. Como ya ha sido comentado anteriormente, para las aplicaciones VRM por la corriente de carga elevada, el convertidor principal suele ser implementado como multifase para distribuir las perdidas entre las fases y bajar el estrés térmico de los dispositivos. Para asegurar el reparto de las corrientes, normalmente un control de modo corriente es usado. Las soluciones de SoA que usan VMC son limitadas a la implementación con solo una fase. Esta tesis propone un nuevo método de control del flujo de energía por el AEP y el convertidor principal. El concepto propuesto se basa en la inyección controlada de la corriente auxiliar al nodo de salida donde la amplitud de la corriente es n-1 veces mayor que la corriente del condensador de salida con las direcciones apropiadas. De esta manera, el AEP genera un condensador virtual cuya capacidad es n veces mayor que el condensador físico y reduce la impedancia de salida. Como el concepto propuesto reduce la impedancia de salida usando el AEP, el concepto es llamado Output Impedance Correction Circuit (OICC) concept. El concepto se desarrolla para un convertidor tipo reductor síncrono multifase con control modo de corriente CMC (incluyendo e implementación con una fase) y puede operar con la tensión de salida constante o con AVP. Además, el concepto es extendido a un convertidor de una fase con control modo de tensión VMC. Durante la operación, el control de tensión de salida de convertidor principal y control de corriente del subsistema OICC están siempre cerrados, incrementando la robustez a las tolerancias de componentes y a los parásitos del cirquito y permitiendo que el sistema se pueda enfrentar a cualquier tipo de la corriente de carga. Según el método de control propuesto, el sistema se puede encontrar en dos estados: durante el régimen permanente, el sistema se encuentra en el estado Idle y el subsistema OICC esta desactivado. Por otro lado, durante el transitorio, el sistema se encuentra en estado Activo y el subsistema OICC está activado para reducir la impedancia de salida. El cambio entre los estados se hace de forma autónoma: el sistema entra en el estado Activo observando la corriente de condensador de salida y vuelve al estado Idle cunado el nuevo régimen permanente es detectado, observando las variables del estado. La validación del concepto OICC es hecha aplicándolo a un convertidor tipo reductor síncrono con dos fases y de 30W cuyo condensador de salida tiene capacidad de 140μF, mientras el factor de multiplicación n es 15, generando en el estado Activo el condensador virtual de 2.1mF. El subsistema OICC es implementado como un convertidor tipo reductor síncrono con PCMC. Comparando el funcionamiento del convertidor con y sin el OICC, los resultados demuestran que se ha logrado una reducción de la desviación de tensión de salida con factor 12, tanto con funcionamiento básico como con funcionamiento AVP. Además, los resultados son comparados con un prototipo de referencia que tiene la misma etapa de potencia y un condensador de salida físico de 2.1mF. Los resultados demuestran que los dos sistemas tienen el mismo comportamiento dinámico. Más aun, se ha cuantificado el impacto en las pérdidas del sistema operando bajo una corriente de carga pulsante y bajo DVS. Se demuestra que el sistema con OICC mejora el rendimiento del sistema, considerando las pérdidas cuando el sistema trabaja con la carga pulsante y con DVS. Por lo último, el condensador de salida de sistema con OICC es mucho más pequeño que el condensador de salida del convertidor de referencia, con lo cual, por usar el concepto OICC, la densidad de energía se incrementa. En resumen, las contribuciones principales de la tesis son: • El concepto propuesto de Output Impedance Correction Circuit (OICC), • El control a nivel de sistema basado en el método usado para cambiar los estados de operación, • La implementación del subsistema OICC en lazo cerrado conjunto con la implementación del convertidor principal, • La cuantificación de las perdidas dinámicas bajo la carga pulsante y bajo la operación DVS, y • La robustez del sistema bajo la variación del condensador de salida y bajo los escalones de carga consecutiva. ABSTRACT Development of new technologies allows engineers to push the performance of the integrated circuits to its limits. New generations of processors, DSPs or FPGAs are able to process information with high speed and high consumption or to wait in low power mode with minimum possible consumption. This huge variation in power consumption and the short time needed to change from one level to another, affect the specifications of the Voltage Regulated Module (VRM) that supplies the IC. Furthermore, additional mandatory features, such as Adaptive Voltage Positioning (AVP) and Dynamic Voltage Scaling (DVS), impose opposite trends on the design of the VRM power stage. In order to cope with high load-step amplitudes, the output capacitor of the VRM power stage output filter is drastically oversized, penalizing power density and the efficiency during the DVS operation. Therefore, the ongoing research trend is directed to improve the dynamic response of the VRM while reducing the size of the output capacitor. The output capacitor reduction leads to a smaller cost and longer life-time of the system since the big bulk capacitors, usually implemented with OSCON capacitors, may not be needed to achieve the desired dynamic behavior. An additional advantage is that, by reducing the output capacitance, dynamic voltage scaling (DVS) can be performed faster and with smaller stress on the power stage, since the needed amount of charge to change the output voltage is smaller. The dynamic behavior of the system with a linear control (Voltage mode control, VMC, Peak Current Mode Control, PCMC,…) is limited by the converter switching frequency and filter size. The reduction of the output capacitor can be achieved by increasing the switching frequency of the converter, thus increasing the bandwidth of the system, and/or by applying advanced non-linear controls. Applying nonlinear control, the system variables get saturated in order to reach the new steady-state in a minimum time, thus the output filter, more specifically the output inductor current slew-rate, determines the output voltage response. Therefore, by reducing the output inductor value, the inductor current reaches faster the new steady state, so a smaller amount of charge is taken from the output capacitor during the transient. The drawback of this approach is that the system efficiency is penalized due to increased switching losses and RMS currents. In order to achieve both the output capacitor reduction and high system efficiency, while satisfying strict dynamic specifications, a Multiphase converter system is adopted as a standard for VRM applications. In order to ensure the current sharing among the phases, the multiphase converter is usually implemented with current mode control. In order to overcome the limitation imposed by the output filter, the second possibility to reduce the output capacitor is to apply Topologic modifications of the basic power stage topology in order to increase the slew-rate of the inductor current and, therefore, reduce the transient duration. Since the transient is reduced, smaller amount of charge is taken from the output capacitor under the same load current, thus, the output capacitor can be reduced to achieve the same output voltage deviation. The third possibility to reduce the output capacitor of the converter is to introduce an additional energy path (AEP) to compensate the charge unbalance of the output capacitor, consequently reducing the transient time and output voltage deviation. Doing so, during the steady-state operation the system has high efficiency because the main low-bandwidth converter is designed to operate at moderate switching frequency, to meet the static requirements, whereas the dynamic behavior during the transients is determined by the high-bandwidth auxiliary energy path. The auxiliary energy path can be implemented as a resistive path, as a Linear regulator, LR, or as a switching converter. The first two implementations provide higher bandwidth, at the expense of increasing losses during the transient. On the other hand, the switching converter implementation presents lower bandwidth, limited by the auxiliary converter switching frequency, though it produces smaller losses compared to the two previous implementations. Depending on the application, the implementation and the control strategy of the system, there is a variety of proposed solutions in the State-of-the-Art (SoA), having different features where one solution offers some advantages over the others, but also some disadvantages. In general, an ideal additional energy path system should have the following features: 1. The impact on the system losses should be minimal. During its operation, the AEP generates additional losses, thus ideally, the AEP should operate for a short period of time, only when the transient is occurring; the other option is to have the AEP constantly on, but due to the inductor current ripple compensation at the output, unnecessary losses are generated. 2. The AEP should be activated nearly instantaneously to prevent bigger output voltage deviation. To achieve near instantaneous activation, the converter system can be informed by the load prior to the load-step or the system can observe the output capacitor current, which is the first system state variable that reacts on the load current perturbation. In this manner, the AEP is turned on with near zero output voltage error, providing smaller output voltage deviation. 3. The AEP should be deactivated once the new steady state is reached to avoid additional settling transients. Most of the SoA solutions estimate duration of the transient which may cause additional transient if the estimation is not performed correctly (e.g. if the main converter inductor current has higher or lower value than needed, the slow regulator of the main converter needs to compensate the difference after the AEP is deactivated). Other SoA solutions are observing state variables, ensuring that the system reaches the new steady state or they are informed by the load. 4. During the transient, at least one subsystem, either the main converter or the AEP, should be in closed-loop. Implementing a closed loop system, preferably the AEP subsystem, due its higher bandwidth, increases the robustness under system tolerances and circuit parasitic. In addition, the AEP can operate with any type of load. The solutions that operate in open loop usually perform minimum time charge balance control, thus reducing the transient length and minimizing the impact on the losses, however they are very sensitive to tolerances and parasitics. 5. The AEP should inject current at the output in a controlled manner, thus reducing the risk of high and potentially damaging currents and increasing robustness on the input voltage deviation. This issue is mainly related to the systems where AEP is implemented as auxiliary converter. The auxiliary converter is designed for small power and, as such, the MOSFETs are rated for small power/currents. If the current is not controlled, due to the some unpredicted spike in input voltage caused by some other part of the system (e.g. different converter), it may lead to a current spike in auxiliary current which will cause the perturbation of the output voltage and even failure of the switching components of auxiliary converter. In the case when the current is controlled, using peak CMC or Hysteretic Window CMC, the auxiliary converter has inherent feed-forwarding of the input voltage in current control and the current is defined and limited. Furthermore, if the solution employs charge balance control, the system may perform poorly if the input voltage has different value than the nominal, causing that AEP injects/extracts more/less charge than needed. 6. Scalability of the system to multiphase converters. As commented previously, in VRM applications, due to the high load currents, the main converters are implemented as multiphase to redistribute losses among the modules, lowering temperature stress of the components. To ensure the current sharing, usually a Current Mode Control (CMC) is employed. The SoA solutions that are implemented with VMC are limited to a single stage implementation. This thesis proposes a novel control method of the energy flow through the AEP and the main converter system. The proposed concept relays on a controlled injection of the auxiliary current at the output node where the instantaneous current value is n-1 times bigger than the output capacitor current with appropriate directions. Doing so, the AEP creates an equivalent n times bigger virtual capacitor at the output, thus reducing the output impedance. Due to the fact that the proposed concept reduces the output impedance using the AEP, it has been named the Output Impedance Correction Circuit (OICC) concept. The concept is developed for a multiphase CMC synchronous buck converter (including a single phase implementation), operating with a constant output voltage and with AVP feature. Further, it is extended to a single phase VMC synchronous buck converter. During the operation, the main converter voltage loop and the OICC subsystem capacitor current loop is constantly closed, increasing the robustness under system tolerances and circuit parasitic and allowing the system to operate with any load-current shape or pattern. According to the proposed control method, the system operates in two states: during the steady-state the system is in the Idle state and the OICC subsystem is deactivated, while during the load-step transient the system is in the Active state and the OICC subsystem is activated in order to reduce the output impedance. The state changes are performed autonomously: the system enters in the Active state by observing the output capacitor current and it returns back to the Idle state when the steady-state operation is detected by observing the state variables. The validation of the OICC concept has been done by applying it to a 30W two phase synchronous buck converter with 140μF output capacitor and with the multiplication factor n equal to 15, generating during the Active state equivalent output capacitor of 2.1mF. The OICC subsystem is implemented as single phase PCMC synchronous buck converter. Comparing the converter operation with and without the OICC the results demonstrate that the 12 times reduction of the output voltage deviation is achieved, for both basic operation and for the AVP operation. Furthermore, the results have been compared to a reference prototype which has the same power stage and a fiscal output capacitor of 2.1mF. The results show that the two systems have the same dynamic behavior. Moreover, an impact on the system losses under the pulsating load and DVS operation has been quantified and it has been demonstrated that the OICC system has improved the system efficiency, considering the losses when the system operates with the pulsating load and the DVS operation. Lastly, the output capacitor of the OICC system is much smaller than the reference design output capacitor, therefore, by applying the OICC concept the power density can be increased. In summary, the main contributions of the thesis are: • The proposed Output Impedance Correction Circuit (OICC) concept, • The system level control based on the used approach to change the states of operation, • The OICC subsystem closed-loop implementation, together with the main converter implementation, • The dynamic losses under the pulsating load and the DVS operation quantification, and • The system robustness on the capacitor impedance variation and consecutive load-steps.

The peculiar electrical response of liquid crystal-carbon nanotube systems as seen by impedance spectroscopy

Conductive nanoparticles, especially elongated ones such as carbon nanotubes, dramatically modify the electrical behavior of liquid crystal cells. These nanoparticles are known to reorient with liquid crystals in electric fields, causing significant variations of conductivity at minute concentrations of tens or hundreds ppm. The above notwithstanding, impedance spectroscopy of doped cells in the frequency range customarily employed by liquid crystal devices, 100 Hz?10 kHz, shows a relatively simple resistor/capacitor response where the components of the cell can be univocally assigned to single components of the electrical equivalent circuit. However, widening the frequency range up to 1 MHz or beyond reveals a complex behavior that cannot be explained with the same simple EEC. Moreover, the system impedance varies with the application of electric fields, their effect remaining after removing the field. Carbon nanotubes are reoriented together with liquid crystal reorientation when applying voltage, but barely reoriented back upon liquid crystal relaxation once the voltage is removed. Results demonstrate a remarkable variation in the impedance of the dielectric blend formed by liquid crystal and carbon nanotubes, the irreversible orientation of the carbon nanotubes and possible permanent contacts between electrodes.

Heterojunction Band Offset Limitations on Open-Circuit Voltage in p-ZnTe/n-ZnSe Solar Cells

Limitations on the open-circuit voltage of p-ZnTe/n-ZnSe heterojunction solar cells are studied via current-voltage (I-V) measurements under solar concentration and at variable temperature. The open-circuit voltage reaches a maximum value of 1.95 V at 77 K and 199 suns. The open-circuit voltage shows good agreement with the calculated built-in potential of 2.00 V at 77 K. These results suggest that the open-circuit voltage is limited by heterojunction band offsets associated with the type-II heterojunction band lineup, rather than the bandgap energy of the ZnTe absorber material.

Outward Rectification of Voltage-Gated K+ Channels Evolved at Least Twice in Life History

Voltage-gated potassium (K+) channels are present in all living systems. Despite high structural similarities in the transmembrane domains (TMD), this K+ channel type segregates into at least two main functional categories—hyperpolarization-activated, inward-rectifying (Kin) and depolarization-activated, outward-rectifying (Kout) channels. Voltage-gated K+ channels sense the membrane voltage via a voltage-sensing domain that is connected to the conduction pathway of the channel. It has been shown that the voltage-sensing mechanism is the same in Kin and Kout channels, but its performance results in opposite pore conformations. It is not known how the different coupling of voltage-sensor and pore is implemented. Here, we studied sequence and structural data of voltage-gated K+ channels from animals and plants with emphasis on the property of opposite rectification. We identified structural hotspots that alone allow already the distinction between Kin and Kout channels. Among them is a loop between TMD S5 and the pore that is very short in animal Kout, longer in plant and animal Kin and the longest in plant Kout channels. In combination with further structural and phylogenetic analyses this finding suggests that outward-rectification evolved twice and independently in the animal and plant kingdom.

Molecular basis of fast inactivation in voltage and Ca2+-activated K+ channels: A transmembrane β-subunit homolog

Voltage-dependent and calcium-sensitive K+ (MaxiK) channels are key regulators of neuronal excitability, secretion, and vascular tone because of their ability to sense transmembrane voltage and intracellular Ca2+. In most tissues, their stimulation results in a noninactivating hyperpolarizing K+ current that reduces excitability. In addition to noninactivating MaxiK currents, an inactivating MaxiK channel phenotype is found in cells like chromaffin cells and hippocampal neurons. The molecular determinants underlying inactivating MaxiK channels remain unknown. Herein, we report a transmembrane β subunit (β2) that yields inactivating MaxiK currents on coexpression with the pore-forming α subunit of MaxiK channels. Intracellular application of trypsin as well as deletion of 19 N-terminal amino acids of the β2 subunit abolished inactivation of the α subunit. Conversely, fusion of these N-terminal amino acids to the noninactivating smooth muscle β1 subunit leads to an inactivating phenotype of MaxiK channels. Furthermore, addition of a synthetic N-terminal peptide of the β2 subunit causes inactivation of the MaxiK channel α subunit by occluding its K+-conducting pore resembling the inactivation caused by the “ball” peptide in voltage-dependent K+ channels. Thus, the inactivating phenotype of MaxiK channels in native tissues can result from the association with different β subunits.

Membrane voltage initiates Ca2+ waves and potentiates Ca2+ increases with abscisic acid in stomatal guard cells

In higher plants changes and oscillations in cytosolic free Ca2+ concentration ([Ca2+]i) are central to hormonal physiology, including that of abscisic acid (ABA), which signals conditions of water stress and alters ion channel activities in guard cells of higher-plant leaves. Such changes in [Ca2+]i are thought to encode for cellular responses to different stimuli, but their origins and functions are poorly understood. Because transients and oscillations in membrane voltage also occur in guard cells and are elicited by hormones, including ABA, we suspected a coupling of [Ca2+]i to voltage and its interaction with ABA. We recorded [Ca2+]i by Fura2 fluorescence ratio imaging and photometry while bringing membrane voltage under experimental control with a two-electrode voltage clamp in intact Vicia guard cells. Free-running oscillations between voltages near −50 mV and −200 mV were associated with oscillations in [Ca2+]i, and, under voltage clamp, equivalent membrane hyperpolarizations caused [Ca2+]i to increase, often in excess of 1 μM, from resting values near 100 nM. Image analysis showed that the voltage stimulus evoked a wave of high [Ca2+]i that spread centripetally from the peripheral cytoplasm within 5–10 s and relaxed over 40–60 s thereafter. The [Ca2+]i increases showed a voltage threshold near −120 mV and were sensitive to external Ca2+ concentration. Substituting Mn2+ for Ca2+ to quench Fura2 fluorescence showed that membrane hyperpolarization triggered a divalent influx. ABA affected the voltage threshold for the [Ca2+]i rise, its amplitude, and its duration. In turn, membrane voltage determined the ability of ABA to raise [Ca2+]i. These results demonstrate a capacity for voltage to evoke [Ca2+]i increases, they point to a dual interaction with ABA in triggering and propagating [Ca2+]i increases, and they implicate a role for voltage in “conditioning” [Ca2+]i signals that regulate ion channels for stomatal function.

Neuronal coincidence detection by voltage-sensitive electrical synapses

Coincidence detection is important for functions as diverse as Hebbian learning, binaural localization, and visual attention. We show here that extremely precise coincidence detection is a natural consequence of the normal function of rectifying electrical synapses. Such synapses open to bidirectional current flow when presynaptic cells depolarize relative to their postsynaptic targets and remain open until well after completion of presynaptic spikes. When multiple input neurons fire simultaneously, the synaptic currents sum effectively and produce a large excitatory postsynaptic potential. However, when some inputs are delayed relative to the rest, their contributions are reduced because the early excitatory postsynaptic potential retards the opening of additional voltage-sensitive synapses, and the late synaptic currents are shunted by already opened junctions. These mechanisms account for the ability of the lateral giant neurons of crayfish to sum synchronous inputs, but not inputs separated by only 100 μsec. This coincidence detection enables crayfish to produce reflex escape responses only to very abrupt mechanical stimuli. In light of recent evidence that electrical synapses are common in the mammalian central nervous system, the mechanisms of coincidence detection described here may be widely used in many systems.

Voltage dependence of the pattern and frequency of discrete Ca2+ release events after brief repriming in frog skeletal muscle

Applying a brief repolarizing pre-pulse to a depolarized frog skeletal muscle fiber restores a small fraction of the transverse tubule membrane voltage sensors from the inactivated state. During a subsequent depolarizing test pulse we detected brief, highly localized elevations of myoplasmic Ca2+ concentration (Ca2+ “sparks”) initiated by restored voltage sensors in individual triads at all test pulse voltages. The latency histogram of these events gives the gating pattern of the sarcoplasmic reticulum (SR) calcium release channels controlled by the restored voltage sensors. Both event frequency and clustering of events near the start of the test pulse increase with test pulse depolarization. The macroscopic SR calcium release waveform, obtained from the spark latency histogram and the estimated open time of the channel or channels underlying a spark, exhibits an early peak and rapid marked decline during large depolarizations. For smaller depolarizations, the release waveform exhibits a smaller peak and a slower decline. However, the mean use time and mean amplitude of the individual sparks are quite similar at all test depolarizations and at all times during a given depolarization, indicating that the channel open times and conductances underlying sparks are essentially independent of voltage. Thus, the voltage dependence of SR Ca2+ release is due to changes in the frequency and pattern of occurrence of individual, voltage-independent, discrete release events.

Patch-clamp and amperometric recordings from norepinephrine transporters: Channel activity and voltage-dependent uptake

Transporters for the biogenic amines dopamine, norepinephrine, epinephrine and serotonin are largely responsible for transmitter inactivation after release. They also serve as high-affinity targets for a number of clinically relevant psychoactive agents, including antidepressants, cocaine, and amphetamines. Despite their prominent role in neurotransmitter inactivation and drug responses, we lack a clear understanding of the permeation pathway or regulation mechanisms at the single transporter level. The resolution of radiotracer-based flux techniques limits the opportunities to dissect these problems. Here we combine patch-clamp recording techniques with microamperometry to record the transporter-mediated flux of norepinephrine across isolated membrane patches. These data reveal voltage-dependent norepinephrine flux that correlates temporally with antidepressant-sensitive transporter currents in the same patch. Furthermore, we resolve unitary flux events linked with bursts of transporter channel openings. These findings indicate that norepinephrine transporters are capable of transporting neurotransmitter across the membrane in discrete shots containing hundreds of molecules. Amperometry is used widely to study neurotransmitter distribution and kinetics in the nervous system and to detect transmitter release during vesicular exocytosis. Of interest regarding the present application is the use of amperometry on inside-out patches with synchronous recording of flux and current. Thus, our results further demonstrate a powerful method to assess transporter function and regulation.

Ceramide-induced inhibition of T lymphocyte voltage-gated potassium channel is mediated by tyrosine kinases

The n-type K+ channel (n-K+, Kv1.3) in lymphocytes has been recently implicated in the regulation of Fas-induced programmed cell death. Here, we demonstrate that ceramide, a lipid metabolite synthesized upon Fas receptor ligation, inhibits n-K+ channel activity and induces a tyrosine phosphorylation of the Kv1.3 protein in Jurkat T lymphocytes. Tyrosine phosphorylation of the n-K+ channel correlated with an activation of the Src-like tyrosine kinase p56lck upon cellular treatment with the ceramide analog C6-ceramide. Because genetic deficiency of p56lck or inhibition of Src-like tyrosine kinases by herbimycin A prevented ceramide-mediated n-K+ channel inhibition and tyrosine phosphorylation, we propose a ceramide-initiated activation of p56lck resulting in tyrosine phosphorylation and inhibition of the n-K+ channel protein.

Two functionally distinct subsites for the binding of internal blockers to the pore of voltage-activated K+ channels

Many blockers of Na+ and K+ channels act by blocking the pore from the intracellular side. For Shaker K+ channels, such intracellular blockers vary in their functional effect on slow (C-type) inactivation: Some blockers interfere with C-type inactivation, whereas others do not. These functional differences can be explained by supposing that there are two overlapping “subsites” for blocker binding, only one of which inhibits C-type inactivation through an allosteric effect. We find that the ability to bind to these subsites depends on specific structural characteristics of the blockers, and correlates with the effect of mutations in two distinct regions of the channel protein. These interactions are important because they affect the ability of blockers to produce use-dependent inhibition.

Evidence for a voltage-dependent enhancement of neurotransmitter release mediated via the synaptic protein interaction site of N-type Ca2+ channels

Secretion of neurotransmitters is initiated by voltage-gated calcium influx through presynaptic, voltage-gated N-type calcium channels. These channels interact with the SNARE proteins, which are core components of the exocytosis process, via the synaptic protein interaction (synprint) site in the intracellular loop connecting domains II and III of their α1B subunit. Interruption of this interaction by competing synprint peptides inhibits fast, synchronous transmitter release. Here we identify a voltage-dependent, but calcium-independent, enhancement of transmitter release that is elicited by trains of action potentials in the presence of a hyperosmotic extracellular concentration of sucrose. This enhancement of transmitter release requires interaction of SNARE proteins with the synprint site. Our results provide evidence for a voltage-dependent signal that is transmitted by protein–protein interactions from the N-type calcium channel to the SNARE proteins and enhances neurotransmitter release by altering SNARE protein function.

Voltage-induced membrane displacement in patch pipettes activates mechanosensitive channels

The patch-clamp technique allows currents to be recorded through single ion channels in patches of cell membrane in the tips of glass pipettes. When recording, voltage is typically applied across the membrane patch to drive ions through open channels and to probe the voltage-sensitivity of channel activity. In this study, we used video microscopy and single-channel recording to show that prolonged depolarization of a membrane patch in borosilicate pipettes results in delayed slow displacement of the membrane into the pipette and that this displacement is associated with the activation of mechanosensitive (MS) channels in the same patch. The membrane displacement, ≈1 μm with each prolonged depolarization, occurs after variable delays ranging from tens of milliseconds to many seconds and is correlated in time with activation of MS channels. Increasing the voltage step shortens both the delay to membrane displacement and the delay to activation. Preventing depolarization-induced membrane displacement by applying positive pressure to the shank of the pipette or by coating the tips of the borosilicate pipettes with soft glass prevents the depolarization-induced activation of MS channels. The correlation between depolarization-induced membrane displacement and activation of MS channels indicates that the membrane displacement is associated with sufficient membrane tension to activate MS channels. Because membrane tension can modulate the activity of various ligand and voltage-activated ion channels as well as some transporters, an apparent voltage dependence of a channel or transporter in a membrane patch in a borosilicate pipette may result from voltage-induced tension rather than from direct modulation by voltage.