A silicon-on-insulator-based thermo-optic waveguide switch with low insertion loss and fast response

A silicon-on-insulator-based thermo-optic waveguide switch integrated with spot size converters is designed and fabricated by inductively coupled plasma reactive ion etching. The device shows good characteristics, including low, insertion loss of 8 +/- 1 dB for wavelength 1530-1580 nm and fast response times of 4.6 As for rising edge and 1.9 mu s for failing edge. The extinction ratios of the two channels are 19.1 and 18 dB, respectively.

Mode analysis and Q-factor enhancement due to mode coupling in rectangular resonators

Modes in rectangular resonators are analyzed and classified according to symmetry properties, and quality factor (Q-factor) enhancement due to mode coupling is observed. In the analysis, mode numbers p and q are used to denote the number of wave nodes in the direction of two orthogonal sides. The even and odd mode numbers correspond to symmetric and antisymmetric field distribution relative to the midlines of sides, respectively. Thus, the modes in a rectangle resonator can be divided into four classes according to the parity of p and q. Mode coupling between modes of different classes is forbidden; however, anti-crossing mode coupling between the modes in the same class exists and results in new modes due to the combination of the coupled modes. One of the combined modes has very low power loss and high Q-factor based on far-field emission of the analytical field distribution, which agrees well with the numerical results of the finite-difference time-domain (FDTD) simulation. Both the analytical and FDTD results show that the Q-factors of the high Q-factor combined modes are over one order larger than those of the original modes. Furthermore, the general condition required to achieve high-Q modes in the rectangular resonator is given based on the analytical solution.

A voltage-adjustable three-phase rectifier with constant power flow

An three phase adjustable output voltage rectifier with constant power flow based on waveform gap patching principle is resented. By patching the gapes in the phase currents in parallel way as well as the ripple of the output voltage in series way, it implements the constant power flow from the three-phase line to the DC output without using any line frequency (and its harmonics) energy storage components. Principally, by treating only 22.4% power of the needed power output, this rectifier can supply constant power flow with adjustable output voltages without bring about any harmonic interferences to the power utility and achieve unite power factor.

A 5.6-mW Power Dissipation CMOS Frequency Synthesizer for L1/L2 Dual-Band GPS Application

This paper presents a wide tuning range CMOS frequency synthesizer for dual-band GPS receiver, which has been fabricated in a standard 0.18-um RF CMOS process. With a high Q on-chip inductor, the wide-band VCO shows a tuning range from 2 to 3.6GHz to cover 2.45GHz and 3.14GHz in case of process corner or temperature variation, with a current consumption varying accordingly from 0.8mA to 0.4mA, from a 1.8V supply voltage. The measurement results show that the whole frequency synthesizer costs a very low power consumption of 5.6mW working at L I band with in-band phase noise less than -82dBc/Hz and out-of-band phase noise about -112 dBc/Hz at 1MHz offset from a 3.142GHz carrier.

Low threshold current density, low resistance oxide-confined VCSEL fabricated by a dielectric-free approach

We present the fabrication process and experimental results of 850-nm oxide-confined vertical cavity surface emitting lasers (VCSELs) fabricated by using dielectric-free approach. The threshold current of 0.4 mA, which corresponds to the threshold current density of 0.5 kA/cm(2), differential resistance of 76 Omega, and maximum output power of more than 5 mW are achieved for the dielectric-free VCSEL with a square oxide aperture size of 9 mu m at room temperature (RT). L-I-V characteristics of the dielectric-free VCSEL are compared with those of conventional VCSEL with the similar aperture size, which indicates the way to realize low-cost, low-power consumption VCSELs with extremely simple process. Preliminary study of the temperature-dependent L-I characteristics and modulation response of the dielectric-free VCSEL are also presented.

A Novel Power Supply Solution of a Passive RFID Transponder

This paper presents a power supply solution for fully integrated passive radio-frequency identification(RFID) transponder IC,which has been implemented in 0.35μm CMOS technology with embedded EEPROM from Chartered Semiconductor.The proposed AC/DC and DC/DC charge pumps can generate stable output for RFID applications with quite low power dissipation and extremely high pumping efficiency.An analytical model of the voltage multiplier,comparison with other charge pumps,simulation results,and chip testing results are presented.

Realization of negative differential resistance and switching devices based on copper phthalocyanine by the control of evaporation rate

We have observed, respectively, a negative differential resistance (NDR) and switching conduction in current-voltage (I-V) characteristics of organic diodes based on copper phthalocyanine (CuPc) film sandwiched between indium-tin-oxide (ITO) and aluminum (Al) by controlling the evaporation rate. The NDR effect is repeatable which can be well, controlled by sweep rate and start voltage, and the switching exhibits write-once-read-many-times (WORM) memory characteristics. The traps in the organic layer and interfacial dipole have been used to explain the NDR effect and switching conduction. This opens up potential applications for CuPc organic semiconductor in low power memory and logic circuits.

Practical wireless sensor networks power consumption metrics for building energy management applications

The power consumption of wireless sensor networks (WSN) module is an important practical concern in building energy management (BEM) system deployments. A set of metrics are created to assess the power profiles of WSN in real world condition. The aim of this work is to understand and eventually eliminate the uncertainties in WSN power consumption during long term deployments and the compatibility with existing and emerging energy harvesting technologies. This paper investigates the key metrics in data processing, wireless data transmission, data sensing and duty cycle parameter to understand the system power profile from a practical deployment prospective. Based on the proposed analysis, the impacts of individual metric on power consumption in a typical BEM application are presented and the subsequent low power solutions are investigated.

Systematic delay-driven power optimisation and power-driven delay optimisation of combinational circuits

With the proliferation of mobile wireless communication and embedded systems, the energy efficiency becomes a major design constraint. The dissipated energy is often referred as the product of power dissipation and the input-output delay. Most of electronic design automation techniques focus on optimising only one of these parameters either power or delay. Industry standard design flows integrate systematic methods of optimising either area or timing while for power consumption optimisation one often employs heuristics which are characteristic to a specific design. In this work we answer three questions in our quest to provide a systematic approach to joint power and delay Optimisation. The first question of our research is: How to build a design flow which incorporates academic and industry standard design flows for power optimisation? To address this question, we use a reference design flow provided by Synopsys and integrate in this flow academic tools and methodologies. The proposed design flow is used as a platform for analysing some novel algorithms and methodologies for optimisation in the context of digital circuits. The second question we answer is: Is possible to apply a systematic approach for power optimisation in the context of combinational digital circuits? The starting point is a selection of a suitable data structure which can easily incorporate information about delay, power, area and which then allows optimisation algorithms to be applied. In particular we address the implications of a systematic power optimisation methodologies and the potential degradation of other (often conflicting) parameters such as area or the delay of implementation. Finally, the third question which this thesis attempts to answer is: Is there a systematic approach for multi-objective optimisation of delay and power? A delay-driven power and power-driven delay optimisation is proposed in order to have balanced delay and power values. This implies that each power optimisation step is not only constrained by the decrease in power but also the increase in delay. Similarly, each delay optimisation step is not only governed with the decrease in delay but also the increase in power. The goal is to obtain multi-objective optimisation of digital circuits where the two conflicting objectives are power and delay. The logic synthesis and optimisation methodology is based on AND-Inverter Graphs (AIGs) which represent the functionality of the circuit. The switching activities and arrival times of circuit nodes are annotated onto an AND-Inverter Graph under the zero and a non-zero-delay model. We introduce then several reordering rules which are applied on the AIG nodes to minimise switching power or longest path delay of the circuit at the pre-technology mapping level. The academic Electronic Design Automation (EDA) tool ABC is used for the manipulation of AND-Inverter Graphs. We have implemented various combinatorial optimisation algorithms often used in Electronic Design Automation such as Simulated Annealing and Uniform Cost Search Algorithm. Simulated Annealing (SMA) is a probabilistic meta heuristic for the global optimization problem of locating a good approximation to the global optimum of a given function in a large search space. We used SMA to probabilistically decide between moving from one optimised solution to another such that the dynamic power is optimised under given delay constraints and the delay is optimised under given power constraints. A good approximation to the global optimum solution of energy constraint is obtained. Uniform Cost Search (UCS) is a tree search algorithm used for traversing or searching a weighted tree, tree structure, or graph. We have used Uniform Cost Search Algorithm to search within the AIG network, a specific AIG node order for the reordering rules application. After the reordering rules application, the AIG network is mapped to an AIG netlist using specific library cells. Our approach combines network re-structuring, AIG nodes reordering, dynamic power and longest path delay estimation and optimisation and finally technology mapping to an AIG netlist. A set of MCNC Benchmark circuits and large combinational circuits up to 100,000 gates have been used to validate our methodology. Comparisons for power and delay optimisation are made with the best synthesis scripts used in ABC. Reduction of 23% in power and 15% in delay with minimal overhead is achieved, compared to the best known ABC results. Also, our approach is also implemented on a number of processors with combinational and sequential components and significant savings are achieved.

Research and design of high-speed advanced analogue front-ends for fibre-optic transmission systems

In the last decade, we have witnessed the emergence of large, warehouse-scale data centres which have enabled new internet-based software applications such as cloud computing, search engines, social media, e-government etc. Such data centres consist of large collections of servers interconnected using short-reach (reach up to a few hundred meters) optical interconnect. Today, transceivers for these applications achieve up to 100Gb/s by multiplexing 10x 10Gb/s or 4x 25Gb/s channels. In the near future however, data centre operators have expressed a need for optical links which can support 400Gb/s up to 1Tb/s. The crucial challenge is to achieve this in the same footprint (same transceiver module) and with similar power consumption as today’s technology. Straightforward scaling of the currently used space or wavelength division multiplexing may be difficult to achieve: indeed a 1Tb/s transceiver would require integration of 40 VCSELs (vertical cavity surface emitting laser diode, widely used for short‐reach optical interconnect), 40 photodiodes and the electronics operating at 25Gb/s in the same module as today’s 100Gb/s transceiver. Pushing the bit rate on such links beyond today’s commercially available 100Gb/s/fibre will require new generations of VCSELs and their driver and receiver electronics. This work looks into a number of state‐of-the-art technologies and investigates their performance restraints and recommends different set of designs, specifically targeting multilevel modulation formats. Several methods to extend the bandwidth using deep submicron (65nm and 28nm) CMOS technology are explored in this work, while also maintaining a focus upon reducing power consumption and chip area. The techniques used were pre-emphasis in rising and falling edges of the signal and bandwidth extensions by inductive peaking and different local feedback techniques. These techniques have been applied to a transmitter and receiver developed for advanced modulation formats such as PAM-4 (4 level pulse amplitude modulation). Such modulation format can increase the throughput per individual channel, which helps to overcome the challenges mentioned above to realize 400Gb/s to 1Tb/s transceivers.

Networking protocols for long life wireless sensor networks

My original contribution to knowledge is the creation of a WSN system that further improves the functionality of existing technology, whilst achieving improved power consumption and reliability. This thesis concerns the development of industrially applicable wireless sensor networks that are low-power, reliable and latency aware. This work aims to improve upon the state of the art in networking protocols for low-rate multi-hop wireless sensor networks. Presented is an application-driven co-design approach to the development of such a system. Starting with the physical layer, hardware was designed to meet industry specified requirements. The end system required further investigation of communications protocols that could achieve the derived application-level system performance specifications. A CSMA/TDMA hybrid MAC protocol was developed, leveraging numerous techniques from the literature and novel optimisations. It extends the current art with respect to power consumption for radio duty-cycled applications, and reliability, in dense wireless sensor networks, whilst respecting latency bounds. Specifically, it provides 100% packet delivery for 11 concurrent senders transmitting towards a single radio duty cycled sink-node. This is representative of an order of magnitude improvement over the comparable art, considering MAC-only mechanisms. A novel latency-aware routing protocol was developed to exploit the developed hardware and MAC protocol. It is based on a new weighted objective function with multiple fail safe mechanisms to ensure extremely high reliability and robustness. The system was empirically evaluated on two hardware platforms. These are the application-specific custom 868 MHz node and the de facto community-standard TelosB. Extensive empirical comparative performance analyses were conducted against the relevant art to demonstrate the advances made. The resultant system is capable of exceeding 10-year battery life, and exhibits reliability performance in excess of 99.9%.

Reliability of power electronic modules

The electric car, the all electric aircraft and requirements for renewable energy are examples of potential technologies needed to address the world problem of global warming/carbon emission etc. Power electronics and packaged modules are fundamental for the underpinning of these technologies and with the diverse requirements for electrical configurations and the range of environmental conditions, time to market is paramount for module manufacturers and systems designers alike. This paper details some of the results from a major UK project into the reliability of power electronic modules using physics of failure techniques. This paper presents a design methodology together with results that demonstrate enhanced product design with improved reliability, performance and value within acceptable time scales

Open ended microwave oven for flip-chip assembly

A novel open-ended waveguide cavity resonator for the microwave curing of bumps, underfills and encapsulants is described. The open oven has the potential to provide fast alignment of devices during flip-chip assembly, direct chip attach, surface mount assembly or wafer-scale level packaging. The prototype microwave oven was designed to operate at X-band for ease of testing, although a higher frequency version is planned. The device described in the paper takes the form of a waveguide cavity resonator. It is approximately square in cross-section and is filled with a low-loss dielectric with a relative permittivity of 6. It is excited by end-fed probes in order to couple power preferentially into the TM3,3,k mode with the object of forming nine 'hot-spots' in the open end. Low power tests using heat sensitive film demonstrate clearly that selective heating in multiple locations in the open end of the oven is achievable

Predicting the reliability of power electronic modules

This paper discusses the reliability of an IGBT power electronics module. This work is part of a major UK funded initiative into the design, packaging and reliability of power electronic modules. The predictive methodology combines numerical modeling techniques with experimentation and accelerated testing to identify failure modes and mechanisms for these type of power electronic module structures. The paper details results for solder joint failure substrate solder. Finite element method modeling techniques have been used to predict the stress and strain distribution within the module structures. Together with accelerated life testing, these results have provided a failure model for these joints which has been used to predict reliability of a rail traction application

Integrated reliability and prognostics prediction methodology for power electronic modules

The article consists of a PowerPoint presentation on integrated reliability and prognostics prediction methodology for power electronic modules. The areas discussed include: power electronics flagship; design for reliability; IGBT module; design for manufacture; power module components; reliability prediction techniques; failure based reliability; etc.