A study of partial discharge characteristics in oil impregnated pressboard insulation

An attempt has been made to study the effect of time and test procedure on the behaviour of partial discharge (PD) pulses causing failure of oil-pressboard system under power frequency voltages using circular disc shaped samples and uniform field electrodes. Weibull statistics have been used to handle the large amount of PD data. The PD phenomena has been found to be stress and time dependent. On the basis of stress level, three different regions are identified and in one of the regions, the rate of deterioration of the sample is at a maximum. The work presents some interesting features of Weibull parameters as related to the condition of insulation studied in addition to its usual PD characteristics

Spatial distribution of oil in groundnut and sunflower seeds by nuclear magnetic resonance imaging

The nuclear magnetic resonance imaging technique has been used to obtain images of different transverse and vertical sections in groundnut and sunflower seeds. Separate images have been obtained for oil and water components in the seeds. The spatial distribution of oil and water inside the seed has been obtained from the detailed analysis of the images. In the immature groundnut seeds obtained commercially, complementary oil and water distributions have been observed. Attempts have been made to explain these results.

Purification and partial characterization of acyl carrier proteins from developing oil seeds of pisa (Actinodaphne hookeri) and ground nut (Arachis hypogaea)

Acyl carrier proteins (ACP) were purified to homogeneity in the active form from developing seeds of pisa (Actinodaphne hookeri) which synthesizes exclusively trilaurin and from ground nut (Arachis hypogaea) which synthesizes triacylglycerols containing long chain fatty acids. Two major isoforms of ACPs were purified from developing pisa seeds using DEAE-cellulose, Superose-6 FPLC and C-4 reversed phase HPLC chromatographic methods. In contrast, only a single form of ACP was present in ground nut seeds which was purified by anion-exchange and activated thiol-Sepharose 4B affinity chromatography. The two isoforms of ACPs from pisa showed nearly the same specific activity of 6,706 and 7,175 pmol per min per mg protein while ground nut ACP showed a specific activity of 3,893 pmol per min per mg protein when assayed using E. coli acyl-ACP synthetase and [1-C-14]palmitic acid. When compared with E. coli ACP, the purified ACPs from both the seeds showed considerable difference in their mobility in native PAGE, but showed similar mobility in SDS-PAGE under reducing conditions. In the absence of reducing agents formation of dimers was quite prominent. The ACPs from both the seed sources were acid- and heat-stable. The major isoform of pisa seed ACP and the ground nut ACP contain 91 amino acids with M(r) 11,616 and 1,228 respectively. However, there is significant variation in their amino acid composition. A comparision of the amino acid sequence in the N-terminal region of pisa and ground nut seed ACPs showed considerable homology between themselves and with other plant ACPs but not with E. coli ACP.

GC-MS study of Artabotrys odoratissimus fatty oil (leaves)

GC-MS study of two fatty oil fractions from Artabotrys odoratissimus (leaves) indicated the presence of fifteen compounds namely, nonanoic acid; methyl phenyl propanoate; decanoic acid; diethyl phthalate; dibutyl phthalate; 2 - amino-3-ethyl biphenyl; 5-methyl-9-phenylnonan-3-ol; hexadeca-2,7,11-triene; 2,6-dimethyl-1-phenylhepta-1-one; 2,5-dimethyltetradecahydrophenenthrene; 1-phenylundecane; 1-isopropyl-4,6-dimethyl naphthalene; 5-(2-butyl phenyl)pent-3-en-2-ol; 1-phenyideca-1-one and 1-phenylundecan-1-one. Some of the compounds are rare occurring and biologically active.

Lubricity of an oil in water emulsion in metal cutting: The effect of hydrophilic/lypophilic balance of emulsifiers

A steel disc is cut using a single point tool. The coefficient of friction of the nascent cut surface is measured by a spherical steel pin situated in close proximity of the point of cutting. The tool, disc and the friction pin are immersed in an oil in water emulsion bath during the experiment. The purpose of the experiments conducted here is to record the effect of hydrophilic/lypophilic balance (HLB) of the emulsifier on the lubricity experienced in the cutting operation. The more lypophilic emulsifiers were found to give greater lubricity than what is recorded when the emulsifier is more hydrophilic. XPS and FTIR spectroscopy are used to explore the tribofilm generated on the nascent cut surface to indicate a possible rationale for the effect. (C) 2011 Elsevier B.V. All rights reserved.

Synthesis, characterization, degradation of biodegradable castor oil based polyesters

A new family of castor oil based biodegradable polyesters was synthesized by catalyst free melt condensation reaction between two different diacids and castor oil with D-mannitol. The polymers synthesized were characterized by NMR spectroscopy, FF-IR and the thermal properties were analysed by DSC. The results of DSC show that the polymer is rubbery in physiological conditions. The contact angle measurement and hydration test results indicate that the surface of the polymer is hydrophilic. The mechanical properties, evaluated in the tensile mode, shows that the polymer has characteristics of a soft material. In vitro degradation of polymer in PBS solution carried out at physiological conditions indicates that the degradation goes to completion within 21 days and it was also found that the rate of degradation can be tuned by varying the curing conditions. (C) 2011 Elsevier Ltd. All rights reserved.

A System-C based Micro architectural Exploration Framework for Latency, Power and Performance Trade-offs of On-Chip Interconnection

We describe a System-C based framework we are developing, to explore the impact of various architectural and microarchitectural level parameters of the on-chip interconnection network elements on its power and performance. The framework enables one to choose from a variety of architectural options like topology, routing policy, etc., as well as allows experimentation with various microarchitectural options for the individual links like length, wire width, pitch, pipelining, supply voltage and frequency. The framework also supports a flexible traffic generation and communication model. We provide preliminary results of using this framework to study the power, latency and throughput of a 4x4 multi-core processing array using mesh, torus and folded torus, for two different communication patterns of dense and sparse linear algebra. The traffic consists of both Request-Response messages (mimicing cache accesses)and One-Way messages. We find that the average latency can be reduced by increasing the pipeline depth, as it enables higher link frequencies. We also find that there exists an optimum degree of pipelining which minimizes energy-delay product.

Memory Architecture Exploration Framework for Cache Based Embedded SoC

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences critical system design objectives like area, power and performance. Hence the embedded system designer performs a complete memory architecture exploration to custom design a memory architecture for a given set of applications. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of exhaustive-search based memory exploration at the outer level and a two step based integrated data layout for SPRAM-Cache based architectures at the inner level. We present a two step integrated approach for data layout for SPRAM-Cache based hybrid architectures with the first step as data-partitioning that partitions data between SPRAM and Cache, and the second step is the cache conscious data layout. We formulate the cache-conscious data layout as a graph partitioning problem and show that our approach gives up to 34% improvement over an existing approach and also optimizes the off-chip memory address space. We experimented our approach with 3 embedded multimedia applications and our approach explores several hundred memory configurations for each application, yielding several optimal design points in a few hours of computation on a standard desktop.

Streaming FFT on REDEFINE-v2: An Application-Architecture Design Space Exploration

In this paper we explore an implementation of a high-throughput, streaming application on REDEFINE-v2, which is an enhancement of REDEFINE. REDEFINE is a polymorphic ASIC combining the flexibility of a programmable solution with the execution speed of an ASIC. In REDEFINE Compute Elements are arranged in an 8x8 grid connected via a Network on Chip (NoC) called RECONNECT, to realize the various macrofunctional blocks of an equivalent ASIC. For a 1024-FFT we carry out an application-architecture design space exploration by examining the various characterizations of Compute Elements in terms of the size of the instruction store. We further study the impact by using application specific, vectorized FUs. By setting up different partitions of the FFT algorithm for persistent execution on REDEFINE-v2, we derive the benefits of setting up pipelined execution for higher performance. The impact of the REDEFINE-v2 micro-architecture for any arbitrary N-point FFT (N > 4096) FFT is also analyzed. We report the various algorithm-architecture tradeoffs in terms of area and execution speed with that of an ASIC implementation. In addition we compare the performance gain with respect to a GPP.

MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip

The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded DSP is complex and usually custom designed with multiple banks of single-ported or dual ported on-chip scratch pad memory and multiple banks of off-chip memory. Building software for such large complex memories with many of the software components as individually optimized software IPs is a big challenge. In order to obtain good performance and a reduction in memory stalls, the data buffers of the application need to be placed carefully in different types of memory. In this paper we present a unified framework (MODLEX) that combines different data layout optimizations to address the complex DSP memory architectures. Our method models the data layout problem as multi-objective genetic algorithm (GA) with performance and power being the objectives and presents a set of solution points which is attractive from a platform design viewpoint. While most of the work in the literature assumes that performance and power are non-conflicting objectives, our work demonstrates that there is significant trade-off (up to 70%) that is possible between power and performance.

MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences these parameters. Hence the embedded system designer performs a complete memory architecture exploration. This problem is a multi-objective optimization problem and can be tackled as a two-level optimization problem. The outer level explores various memory architecture while the inner level explores placement of data sections (data layout problem) to minimize memory stalls. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of Multi-objective Genetic Algorithm (Memory Architecture exploration) and an efficient heuristic data placement algorithm. At the outer level the memory architecture exploration is done by picking memory modules directly from a ASIC memory Library. This helps in performing the memory architecture exploration in a integrated framework, where the memory allocation, memory exploration and data layout works in a tightly coupled way to yield optimal design points with respect to area, power and performance. We experimented our approach for 3 embedded applications and our approach explores several thousand memory architecture for each application, yielding a few hundred optimal design points in a few hours of computation time on a standard desktop.

Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform

In the world of high performance computing huge efforts have been put to accelerate Numerical Linear Algebra (NLA) kernels like QR Decomposition (QRD) with the added advantage of reconfigurability and scalability. While popular custom hardware solution in form of systolic arrays can deliver high performance, they are not scalable, and hence not commercially viable. In this paper, we show how systolic solutions of QRD can be realized efficiently on REDEFINE, a scalable runtime reconfigurable hardware platform. We propose various enhancements to REDEFINE to meet the custom need of accelerating NLA kernels. We further do the design space exploration of the proposed solution for any arbitrary application of size n × n. We determine the right size of the sub-array in accordance with the optimal pipeline depth of the core execution units and the number of such units to be used per sub-array.