Force ripple compensation in a tubular linear generator for marine renewable generation

Tubular permanent magnet linear generators are a promising generator technology for use in marine renewables. One aspect of their design relates to the conditions necessary for achieving a smooth thrust response from the generator, free from cogging and periodic variations due to spatial harmonics of the flux cutting the generator coils. This paper presents an experimental and finite element study of the sources of thrust ripple in a prototype linear generator for marine generation. A simple self-commutated control scheme is shown, which uses linear Hall-effect sensors and look-up-table based feed-forward compensation to derive the excitation currents required to drive the machine with constant force. Details of the controller's FPGA based implementation are given, including its strategy for detecting sensor failure. © 2011 IEEE.

Channel-hopping model predictive control

In Multiplexed MPC, the control variables of a MIMO plant are moved asynchronously, following a pre-planned periodic sequence. The advantage of Multiplexed MPC lies in its reduced computational complexity, leading to faster response to disturbances, which may result in improved performance, despite finding sub-optimal solution to the original problem. This paper extends the original Multiplexed MPC in a way such that the control inputs are no longer restricted to a pre-planned periodic sequence. Instead, the most appropriate control input channel would be optimised and selected to counter the disturbances, hence the name 'Channel-Hopping'. In addition, the proposed algorithm is suitable for execution on modern computing platforms such as FPGA or GPU, exploits multi-core, parallel and pipeline computing techniques. The algorithm for the proposed Channel-hopping MPC (CH-MPC) will be described and its stability established. Illustrative examples are given to demonstrate the behaviour of the proposed Channel-Hopping MPC algorithm. © 2011 IFAC.

Heterogeneous reconfigurable system for adaptive particle filters in real-time applications

This paper presents a heterogeneous reconfigurable system for real-time applications applying particle filters. The system consists of an FPGA and a multi-threaded CPU. We propose a method to adapt the number of particles dynamically and utilise the run-time reconfigurability of the FPGA for reduced power and energy consumption. An application is developed which involves simultaneous mobile robot localisation and people tracking. It shows that the proposed adaptive particle filter can reduce up to 99% of computation time. Using run-time reconfiguration, we achieve 34% reduction in idle power and save 26-34% of system energy. Our proposed system is up to 7.39 times faster and 3.65 times more energy efficient than the Intel Xeon X5650 CPU with 12 threads, and 1.3 times faster and 2.13 times more energy efficient than an NVIDIA Tesla C2070 GPU. © 2013 Springer-Verlag.

FEC-free 50 m 1.5 Gb/s plastic optical fibre link using CAP modulation for home networks

LED-based carrierless amplitude and phase modulation is investigated for a multi-gigabit plastic optical fibre link. An FPGA-based 1.5 Gbit/s error free transmission over 50 m standard SI-POF using CAP64 is achieved, providing 2.9 dB power margin without forward error correction. © 2012 OSA.

FEC-free 50 m 1.5 Gb/s plastic optical fibre link using CAP modulation for home networks

LED-based carrierless amplitude and phase modulation is investigated for a multi-gigabit plastic optical fibre link. An FPGA-based 1.5 Gbit/s error free transmission over 50 m standard SI-POF using CAP64 is achieved, providing 2.9 dB power margin without forward error correction. © 2012 Optical Society of America.

Field programmable gate array based predictive control system for spacecraft rendezvous in elliptical orbits

Copyright © 2014 John Wiley & Sons, Ltd. Copyright © 2014 John Wiley & Sons, Ltd. Summary A field programmable gate array (FPGA) based model predictive controller for two phases of spacecraft rendezvous is presented. Linear time-varying prediction models are used to accommodate elliptical orbits, and a variable prediction horizon is used to facilitate finite time completion of the longer range manoeuvres, whilst a fixed and receding prediction horizon is used for fine-grained tracking at close range. The resulting constrained optimisation problems are solved using a primal-dual interior point algorithm. The majority of the computational demand is in solving a system of simultaneous linear equations at each iteration of this algorithm. To accelerate these operations, a custom circuit is implemented, using a combination of Mathworks HDL Coder and Xilinx System Generator for DSP, and used as a peripheral to a MicroBlaze soft-core processor on the FPGA, on which the remainder of the system is implemented. Certain logic that can be hard-coded for fixed sized problems is implemented to be configurable online, in order to accommodate the varying problem sizes associated with the variable prediction horizon. The system is demonstrated in closed-loop by linking the FPGA with a simulation of the spacecraft dynamics running in Simulink on a PC, using Ethernet. Timing comparisons indicate that the custom implementation is substantially faster than pure embedded software-based interior point methods running on the same MicroBlaze and could be competitive with a pure custom hardware implementation.

针对多模式逻辑单元可编程门阵列的工艺映射方法

本发明公开了一种针对多模式逻辑单元可编程门阵列的工艺映射方法，该方法包括映射和合并两个步骤，首先对输入的与具体工艺无关的门级电路网表进行解析，并对解析的结果进行工艺映射，然后再根据多模式LC的约束信息对工艺映射结果进行合并处理，计算出多模式LC的模式配置值，得到最终优化的工艺相关的电路网表。利用本发明，解决了多模式逻辑单元结构FPGA的工艺映射问题，充分利用了基于两个LUT3的LC结构的优势。

一种可重构的乘法器

本发明公开了一种可重构的乘法器，包括:输入单元，用于将乘数和被乘数分别输出至部分积产生单元;部分积产生单元，用于对接收自输入单元的乘数和被乘数的每一位进行操作产生一个部分积，并输出给部分积压缩单元;部分积压缩单元，用于对部分积产生单元输入的部分积进行进位保留加法器累加压缩，得到一排和信号以及一排进位信号，输出给最终积合成单元;最终积合成单元，包括一低位超前进位加法器和一高位超前进位加法器，用于对接收自部分积压缩单元的一排和信号以及一排进位信号进行合并而产生积，并输出给输出单元;输出单元，用于将接收自最终积合成单元的积采用异步操作或同步操作方式进行输出。本发明能够大大提高FPGA处理数据运算的速度。

基于神经计算机的高速数据通道设计

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Pipeline Architecture and Parallel Computation-Based Real-Time Stereovision Tracking System for Surgical Navigation

This paper studies the development of a real-time stereovision system to track multiple infrared markers attached to a surgical instrument. Multiple stages of pipeline in field-programmable gate array (FPGA) are developed to recognize the targets in both left and right image planes and to give each target a unique label. The pipeline architecture includes a smoothing filter, an adaptive threshold module, a connected component labeling operation, and a centroid extraction process. A parallel distortion correction method is proposed and implemented in a dual-core DSP. A suitable kinematic model is established for the moving targets, and a novel set of parallel and interactive computation mechanisms is proposed to position and track the targets, which are carried out by a cross-computation method in a dual-core DSP. The proposed tracking system can track the 3-D coordinate, velocity, and acceleration of four infrared markers with a delay of 9.18 ms. Furthermore, it is capable of tracking a maximum of 110 infrared markers without frame dropping at a frame rate of 60 f/s. The accuracy of the proposed system can reach the scale of 0.37 mm RMS along the x- and y-directions and 0.45 mm RMS along the depth direction (the depth is from 0.8 to 0.45 m). The performance of the proposed system can meet the requirements of applications such as surgical navigation, which needs high real time and accuracy capability.

Pipeline Architecture and Parallel Computation-Based Real-Time Stereovision Tracking System for Surgical Navigation

This paper studies the development of a real-time stereovision system to track multiple infrared markers attached to a surgical instrument. Multiple stages of pipeline in field-programmable gate array (FPGA) are developed to recognize the targets in both left and right image planes and to give each target a unique label. The pipeline architecture includes a smoothing filter, an adaptive threshold module, a connected component labeling operation, and a centroid extraction process. A parallel distortion correction method is proposed and implemented in a dual-core DSP. A suitable kinematic model is established for the moving targets, and a novel set of parallel and interactive computation mechanisms is proposed to position and track the targets, which are carried out by a cross-computation method in a dual-core DSP. The proposed tracking system can track the 3-D coordinate, velocity, and acceleration of four infrared markers with a delay of 9.18 ms. Furthermore, it is capable of tracking a maximum of 110 infrared markers without frame dropping at a frame rate of 60 f/s. The accuracy of the proposed system can reach the scale of 0.37 mm RMS along the x- and y-directions and 0.45 mm RMS along the depth direction (the depth is from 0.8 to 0.45 m). The performance of the proposed system can meet the requirements of applications such as surgical navigation, which needs high real time and accuracy capability.

多功能车辆总线网络设备的设计与实现

随着高速列车在全世界范围内的应用日益广泛，列车通信网络成为重要的研究领域。而多功能车辆总线网络设备是列车通信网络的核心技术。传统的基于单片机或基于可编程片上系统的网络设备在实时性、可扩展性和可靠性等方面均存在较大的劣势，现场可编程逻辑门阵列和通用微处理器的组合为克服这一困难提供了新的解决方案。现场可编程逻辑门阵列是现在集成电路设计验证的主流技术，在设计成本、开发周期、可扩展性和可重构性等方面有着明显的优势，为实现高性能网络设备提供了新的实现方法。通用微处理器广泛应用于嵌入式系统，在低功耗、外设扩展、处理速度等方面表现尤为突出。 本文结合列车通信网络和多功能车辆总线的研究，系统介绍了多功能车辆总线网络设备及通讯协议栈的设计，阐述了系统开发的相关技术，并重点介绍了通讯协议栈的具体实现。多功能车辆总线网络设备基于现场可编程逻辑门阵列FPGA和通用微处理器ARM。协议栈链路下层协议和物理线路控制逻辑在时序、时延、可靠性和并发性等方面有严格要求，且此部分功能的算法相对简单，采用FPGA实现。协议栈链路上层协议和其他高层协议在多任务、存储和定时等方面有着诸多需求，且此部分功能的算法相对复杂，采用基于嵌入式实时操作系统RTEMS和ARM的软硬件平台实现。本课题已经完成了基于FPGA和ARM的多功能车辆总线网络设备及通讯协议栈，证明了该设计框架的可行性，为自主研发列车通信网络相关产品提供了一个良好的实例。

利用OVM实现基于Class的高效仿真验证环境

中国计算机学会

面向空间应用的图像压缩技术研究

在空间图像传感器技术向高分辨率、高精度的应用领域迈进的同时，图像数据量的增长向空间飞行器数据存储和传输设备的性能提出了挑战。 为了解决图像质量和系统瓶颈之间的矛盾， 在地面广泛应用的图像压缩技术也在空间领域逐步取得应用。 空间传感图像的关键性和复杂性使得空间图像系统的设计倾向于选择无损或近无损的图像压缩技术。 尽管本文研究的目的是针对特定工程项目进行图像压缩算法的选型和实现，对空间图像压缩技术特点和算法选型策略进行总结也是本文的一项重要任务。JPEG-LS和CCSDS分别是基于预测的编码技术和基于变换的编码技术的典型代表，两者同样支持图像的无损/有损压缩；同样具有较高的压缩率和较低的复杂度；同样便于软硬件实现，并且已经在国内外的空间项目中获得应用。本文对这两种算法原理进行了详细的研究， 并在此基础上对两者的性能和适用环境进行了对比。本文总结了两种算法各自的优点，并提出了对算法局限性的改进方案。 FPGA在图像处理领域一直具有性能方面的优势。近年来随着技术的成熟，FPGA在空间设备中逐渐获得广泛应用。本文对选定的空间图像压缩算法进行了FPGA 实现，并在硬件平台上对算法进行了验证。测试结果表明，本文提出的FPGA实现性能超过国内外其它 FPGA实现，并接近甚至超过部分 ASIC实现。