Quantum circuits for spin and flavor degrees of freedom of quarks forming nucleons

We discuss the quantum-circuit realization of the state of a nucleon in the scope of simple simmetry groups. Explicit algorithms are presented for the preparation of the state of a neutron or a proton as resulting from the composition of their quark constituents. We estimate the computational resources required for such a simulation and design a photonic network for its implementation. Moreover, we highlight that current work on three-body interactions in lattices of interacting qubits, combined with the measurement-based paradigm for quantum information processing, may also be suitable for the implementation of these nucleonic spin states.

Design and analysis of dual-rail circuits for security applications

Dual-rail encoding, return-to-spacer protocol, and hazard-free logic can be used to resist power analysis attacks by making energy consumed per clock cycle independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g., all-zeros, which gives rise to energy balancing problems. We address these problems by incorporating two spacers; the spacers alternate between adjacent clock cycles. This guarantees that all gates switch in every clock cycle regardless of the transmitted data values. To generate these dual-rail circuits, an automated tool has been developed. It is capable of converting synchronous netlists into dual-rail circuits and it is interfaced to industry CAD tools. Dual-rail and single-rail benchmarks based upon the advanced encryption standard (AES) have been simulated and compared in order to evaluate the method and the tool.

Mechanisms and sources of passive intermodulation in printed circuits

Modern wireless systems are expected to operate in multiple frequency bands and support diverse communications standards to provide the high volume and speed of data transmission. Today's major limitations of their performance are imposed by interference, spurious emission and noise generated by high-power carriers in antennas and passive components of the RF front-end. Passive Intermodulation (PIM), which causes the combinatorial frequency generation in the operational bands, presents a primary challenge to signal integrity, system efficacy and data throughput. © 2013 IEEE.

Design methodology for low power and arametric robustness through output-quality modulation:Application to color-interpolation filtering

Power dissipation and robustness to process variation have conflicting design requirements. Scaling of voltage is associated with larger variations, while Vdd upscaling or transistor upsizing for parametric-delay variation tolerance can be detrimental for power dissipation. However, for a class of signal-processing systems, effective tradeoff can be achieved between Vdd scaling, variation tolerance, and output quality. In this paper, we develop a novel low-power variation-tolerant algorithm/architecture for color interpolation that allows a graceful degradation in the peak-signal-to-noise ratio (PSNR) under aggressive voltage scaling as well as extreme process variations. This feature is achieved by exploiting the fact that all computations used in interpolating the pixel values do not equally contribute to PSNR improvement. In the presence of Vdd scaling and process variations, the architecture ensures that only the less important computations are affected by delay failures. We also propose a different sliding-window size than the conventional one to improve interpolation performance by a factor of two with negligible overhead. Simulation results show that, even at a scaled voltage of 77% of nominal value, our design provides reasonable image PSNR with 40% power savings. © 2006 IEEE.

Passive Intermodulation in Distributed Circuits with Cascaded Discrete Nonlinearities

The principle aspects of passive intermodulation (PIM) characterisation in distributed printed circuits with cascaded lumped nonlinearities are presented. Mechanisms of PIM generations have been investigated experimentally and modelled using the formalism of X-parameters. The devised equivalent circuit models are applied to the analysis of microstrip lines with distributed and cascaded lumped sources of nonlinearity. The dynamic measurements have revealed that PIM generation rates in straight and meandered microstrip lines differ and significantly deviate from those expected for the respective discrete sources of nonlinearity. The obtained results indicate that multiple physical sources of nonlinearity contribute to PIM generation in printed circuits. Finally, it is demonstrated that the electrical discontinuities can have significant effect on the overall PIM response of the distributed passive circuits and cause PIM product leakage and parasitic coupling between isolated circuit elements.

Nonlinear behavioral modeling of mixed signal RF-digital I/O devices

Esta tese investiga a caracterização (e modelação) de dispositivos que realizam o interface entre os domínios digital e analógico, tal como os buffers de saída dos circuitos integrados (CI). Os terminais sem fios da atualidade estão a ser desenvolvidos tendo em vista o conceito de rádio-definido-por-software introduzido por Mitola. Idealmente esta arquitetura tira partido de poderosos processadores e estende a operação dos blocos digitais o mais próximo possível da antena. Neste sentido, não é de estranhar que haja uma crescente preocupação, no seio da comunidade científica, relativamente à caracterização dos blocos que fazem o interface entre os domínios analógico e digital, sendo os conversores digital-analógico e analógico-digital dois bons exemplos destes circuitos. Dentro dos circuitos digitais de alta velocidade, tais como as memórias Flash, um papel semelhante é desempenhado pelos buffers de saída. Estes realizam o interface entre o domínio digital (núcleo lógico) e o domínio analógico (encapsulamento dos CI e parasitas associados às linhas de transmissão), determinando a integridade do sinal transmitido. Por forma a acelerar a análise de integridade do sinal, aquando do projeto de um CI, é fundamental ter modelos que são simultaneamente eficientes (em termos computacionais) e precisos. Tipicamente a extração/validação dos modelos para buffers de saída é feita usando dados obtidos da simulação de um modelo detalhado (ao nível do transístor) ou a partir de resultados experimentais. A última abordagem não envolve problemas de propriedade intelectual; contudo é raramente mencionada na literatura referente à caracterização de buffers de saída. Neste sentido, esta tese de Doutoramento foca-se no desenvolvimento de uma nova configuração de medição para a caracterização e modelação de buffers de saída de alta velocidade, com a natural extensão aos dispositivos amplificadores comutados RF-CMOS. Tendo por base um procedimento experimental bem definido, um modelo estado-da-arte é extraído e validado. A configuração de medição desenvolvida aborda não apenas a integridade dos sinais de saída mas também do barramento de alimentação. Por forma a determinar a sensibilidade das quantias estimadas (tensão e corrente) aos erros presentes nas diversas variáveis associadas ao procedimento experimental, uma análise de incerteza é também apresentada.

South Carolina/Common Pleas Court Circuits Meeting Benchmark

This is a list of the courts in all the circuits of South Carolina and the percentage of cases disposed of in 365 day or less. None of the courts met the 80% benchmark.

South Carolina/Common Pleas Court Circuits Meeting Benchmark ... as of August 31, 2014

This is a list of the courts in all the circuits of South Carolina and the percentage of cases disposed of in 365 day or less as of August 31, 2014. None of the courts met the 80% benchmark.

South Carolina/common pleas court circuits meeting benchmark 80% of Pending Docket 365 Days or Less From Placement on the Trial Docket as of February 28, 2015

This is a list of the courts in all the circuits of South Carolina and the percentage of cases disposed of in 365 day or less. Only three courts met the 80% benchmark.