Development of hardware in the loop real-time control techniques for hybrid power systems involving distributed demands and sustainable energy sources

The future power grid will effectively utilize renewable energy resources and distributed generation to respond to energy demand while incorporating information technology and communication infrastructure for their optimum operation. This dissertation contributes to the development of real-time techniques, for wide-area monitoring and secure real-time control and operation of hybrid power systems. ^ To handle the increased level of real-time data exchange, this dissertation develops a supervisory control and data acquisition (SCADA) system that is equipped with a state estimation scheme from the real-time data. This system is verified on a specially developed laboratory-based test bed facility, as a hardware and software platform, to emulate the actual scenarios of a real hybrid power system with the highest level of similarities and capabilities to practical utility systems. It includes phasor measurements at hundreds of measurement points on the system. These measurements were obtained from especially developed laboratory based Phasor Measurement Unit (PMU) that is utilized in addition to existing commercially based PMU’s. The developed PMU was used in conjunction with the interconnected system along with the commercial PMU’s. The tested studies included a new technique for detecting the partially islanded micro grids in addition to several real-time techniques for synchronization and parameter identifications of hybrid systems. ^ Moreover, due to numerous integration of renewable energy resources through DC microgrids, this dissertation performs several practical cases for improvement of interoperability of such systems. Moreover, increased number of small and dispersed generating stations and their need to connect fast and properly into the AC grids, urged this work to explore the challenges that arise in synchronization of generators to the grid and through introduction of a Dynamic Brake system to improve the process of connecting distributed generators to the power grid.^ Real time operation and control requires data communication security. A research effort in this dissertation was developed based on Trusted Sensing Base (TSB) process for data communication security. The innovative TSB approach improves the security aspect of the power grid as a cyber-physical system. It is based on available GPS synchronization technology and provides protection against confidentiality attacks in critical power system infrastructures. ^

Effective Reconfigurable Antenna Designs to Enhance Performance and Enable Wireless Powering

With the increase in traffic on the internet, there is a greater demand for wireless mobile and ubiquitous applications. These applications need antennas that are not only broadband, but can also work in different frequency spectrums. Even though there is a greater demand for such applications, it is still imperative to conserve power. Thus, there is a need to design multi-broadband antennas that do not use a lot of power. Reconfigurable antennas can work in different frequency spectrums as well as conserve power. The current designs of reconfigurable antennas work only in one band. There is a need to design reconfigurable antennas that work in different frequency spectrums. In this current era of high power consumption there is also a greater demand for wireless powering. This dissertation explores ideal designs of reconfigurable antennas that can improve performance and enable wireless powering. This dissertation also presents lab results of the multi-broadband reconfigurable antenna that was created. A detailed mathematical analyses, as well as extensive simulation results are also presented. The novel reconfigurable antenna designs can be extended to Multiple Input Multiple Output (MIMO) environments and military applications.

Implementação de uma arquitetura fuzzy neural em hardware com treinamento online

Computational Intelligence Methods have been expanding to industrial applications motivated by their ability to solve problems in engineering. Therefore, the embedded systems follow the same idea of using computational intelligence tools embedded on machines. There are several works in the area of embedded systems and intelligent systems. However, there are a few papers that have joined both areas. The aim of this study was to implement an adaptive fuzzy neural hardware with online training embedded on Field Programmable Gate Array – FPGA. The system adaptation can occur during the execution of a given application, aiming online performance improvement. The proposed system architecture is modular, allowing different configurations of fuzzy neural network topologies with online training. The proposed system was applied to: mathematical function interpolation, pattern classification and selfcompensation of industrial sensors. The proposed system achieves satisfactory performance in both tasks. The experiments results shows the advantages and disadvantages of online training in hardware when performed in parallel and sequentially ways. The sequentially training method provides economy in FPGA area, however, increases the complexity of architecture actions. The parallel training method achieves high performance and reduced processing time, the pipeline technique is used to increase the proposed architecture performance. The study development was based on available tools for FPGA circuits.

Implementação em FPGA de módulo de efeito de reverberação

Reverberation is caused by the reflection of the sound in adjacent surfaces close to the sound source during its propagation to the listener. The impulsive response of an environment represents its reverberation characteristics. Being dependent on the environment, reverberation takes to the listener characteristics of the space where the sound is originated and its absence does not commonly sounds like “natural”. When recording sounds, it is not always possible to have the desirable characteristics of reverberation of an environment, therefore methods for artificial reverberation have been developed, always seeking a more efficient implementations and more faithful to the real environments. This work presents an implementation in FPGAs (Field Programmable Gate Arrays ) of a classic digital reverberation audio structure, based on a proposal of Manfred Schroeder, using sets of all-pass and comb filters. The developed system exploits the use of reconfigurable hardware as a platform development and implementation of digital audio effects, focusing on the modularity and reuse characteristics

Modelo comportamental do capacitor ferroelétrico como unidade básica de neurônios artificiais e sua implementação em FPGA

This work proposes the use of the behavioral model of the hysteresis loop of the ferroelectrics capacitor as a new alternative to the usually costly techniques in the computation of nonlinear functions in artificial neurons implemented on reconfigurable hardware platform, in this case, a FPGA device. Initially the proposal has been validated by the implementation of the boolean logic through the digital models of two artificial neurons: the Perceptron and a variation of the model Integrate and Fire Spiking Neuron, both using the model also digital of the hysteresis loop of the ferroelectric capacitor as it’s basic nonlinear unit for the calculations of the neurons outputs. Finally, it has been used the analog model of the ferroelectric capacitor with the goal of verifying it’s effectiveness and possibly the reduction of the number of necessary logic elements in the case of implementing the artificial neurons on integrated circuit. The implementations has been carried out by Simulink models and the synthesizing has been done through the DSP Builder software from Altera Corporation.

Mecanismo de tolerância a falhas através de escalonamento para uma arquitetura reconfigurável de grão grosso

The continuous evolution of integrated circuit technology has allowed integrating thousands of transistors on a single chip. This is due to the miniaturization process, which reduces the diameter of wires and transistors. One drawback of this process is that the circuit becomes more fragile and susceptible to break, making the circuit more susceptible to permanent faults during the manufacturing process as well as during their lifetime. Coarse Grained Reconfigurable Architectures (CGRAs) have been used as an alternative to traditional architectures in an attempt to tolerate such faults due to its intrinsic hardware redundancy and high performance. This work proposes a fault tolerance mechanism in a CGRA in order to increase the architecture fault tolerance even considering a high fault rate. The proposed mechanism was added to the scheduler, which is the mechanism responsible for mapping instructions onto the architecture. The instruction mapping occurs at runtime, translating binary code without the need for recompilation. Furthermore, to allow faster implementation, instruction mapping is performed using a greedy module scheduling algorithm, which consists of a software pipeline technique for loop acceleration. The results show that, even with the proposed mechanism, the time for mapping instructions is still in order of microseconds. This result allows that instruction mapping process remains at runtime. In addition, a study was also carried out mapping scheduler rate. The results demonstrate that even at fault rates over 50% in functional units and interconnection components, the scheduler was able to map instructions onto the architecture in most of the tested applications.

Implementação de uma matriz de neurônios dinamicamente reconfigurável para descrição de topologias de redes neurais artificiais multilayer perceptrons

The Artificial Neural Networks (ANN), which is one of the branches of Artificial Intelligence (AI), are being employed as a solution to many complex problems existing in several areas. To solve these problems, it is essential that its implementation is done in hardware. Among the strategies to be adopted and met during the design phase and implementation of RNAs in hardware, connections between neurons are the ones that need more attention. Recently, are RNAs implemented both in application specific integrated circuits's (Application Specific Integrated Circuits - ASIC) and in integrated circuits configured by the user, like the Field Programmable Gate Array (FPGA), which have the ability to be partially rewritten, at runtime, forming thus a system Partially Reconfigurable (SPR), the use of which provides several advantages, such as flexibility in implementation and cost reduction. It has been noted a considerable increase in the use of FPGAs for implementing ANNs. Given the above, it is proposed to implement an array of reconfigurable neurons for topologies Description of artificial neural network multilayer perceptrons (MLPs) in FPGA, in order to encourage feedback and reuse of neural processors (perceptrons) used in the same area of the circuit. It is further proposed, a communication network capable of performing the reuse of artificial neurons. The architecture of the proposed system will configure various topologies MLPs networks through partial reconfiguration of the FPGA. To allow this flexibility RNAs settings, a set of digital components (datapath), and a controller were developed to execute instructions that define each topology for MLP neural network.

Implementação de uma matriz de neurônios dinamicamente reconfigurável para descrição de topologias de redes neurais artificiais multilayer perceptrons

The Artificial Neural Networks (ANN), which is one of the branches of Artificial Intelligence (AI), are being employed as a solution to many complex problems existing in several areas. To solve these problems, it is essential that its implementation is done in hardware. Among the strategies to be adopted and met during the design phase and implementation of RNAs in hardware, connections between neurons are the ones that need more attention. Recently, are RNAs implemented both in application specific integrated circuits's (Application Specific Integrated Circuits - ASIC) and in integrated circuits configured by the user, like the Field Programmable Gate Array (FPGA), which have the ability to be partially rewritten, at runtime, forming thus a system Partially Reconfigurable (SPR), the use of which provides several advantages, such as flexibility in implementation and cost reduction. It has been noted a considerable increase in the use of FPGAs for implementing ANNs. Given the above, it is proposed to implement an array of reconfigurable neurons for topologies Description of artificial neural network multilayer perceptrons (MLPs) in FPGA, in order to encourage feedback and reuse of neural processors (perceptrons) used in the same area of the circuit. It is further proposed, a communication network capable of performing the reuse of artificial neurons. The architecture of the proposed system will configure various topologies MLPs networks through partial reconfiguration of the FPGA. To allow this flexibility RNAs settings, a set of digital components (datapath), and a controller were developed to execute instructions that define each topology for MLP neural network.

Progettazione e sviluppo di un sistema per la verifica dell'integrità hardware e firmware di un sistema

Questa tesi tratta un argomento che si è fatto sempre più interessante, soprattutto in questi ultimi anni, l'integrità firmware e hardware di un sistema. Oggigiorno milioni di persone fanno completamente affidamento al proprio sistema lasciando nelle loro mani moli di dati personali e non, molte delle quali si affidano ai moderni antivirus i quali, però, non sono in grado di rilevare e gestire attacchi che implicano l'alterazione dei firmware. Verranno mostrati diversi attacchi di questo tipo cercando di fare capire come la relativa sicurezza sia importante, inoltre saranno discussi diversi progetti reputati interessanti. Sulla base delle ricerche effettuate, poi, sarà mostrata la progettazione e l'implementazione di un software in grado di rilevare alterazioni hardware e firmware in un sistema.

Hardware Implementation of a Fault-Tolerant Hopfield Neural Network on FPGAs

This letter presents an FPGA implementation of a fault-tolerant Hopfield NeuralNetwork (HNN). The robustness of this circuit against Single Event Upsets (SEUs) and Single Event Transients (SETs) has been evaluated. Results show the fault tolerance of the proposed design, compared to a previous non fault- tolerant implementation and a solution based on triple modular redundancy (TMR) of a standard HNN design.

A planar reconfigurable linear rigid-body motion linkage with two operation modes

A planar reconfigurable linear (also rectilinear) rigid-body motion linkage (RLRBML) with two operation modes, that is, linear rigid-body motion mode and lockup mode, is presented using only R (revolute) joints. The RLRBML does not require disassembly and external intervention to implement multi-task requirements. It is created via combining a Robert’s linkage and a double parallelogram linkage (with equal lengths of rocker links) arranged in parallel, which can convert a limited circular motion to a linear rigid-body motion without any reference guide way. This linear rigid-body motion is achieved since the double parallelogram linkage can guarantee the translation of the motion stage, and Robert’s linkage ensures the approximate straight line motion of its pivot joint connecting to the double parallelogram linkage. This novel RLRBML is under the linear rigid-body motion mode if the four rocker links in the double parallelogram linkage are not parallel. The motion stage is in the lockup mode if all of the four rocker links in the double parallelogram linkage are kept parallel in a tilted position (but the inner/outer two rocker links are still parallel). In the lockup mode, the motion stage of the RLRBML is prohibited from moving even under power off, but the double parallelogram linkage is still moveable for its own rotation application. It is noted that further RLRBMLs can be obtained from the above RLRBML by replacing Robert’s linkage with any other straight line motion linkage (such as Watt’s linkage). Additionally, a compact RLRBML and two single-mode linear rigid-body motion linkages are presented.

SDN enabled dynamically reconfigurable high capacity optical access architecture for converged services

Dynamically reconfigurable time-division multiplexing (TDM) dense wavelength division multiplexing (DWDM) long-reach passive optical networks (PONs) can support the reduction of nodes and network interfaces by enabling a fully meshed flat optical core. In this paper we demonstrate the flexibility of the TDM-DWDM PON architecture, which can enable the convergence of multiple service types on a single physical layer. Heterogeneous services and modulation formats, i.e. residential 10G PON channels, business 100G dedicated channel and wireless fronthaul, are demonstrated co-existing on the same long reach TDM-DWDM PON system, with up to 100km reach, 512 users and emulated system load of 40 channels, employing amplifier nodes with either erbium doped fiber amplifiers (EDFAs) or semiconductor optical amplifiers (SOAs). For the first time end-to-end software defined networking (SDN) management of the access and core network elements is also implemented and integrated with the PON physical layer in order to demonstrate two service use cases: a fast protection mechanism with end-to-end service restoration in the case of a primary link failure; and dynamic wavelength allocation (DWA) in response to an increased traffic demand.

The hardware impairments impact on fixed-gain AF relaying performance in Nakagami-m fading

The effects of joint hardware impairments on the performance of fixed gain amplify-and-forward (AF) relaying are studied. By considering IQ imbalance at the source and destination and the nonlinear relay the outage probability over Nakagami-m fading channels is derived, and the effects of fading and hardware impairments on the system are analysed. The analytical results are verified by Monte Carlo simulations.

Reconfigurable Matching Networks for RF Amplifiers

This article presents applications of reconfigurable matching networks for RF amplifier design. Two possible solutions are given, one where the switching element is a PIN diode, and the other is based on graphene. Due to the fact that its conductivity depends on applied bias voltage, the graphene-based circuits can be used in microwave circuits as controllable elements. The structure of the proposed switch is very simple and it is particularly convenient for microstrip-based circuits. Because of that, a design of reconfigurable amplifier with the graphene-based switch is presented together with the one which has the PIN diode switch. Both amplifiers have the same specifications, and the one with the PIN diode switch is fabricated. The amplifier utilizing the PIN switch was used as a reference to make a comparison the two types of switches. Results of both amplifiers are very similar which indicates possible future applications of the graphene-based switch.