Operating infrastructure for an FPGA and ARM system

Advances in FPGA technology and higher processing capabilities requirements have pushed to the emerge of All Programmable Systems-on-Chip, which incorporate a hard designed processing system and a programmable logic that enable the development of specialized computer systems for a wide range of practical applications, including data and signal processing, high performance computing, embedded systems, among many others. To give place to an infrastructure that is capable of using the benefits of such a reconfigurable system, the main goal of the thesis is to implement an infrastructure composed of hardware, software and network resources, that incorporates the necessary services for the operation, management and interface of peripherals, that coompose the basic building blocks for the execution of applications. The project will be developed using a chip from the Zynq-7000 All Programmable Systems-on-Chip family.

Arquitetura híbrida com DSP e FPGA para implementação de controladores de filtros ativos de potência

The presence of non-linear loads at a point in the distribution system may deform voltage waveform due to the consumption of non-sinusoidal currents. The use of active power filters allows significant reduction of the harmonic content in the supply current. However, the processing of digital control structures for these filters may require high performance hardware, particularly for reference currents calculation. This work describes the development of hardware structures with high processing capability for application in active power filters. In this sense, it considers an architecture that allows parallel processing using programmable logic devices. The developed structure uses a hybrid model using a DSP and an FPGA. The DSP is used for the acquisition of current and voltage signals, calculation of fundamental current related controllers and PWM generation. The FPGA is used for intensive signal processing, such as the harmonic compensators. In this way, from the experimental analysis, significant reductions of the processing time are achieved when compared to traditional approaches using only DSP. The experimental results validate the designed structure and these results are compared with other ones from architectures reported in the literature.

Principios del FPGA y aplicaciones en el control de procesos industriales

La presente investigación muestra los pasos sugeridos para introducirse a la creación de sistemas electrónicos programables a través de la tecnología FPGA. Un FPGA es un dispositivo programable de alta capacidad que puede ser utilizado para la creación de sistemas digitales de control y automatización de procesos. La investigación se divide en cuatro capítulos estructurados de la siguiente forma: Capítulo I- Teoría general: Abarca las características básicas de los FPGA en general y las del equipo a utilizar; Capítulo II-Software: Consta de un manual de usuario sobre el software utilizado en la investigación; Capítulo III-Laboratorios: Una serie de laboratorios prácticos; Capítulo IV- Aplicaciones: Metodología y ejemplo

Implementação em FPGA de compensadores de desvios para conversor analógico digital intercalado

This work presents the modeling and FPGA implementation of digital TIADC mismatches compensation systems. The development of the whole work follows a top-down methodology. Following this methodology was developed a two channel TIADC behavior modeling and their respective offset, gain and clock skew mismatches on Simulink. In addition was developed digital mismatch compensation system behavior modeling. For clock skew mismatch compensation fractional delay filters were used, more specifically, the efficient Farrow struct. The definition of wich filter design methodology would be used, and wich Farrow structure, required the study of various design methods presented in literature. The digital compensation systems models were converted to VHDL, for FPGA implementation and validation. These system validation was carried out using the test methodology FPGA In Loop . The results obtained with TIADC mismatch compensators show the high performance gain provided by these structures. Beyond this result, these work illustrates the potential of design, implementation and FPGA test methodologies.

Diseño e implementación en FPGA de un filtro de partículas para aplicaciones biomédicas

La diabetes mellitus tipo 1 (DM1) es una enfermedad crónica caracterizada por la incapacidad del páncreas de producir insulina. Esta hormona regula la absorción de la glucosa del torrente sanguíneo por parte de las células. Debido a la ausencia de insulina en el cuerpo, la glucosa se acumula en el torrente sanguíneo provocando problemas a corto y largo plazo, como por ejemplo deterioro celular. Los pacientes con esta enfermedad necesitan controlar su glucemia (concentración de glucosa en sangre) midiendo la misma de forma regular e inyectándose insulina subcutánea de por vida. Para conocer la glucemia se pueden utilizar Monitores Continuos de Glucosa (MCG), que proporcionan el valor de la glucosa intersticial en un rango entre uno y cinco minutos. Los MCG actuales presentan los siguientes problemas: Por un lado, el sensor que lleva incorporado introduce ruidos asociados a la medición obtenida. Y, por otro lado, el sensor se degrada a lo largo de su vida útil, lo que dificulta la interpretación de los datos obtenidos. La solución propuesta en este trabajo consiste en la utilización de filtros de partículas. Este tipo de filtros consta de cuatro fases: inicialización, predicción, corrección y remuestreo. Son capaces de identificar los estados ocultos del sistema (glucosa en sangre y degeneración del sensor), a partir de medidas indirectas del mismo (como por ejemplo la glucosa intersticial) teniendo en cuenta el ruido de las mediciones del MCG. En este proyecto se va a aplicar un filtro de partículas de cuatro estados (glucosa, velocidad de variación de la glucosa, degeneración del sensor y velocidad de variación de la degeneración del sensor.). En primera instancia, se utilizará la herramienta Matlab para analizar el correcto funcionamiento de este algoritmo frente a los problemas mencionados anteriormente de los MCG. Y, en segundo lugar, se realizará una implementación hardware sobre una FPGA.

A Study of the Robustness Against SEUs of Digital Circuits Implemented with FPGA DSPs

In this paper we present an experimental validation of the reliability increase of digital circuits implemented in XilinxTMFPGAs when they are implemented using the DSPs (Digital Signal Processors) that are available in the reconfigurable device. For this purpose, we have used a fault-injection platform developed by our research group, NESSY [1]. The presented experiments demonstrate that the probability of occurrence of a SEU effect is similar both in the circuits implemented with and without using embedded DSPs. However, the former are more efficient in terms of area usage, which leads to a decrease in the probability of a SEU occurrence.

Implémentation sur FPGA de l’algorithme MUSIC sur antenne-réseau expérimentale à 10 GHz

Les techniques des directions d’arrivée (DOA) sont une voie prometteuse pour accroitre la capacité des systèmes et les services de télécommunications en permettant de mieux estimer le canal radio-mobile. Elles permettent aussi de suivre précisément des usagers cellulaires pour orienter les faisceaux d’antennes dans leur direction. S’inscrivant dans ce contexte, ce présent mémoire décrit étape par étape l’implémentation de l’algorithme de haut niveau MUSIC (MUltiple SIgnal Classification) sur une plateforme FPGA afin de déterminer en temps réel l’angle d’arrivée d’une ou des sources incidentes à un réseau d’antennes. Le concept du prototypage rapide des lois de commande (RCP) avec les outils de XilinxTM System generator (XSG) et du MBDK (Model Based Design Kit) de NutaqTM est le concept de développement utilisé. Ce concept se base sur une programmation de code haut niveau à travers des modèles, pour générer automatiquement un code de bas niveau. Une attention particulière est portée sur la méthode choisie pour résoudre le problème de la décomposition en valeurs et vecteurs propres de la matrice complexe de covariance par l’algorithme de Jacobi. L’architecture mise en place implémentant cette dernière dans le FPGA (Field Programmable Gate Array) est détaillée. Par ailleurs, il est prouvé que MUSIC ne peut effectuer une estimation intéressante de la position des sources sans une calibration préalable du réseau d’antennes. Ainsi, la technique de calibration par matrice G utilisée dans ce projet est présentée, en plus de son modèle d’implémentation. Enfin, les résultats expérimentaux du système mis à l’épreuve dans un environnement réel en présence d’une source puis de deux sources fortement corrélées sont illustrés et analysés.

AITPM Email Newsletter Volume 0905, May 2009: Presidents Message

President’s Message Hello fellow AITPM members, We’ve been offered a lot of press lately about the Federal Government’s plan for the multibillion dollar rollout of its high speed broadband network, which at the moment is being rated to a speed of 100Mb/s. This seems fantastic in comparison to the not atypical 250 to 500kb/s that I receive on my metropolitan cable broadband, which incidentally my service provider rates at theoretical speeds of up to 8 Mb/s. I have no doubt that such a scheme will generate significant advantages to business and consumers. However, I also have some reservations. Only a few of years ago I marvelled at my first 256Mb USB stick, which cost my employer about $90. Last month I purchased a 16Gb stick with a free computer carry bag for $80, which on the back of my envelope has given me about 72 times the value of my first USB stick not including the carry bag! I am pretty sure the technology industry will find a way to eventually push a lot more than 100Mb/s down the optic fibre network just as they have done with pushing several Mb/s ADSL2 down antique copper wire. This makes me wonder about the general problem of inbuilt obsolescence of all things high-tech due to rapid advances in the tech industry. As a transport professional I then think to myself that our industry has been moving forward at somewhat of a slower pace. We certainly have had major milestones having significant impacts, such as the move from horse and cart to the self propelled motor vehicle, sealing and formal geometric design of roads, development of motorways, signalisation of intersections, coordination of networks, to simulation modelling for real time adaptive control (perhaps major change has been at a frequency of 30 years or so?). But now with ITS truly penetrating the transport market, largely thanks to the in-car GPS navigator, smart phone, e-toll and e-ticket, I believe that to avoid our own obsolescence we’re going to need to “plan for ITS” rather than just what we seem to have been doing up until now, that is, to get it out there. And we’ll likely need to do it at a faster pace. It will involve understanding how to data mine enormous data sets, better understanding the human/machine interface, keeping pace with automotive technology more closely, resolving the ethical and privacy chestnuts, and in the main actually planning for ITS to make peoples’ lives easier rather than harder. And in amongst this we’ll need to keep pace with the types of technology advances similar to my USB stick example above. All the while we’ll be making a brand new set of friends in the disciplines that will morph into ITS along with us. Hopefully these will all be “good” problems for our profession to have. I should close in reminding everyone again that AITPM’s flagship event, the 2009 AITPM National Conference, Traffic Beyond Tomorrow, is being held in Adelaide from 5 to 7 August. www.aitpm.com has all of the details about how to register, sponsor a booth, session, etc. Best regards all, Jon Bunker

Characteristic analysis for multisampled digital implementation of fixed-switching-frequency closed-loop modulation of voltage-source inverter

In this paper, a fixed-switching-frequency closed-loop modulation of a voltage-source inverter (VSI), upon the digital implementation of the modulation process, is analyzed and characterized. The sampling frequency of the digital processor is considered as an integer multiple of the modulation switching frequency. An expression for the determination of the modulation design parameter is developed for smooth modulation at a fixed switching frequency. The variation of the sampling frequency, switching frequency, and modulation index has been analyzed for the determination of the switching condition under closed loop. It is shown that the switching condition determined based on the continuous-time analysis of the closed-loop modulation will ensure smooth modulation upon the digital implementation of the modulation process. However, the stability properties need to be tested prior to digital implementation as they get deteriorated at smaller sampling frequencies. The closed-loop modulation index needs to be considered maximum while determining the design parameters for smooth modulation. In particular, a detailed analysis has been carried out by varying the control gain in the sliding-mode control of a two-level VSI. The proposed analysis of the closed-loop modulation of the VSI has been verified for the operation of a distribution static compensator. The theoretical results are validated experimentally on both single- and three-phase systems.

A methodological approach to visceral hedonic rhetoric

One of the most important tasks as an industrial designer is to evoke specific affective responses via the creation of their designed products. This paper describes an investigation of visceral hedonic rhetoric through the study of interactive products. This research lays the foundation for this work by discussing the scope, significance and limitations of currently available research in the areas of visceral design, consumer hedonics and product rhetoric. Understanding why consumers respond to certain visceral hedonic rhetoric stimulus and what those stimuli are will provide further understanding into the field of emotional design. The study examines visceral hedonic responses given by consumers to three interactive products including mobile telephones, USB memory sticks and MP3 players. The methods used in this study will be discussed in further detail in this paper.

Vision-based topological mapping and localisation

Competent navigation in an environment is a major requirement for an autonomous mobile robot to accomplish its mission. Nowadays, many successful systems for navigating a mobile robot use an internal map which represents the environment in a detailed geometric manner. However, building, maintaining and using such environment maps for navigation is difficult because of perceptual aliasing and measurement noise. Moreover, geometric maps require the processing of huge amounts of data which is computationally expensive. This thesis addresses the problem of vision-based topological mapping and localisation for mobile robot navigation. Topological maps are concise and graphical representations of environments that are scalable and amenable to symbolic manipulation. Thus, they are well-suited for basic robot navigation applications, and also provide a representational basis for the procedural and semantic information needed for higher-level robotic tasks. In order to make vision-based topological navigation suitable for inexpensive mobile robots for the mass market we propose to characterise key places of the environment based on their visual appearance through colour histograms. The approach for representing places using visual appearance is based on the fact that colour histograms change slowly as the field of vision sweeps the scene when a robot moves through an environment. Hence, a place represents a region of the environment rather than a single position. We demonstrate in experiments using an indoor data set, that a topological map in which places are characterised using visual appearance augmented with metric clues provides sufficient information to perform continuous metric localisation which is robust to the kidnapped robot problem. Many topological mapping methods build a topological map by clustering visual observations to places. However, due to perceptual aliasing observations from different places may be mapped to the same place representative in the topological map. A main contribution of this thesis is a novel approach for dealing with the perceptual aliasing problem in topological mapping. We propose to incorporate neighbourhood relations for disambiguating places which otherwise are indistinguishable. We present a constraint based stochastic local search method which integrates the approach for place disambiguation in order to induce a topological map. Experiments show that the proposed method is capable of mapping environments with a high degree of perceptual aliasing, and that a small map is found quickly. Moreover, the method of using neighbourhood information for place disambiguation is integrated into a framework for topological off-line simultaneous localisation and mapping which does not require an initial categorisation of visual observations. Experiments on an indoor data set demonstrate the suitability of our method to reliably localise the robot while building a topological map.

Designing ePortfolios for music postgraduate study : a practice-led inquiry

In this research I have examined how ePortfolios can be designed for Music postgraduate study through a practice led research enquiry. This process involved designing two Web 2.0 ePortfolio systems for a group of five post graduate music research students. The design process revolved around the application of an iterative methodology called Software Develop as Research (SoDaR) that seeks to simultaneously develop design and pedagogy. The approach to designing these ePortfolio systems applied four theoretical protocols to examine the use of digitised artefacts in ePortfolio systems to enable a dynamic and inclusive dialogue around representations of the students work. The research and design process involved an analysis of existing software and literature with a focus upon identifying the affordances of available Web 2.0 software and the applications of these ideas within 21st Century life. The five post graduate music students each posed different needs in relation to the management of digitised artefacts and the communication of their work amongst peers, supervisors and public display. An ePortfolio was developed for each of them that was flexible enough to address their needs within the university setting. However in this first SoDaR iteration data gathering phase I identified aspects of the university context that presented a negative case that impacted upon the design and usage of the ePortfolios and prevented uptake. Whilst the portfolio itself functioned effectively, the university policies and technical requirements prevented serious use. The negative case analysis of the case study found revealed that Access and Control and Implementation, Technical and Policy Constraints protocols where limiting user uptake. From the semistructured interviews carried out as part of this study participant feedback revealed that whilst the participants did not use the ePortfolio system I designed, each student was employing Web 2.0 social networking and storage processes in their lives and research. In the subsequent iterations I then designed a more ‘ideal’ system that could be applied outside of the University context that draws upon the employment of these resources. In conclusion I suggest recommendations about ePortfolio design that considers what the applications of the theoretical protocols reveal about creative arts settings. The transferability of these recommendations are of course dependent upon the reapplication of the theoretical protocols in a new context. To address the mobility of ePortfolio design between Institutions and wider settings I have also designed a prototype for a business card sized USB portal for the artists’ ePortfolio. This research project is not a static one; it stands as an evolving design for a Web 2.0 ePortfolio that seeks to refer to users needs, institutional and professional contexts and the development of software that can be incorporated within the design. What it potentially provides to creative artist is an opportunity to have a dialogue about art with artefacts of the artist products and processes in that discussion.

Low-cost hardware speech enhancement for improved speech recognition in automotive environments

Voice recognition is one of the key enablers to reduce driver distraction as in-vehicle systems become more and more complex. With the integration of voice recognition in vehicles, safety and usability are improved as the driver’s eyes and hands are not required to operate system controls. Whilst speaker independent voice recognition is well developed, performance in high noise environments (e.g. vehicles) is still limited. La Trobe University and Queensland University of Technology have developed a low-cost hardware-based speech enhancement system for automotive environments based on spectral subtraction and delay–sum beamforming techniques. The enhancement algorithms have been optimised using authentic Australian English collected under typical driving conditions. Performance tests conducted using speech data collected under variety of vehicle noise conditions demonstrate a word recognition rate improvement in the order of 10% or more under the noisiest conditions. Currently developed to a proof of concept stage there is potential for even greater performance improvement.

A synthesizable hardware evolutionary algorithm design for unmanned aerial system real-time path planning

The main objective of this paper is to detail the development of a feasible hardware design based on Evolutionary Algorithms (EAs) to determine flight path planning for Unmanned Aerial Vehicles (UAVs) navigating terrain with obstacle boundaries. The design architecture includes the hardware implementation of Light Detection And Ranging (LiDAR) terrain and EA population memories within the hardware, as well as the EA search and evaluation algorithms used in the optimizing stage of path planning. A synthesisable Very-high-speed integrated circuit Hardware Description Language (VHDL) implementation of the design was developed, for realisation on a Field Programmable Gate Array (FPGA) platform. Simulation results show significant speedup compared with an equivalent software implementation written in C++, suggesting that the present approach is well suited for UAV real-time path planning applications.