Subpixel interpolation architecture for multistandard video motion estimation

A new reconfigurable subpixel interpolation architecture for multistandard (e.g., MPEG-2, MPEG-4, H.264, and AVS) video motion estimation (ME) is presented. This exploits the mixed use of parallel and serial-input FIR filters to achieve high throughput rate and efficient silicon utilization. Silicon design studies show that this can be implemented using 34.8 × 10 3 gates with area and performance that compares very favorably with specific fixed solutions, e.g., for the H.264 standard alone. This can support SDTV and HDTV applications when implemented in 0.18 µm CMOS technology, with further performance enhancements achievable at 0.13 µm and below. © 2009 IEEE.

The influence of video games with apocalyptic content in adolescents

The aim of this study is the dissertation and analysis of the influence (sociological, psychological and cultural) exerted on adolescents by the concept of Apocalypse. Become a key thought of visual culture, the called doomsday theory achieves one of its highest expressions in video games, possibly the favorite entertainment for young people in their leisure time. The results obtained in this research represent a first approach to the subject through the selected samples, two secondary schools from the city of Seville with disparate locations and divergent socioeconomic backgrounds. To reinforce the comparative study, we have included issues related to parental control, principal gaming platforms used by respondents or the number of hours dedicated to this type of entertainment. The conclusions demonstrate an irremediable attraction from our youth towards apocalyptic universes, plotter consciously with leisure and entertainment as escape from their routine of everyday life.

Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding

A new domain-specific, reconfigurable system-on-a-chip (SoC) architecture is proposed for video motion estimation. This has been designed to cover most of the common block-based video coding standards, including MPEG-2, MPEG-4, H.264, WMV-9 and AVS. The architecture exhibits simple control, high throughput and relatively low hardware cost when compared with existing circuits. It can also easily handle flexible search ranges without any increase in silicon area and can be configured prior to the start of the motion estimation process for a specific standard. The computational rates achieved make the circuit suitable for high-end video processing applications, such as HDTV. Silicon design studies indicate that circuits based on this approach incur only a relatively small penalty in terms of power dissipation and silicon area when compared with implementations for specific standards. Indeed, the cost/performance achieved exceeds that of existing but specific solutions and greatly exceeds that of general purpose field programmable gate array (FPGA) designs.