Trace me if you can: the use of intrinsic biogeochemical markers in marine top predators

Human activities have serious impacts on marine apex predators. Inadequate knowledge of the spatial and trophic ecology of these marine animals ultimately compromises the viability of their populations and impedes our ability to use them as environmental biomonitors. Intrinsic biogeochemical markers, such as stable isotopes, fatty acids, trace elements, and chemical pollutants, are increasingly being used to trace the spatial and trophic ecology of marine top predators. Notable advances include the emergence of the first oceanographic"isoscapes" (isotopic geographic gradients), the advent of compound-specific isotopic analyses, improvements in diet reconstruction through Bayesian statistics, and tissue analysis of tracked animals to ground-truth biogeochemical profiles. However, most researchers still focus on only a few tracers. Moreover, insufficient knowledge of the biogeochemical integration in tissues, fractionation and routing processes, and geographic and temporal variability in baseline levels continue to hamper the resolution and potential of these markers in studying the spatial and feeding ecology of top predators.

Optimal Traffic Grooming in WDM using Lighttours

Recent developments in optical communications have allowed simpler optical devices to improve network resource utilization. As such, we propose adding a lambda-monitoring device to a wavelength-routing switch (WRS) allowing better performance when traffic is routed and groomed. This device may allow a WRS to aggregate traffic over optical routes without incurring in optical-electrical-optical conversion for the existing traffic. In other words, optical routes can be taken partially to route demands creating a sort of "lighttours". In this paper, we compare the number of OEO conversions needed to route a complete given traffic matrix using either lighttours or lightpaths

Operational Cost Reduction in WDM Networks using Lighttours

Wavelength division multiplexing (WDM) networks have been adopted as a near-future solution for the broadband Internet. In previous work we proposed a new architecture, named enhanced grooming (G+), that extends the capabilities of traditional optical routes (lightpaths). In this paper, we compare the operational expenditures incurred by routing a set of demands using lightpaths with that of lighttours. The comparison is done by solving an integer linear programming (ILP) problem based on a path formulation. Results show that, under the assumption of single-hop routing, almost 15% of the operational cost can be reduced with our architecture. In multi-hop routing the operation cost is reduced in 7.1% and at the same time the ratio of operational cost to number of optical-electro-optical conversions is reduced for our architecture. This means that ISPs could provide the same satisfaction in terms of delay to the end-user with a lower investment in the network architecture

G+: Enhanced Traffic Grooming in WDM Mesh Networks using Lighttours

In this article, a new technique for grooming low-speed traffic demands into high-speed optical routes is proposed. This enhancement allows a transparent wavelength-routing switch (WRS) to aggregate traffic en route over existing optical routes without incurring expensive optical-electrical-optical (OEO) conversions. This implies that: a) an optical route may be considered as having more than one ingress node (all inline) and, b) traffic demands can partially use optical routes to reach their destination. The proposed optical routes are named "lighttours" since the traffic originating from different sources can be forwarded together in a single optical route, i.e., as taking a "tour" over different sources towards the same destination. The possibility of creating lighttours is the consequence of a novel WRS architecture proposed in this article, named "enhanced grooming" (G+). The ability to groom more traffic in the middle of a lighttour is achieved with the support of a simple optical device named lambda-monitor (previously introduced in the RingO project). In this article, we present the new WRS architecture and its advantages. To compare the advantages of lighttours with respect to classical lightpaths, an integer linear programming (ILP) model is proposed for the well-known multilayer problem: traffic grooming, routing and wavelength assignment The ILP model may be used for several objectives. However, this article focuses on two objectives: maximizing the network throughput, and minimizing the number of optical-electro-optical conversions used. Experiments show that G+ can route all the traffic using only half of the total OEO conversions needed by classical grooming. An heuristic is also proposed, aiming at achieving near optimal results in polynomial time

Estudi i implementació pràctica d'una xarxa Wifi Mesh

En el projecte ens centrarem en el funcionament de les Xarxes mallades sense fils, es fa una breu explicació de les xarxes Ad-hoc, ja que aquestes formen un part important dintre d’una xarxa Mesh. S’explicaran diversos protocols d’enrutament com ara BATMAN, AODV, 802.11s i OLSR. Aquest últim és el que utilitzarem per a la configuració de la xarxa que realitzarem. S’explicarà el tipus de paquets que s’envien entre els nodes perquè el funcionament de la xarxa sigui òptim i tots els clients puguin tenir-hi accés i estiguin connectats entre ells. Al finalitzar l’estudi teòric d’aquest tipus de xarxa i veure les seves avantatges i desavantatges respecte altres tipus de xarxes sense fils, es muntaran dos petites xarxa. Per a muntar-les utilitzarem de Punts d’Accés els nodes Ubuquiti Nanoestation LocoM2. Una de les xarxes serà al poble Bellcaire d’Urgell, on és connectaran tres cases, on només una te accés a Internet i els nodes estaran connectats en línia, es a dir, del Node1 – Node2 – Node3. La segona serà a una casa de Barcelona on mitjançant els tres nodes obtindrem una connexió d’Internet a tota la casa, en aquest cas els tres nodes estaran connectats els tres formant un cercle, es a dir, Node1-Node2-Node3-Node1. Finalment, és mirarà una proposta de futur, on es parlaria amb l’Ajuntament del poble on s’ha fet la primera proba per realitzar una Xarxa mallada sense fils a tots els llocs públics del poble.

On Fault Tolerance Methods for Networks-on-Chip

Technology scaling has proceeded into dimensions in which the reliability of manufactured devices is becoming endangered. The reliability decrease is a consequence of physical limitations, relative increase of variations, and decreasing noise margins, among others. A promising solution for bringing the reliability of circuits back to a desired level is the use of design methods which introduce tolerance against possible faults in an integrated circuit. This thesis studies and presents fault tolerance methods for network-onchip (NoC) which is a design paradigm targeted for very large systems-onchip. In a NoC resources, such as processors and memories, are connected to a communication network; comparable to the Internet. Fault tolerance in such a system can be achieved at many abstraction levels. The thesis studies the origin of faults in modern technologies and explains the classification to transient, intermittent and permanent faults. A survey of fault tolerance methods is presented to demonstrate the diversity of available methods. Networks-on-chip are approached by exploring their main design choices: the selection of a topology, routing protocol, and flow control method. Fault tolerance methods for NoCs are studied at different layers of the OSI reference model. The data link layer provides a reliable communication link over a physical channel. Error control coding is an efficient fault tolerance method especially against transient faults at this abstraction level. Error control coding methods suitable for on-chip communication are studied and their implementations presented. Error control coding loses its effectiveness in the presence of intermittent and permanent faults. Therefore, other solutions against them are presented. The introduction of spare wires and split transmissions are shown to provide good tolerance against intermittent and permanent errors and their combination to error control coding is illustrated. At the network layer positioned above the data link layer, fault tolerance can be achieved with the design of fault tolerant network topologies and routing algorithms. Both of these approaches are presented in the thesis together with realizations in the both categories. The thesis concludes that an optimal fault tolerance solution contains carefully co-designed elements from different abstraction levels

Palveluväylän hyödyntäminen palvelukeskeisessä arkkitehtuurissa

Palvelukeskeinen arkkitehtuuri on uusi tapa rakentaa tietojärjestelmiä. Se perustuu siihen, että logiikasta koostetaan yleiskäyttöisiä palveluita, joita tarjotaan muiden järjestelmän osien käyttöön. Tällöin samoja asioita ei tarvitse toteuttaa moneen kertaan ja järjestelmää voidaan hyödyntää tehokkaasti ja monipuolisesti. Näiden palveluiden hallinnassa voidaan hyödyntää palveluväyliä, eli ESB -tuotteita. Palveluväylät sisältävät erilaisia mekanismeja, joiden avulla palveluihin liittyvää viestiliikennettä voidaan reitittää, muokata ja valvoa eri tavoin. Nykyisissä palvelukeskeisissä toteutuksissa käytetään usein XML -kieleen pohjautuvia Web Service -määrityksiä. Ne tarjoavat ympäristöriippumattoman pohjan, joka täyttää suoraan useita palvelukeskeisen arkkitehtuurin vaatimuksia. Määritysten ympärille on myös paljon valmiita laajennuksia, joiden avulla palveluihin voidaan liittää lisätoiminnallisuutta. Lahden kaupunki lähti Fenix -projektin yhteydessä kehittämään uutta kuntien käyttöön soveltuvaa järjestelmää, joka hyödyntää palvelukeskeisen arkkitehtuurin periaatteita. Järjestelmä jaettiin selkeisiin kerroksiin siten, että käyttöliittymä erotettiin palvelulogiikoista palveluväylän avulla. Tällöin järjestelmä saatiin jaettua loogisiin kokonaisuuksiin, joilla on selkeä rooli. Taustapalvelut hoitavat käsitteiden hallinnan, sekä niihin liittyvät liiketoimintasäännöt. Käyttöliittymäkerros hoitaa tiedon esittämisen ja tarjoaa graafisen, selainpohjaisen käyttöliittymän palveluihin. Palveluväylä hoitaa liikenteen reitittämisen, sekä huolehtii palveluihin liittyvistä käyttöoikeuksista ja tilastoinnista. Lopputuloksena on loputtomiin laajennettavissa oleva järjestelmä, jonka päälle voidaan kehittää erilaisia sähköisiä palveluita kunnan ja sen asukkaiden välille.

Supply chain costs of a small board lot: sheet cutting and logistics

Succeeding in small board lot (0-20 tons) deliveries, is not always prosperous and failures as well as extra costs compared to standard costs arise. Failure deliveries from converting plants to customer locations tie a lot of unwanted and unexpected costs. Extra costs are handled as quality costs and more precise, internal failure costs. These costs revolve from unsuccessful truck payloads, redundant warehousing or unfavorable routing as examples. Quality costs are becoming more and more important factor in company’s financial decision making. Actual, realized truck payload correlates with the extra costs occurring, so filling the truck payload all get-out well is a key to lower the extra costs. Case company in this study is Corporation A, business segment Boards. Boards have outsourced half of their converting in order to gain better customer service via flexibility, lead time reductions and logistics efficiency improvements. Examination period of the study is first two quarters of year 2008 and deliveries examined are from converters to the customer locations. In Corporation A’s case, the total loss in failure deliveries is hundreds of thousands of Euros during the examination period. So, the logistics goal of getting the right product to the right place and right time for the least cost, does not completely realize.

Hiilijalanjäljen laskeminen purku- ja korjausrakentamiskohteille

Tämä opinnäytetyö on tehty yhteistyössä Lappeenrannan teknillisen yliopiston ja Enviroc Oy:n kanssa. Työn tarkoituksena on ollut kehittää suomalaisiin olosuhteisiin soveltuva laskentamalli purku- ja korjausrakentamiskohteiden hiilijalanjäljelle. Kehitettyä mallia voi käyttää yrityksessä lainsäädännön vaatimusten noudattamisen todentamiseen sekä purku- ja korjausrakentamiskohteiden toimintatapojen vertailuun. Työssä käsitellään purku- ja korjausrakentamiskohteiden hiilijalanjälkeen vaikuttavia asioita, joita ovat työmaan energiankulutus sekä syntyvien jätteiden lajittelu, kuljetukset, käsittely ja hyödyntäminen tai loppusijoitus. Laskentamalli on kehitetty laskemalla esimerkkikohteille hiilijalanjäljet elinkaarimallintamisen avulla. Työssä on tarkasteltu myös vaihtoehtoisia jäteskenaarioita sekä laskentamallin luotettavuutta. Työn lopputuloksena on saatu kolmen eri kokoluokan esimerkkikohteen hiilijalanjäljet ja laskentamallin periaatekaaviot. Jätteiden toimituspisteiden ja jätejakeiden kulkureittien vaihtelevuuden sekä eri kohteista muodostuvien erityyppisten jätejakeiden johdosta yhden kokonaisvaltaisen laskentamallin kehittäminen on haasteellista. Myös tietojen hankinta kohteista ja jatkokäsittelyistä ja etenkin primääritietojen saaminen on ongelmallista. Tämänhetkinen laskentamalli perustuu enimmäkseen sekundääritietoihin ja arvioihin, joten mallin luotettavuuden lisäämiseksi olisi panostettava primääritiedon määrän lisäämiseen. Laskennan perusteella jäteskenaariovaihtoehdoista lajitteleva toimintamalli osoittautui hiilijalanjäljen kannalta suotuisimmaksi pienemmissä kohteissa ja käsittelylaitospainotteinen malli suuressa kohteessa. Merkittäviä tekijöitä kohteiden hiilijalanjälkien muodostumiselle olivat metallien käsittely, jätteiden poltto sekä neitsytraaka-aineista valmistetun teräksen ja fossiilisten polttoaineiden vältetyt päästöt. Merkittävimmiksi kasvihuonekaasuiksi purku- ja korjausrakentamiskohteiden laskennassa osoittautuivat hiilidioksidin lisäksi halogenoidut hiilivedyt ja metaani.

Exploring Adaptive Implementation of On-Chip Networks

As technology geometries have shrunk to the deep submicron regime, the communication delay and power consumption of global interconnections in high performance Multi- Processor Systems-on-Chip (MPSoCs) are becoming a major bottleneck. The Network-on- Chip (NoC) architecture paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues such as performance limitations of long interconnects and integration of large number of Processing Elements (PEs) on a chip. The choice of routing protocol and NoC structure can have a significant impact on performance and power consumption in on-chip networks. In addition, building a high performance, area and energy efficient on-chip network for multicore architectures requires a novel on-chip router allowing a larger network to be integrated on a single die with reduced power consumption. On top of that, network interfaces are employed to decouple computation resources from communication resources, to provide the synchronization between them, and to achieve backward compatibility with existing IP cores. Three adaptive routing algorithms are presented as a part of this thesis. The first presented routing protocol is a congestion-aware adaptive routing algorithm for 2D mesh NoCs which does not support multicast (one-to-many) traffic while the other two protocols are adaptive routing models supporting both unicast (one-to-one) and multicast traffic. A streamlined on-chip router architecture is also presented for avoiding congested areas in 2D mesh NoCs via employing efficient input and output selection. The output selection utilizes an adaptive routing algorithm based on the congestion condition of neighboring routers while the input selection allows packets to be serviced from each input port according to its congestion level. Moreover, in order to increase memory parallelism and bring compatibility with existing IP cores in network-based multiprocessor architectures, adaptive network interface architectures are presented to use multiple SDRAMs which can be accessed simultaneously. In addition, a smart memory controller is integrated in the adaptive network interface to improve the memory utilization and reduce both memory and network latencies. Three Dimensional Integrated Circuits (3D ICs) have been emerging as a viable candidate to achieve better performance and package density as compared to traditional 2D ICs. In addition, combining the benefits of 3D IC and NoC schemes provides a significant performance gain for 3D architectures. In recent years, inter-layer communication across multiple stacked layers (vertical channel) has attracted a lot of interest. In this thesis, a novel adaptive pipeline bus structure is proposed for inter-layer communication to improve the performance by reducing the delay and complexity of traditional bus arbitration. In addition, two mesh-based topologies for 3D architectures are also introduced to mitigate the inter-layer footprint and power dissipation on each layer with a small performance penalty.

Exploration and Design of Power-Efficient Networked Many-Core Systems

Multiprocessing is a promising solution to meet the requirements of near future applications. To get full benefit from parallel processing, a manycore system needs efficient, on-chip communication architecture. Networkon- Chip (NoC) is a general purpose communication concept that offers highthroughput, reduced power consumption, and keeps complexity in check by a regular composition of basic building blocks. This thesis presents power efficient communication approaches for networked many-core systems. We address a range of issues being important for designing power-efficient manycore systems at two different levels: the network-level and the router-level. From the network-level point of view, exploiting state-of-the-art concepts such as Globally Asynchronous Locally Synchronous (GALS), Voltage/ Frequency Island (VFI), and 3D Networks-on-Chip approaches may be a solution to the excessive power consumption demanded by today’s and future many-core systems. To this end, a low-cost 3D NoC architecture, based on high-speed GALS-based vertical channels, is proposed to mitigate high peak temperatures, power densities, and area footprints of vertical interconnects in 3D ICs. To further exploit the beneficial feature of a negligible inter-layer distance of 3D ICs, we propose a novel hybridization scheme for inter-layer communication. In addition, an efficient adaptive routing algorithm is presented which enables congestion-aware and reliable communication for the hybridized NoC architecture. An integrated monitoring and management platform on top of this architecture is also developed in order to implement more scalable power optimization techniques. From the router-level perspective, four design styles for implementing power-efficient reconfigurable interfaces in VFI-based NoC systems are proposed. To enhance the utilization of virtual channel buffers and to manage their power consumption, a partial virtual channel sharing method for NoC routers is devised and implemented. Extensive experiments with synthetic and real benchmarks show significant power savings and mitigated hotspots with similar performance compared to latest NoC architectures. The thesis concludes that careful codesigned elements from different network levels enable considerable power savings for many-core systems.

Loviisan ydinvoimalaitoksen kaapelireittien tiedonhallinnan kehittäminen paloriskitutkimusta varten

Tässä diplomityössä kehitetään Loviisan voimalaitoksen todennäköisyyspohjaisen paloriskianalyysin kaapelitietokantaa tulevaisuuden haasteita varten. Tietokannan kehittämistä varten tutustutaan todennäköisyyspohjaiseen riskianalyysiin varsin-kin paloriskianalyysin osalta. Käytännönläheisempää kehittämistä varten tutustu-taan voimalaitoksella nykyisin käytössä oleviin kaapelitietokantoihin: paloriski-tutkimusta varten laadittuun PSA-ELTIEen, kunnossapidon tiedonhallintajärjes-telmä LOMAXiin, sähkö- ja automaatiosuunnitteluyksikköjen arkistoihin sekä automaatiouudistuksen tietokantaan. Tietokannan käytännönläheisempien ominai-suuksien selvittämiseksi voimalaitoksella kokeiltiin kenttätarkastusmenetelmää, joka on ensisijainen kaapelikartoitusmenetelmä. Tietokantoihin tutustumisen perusteella vaihtoehtoisiksi tulevaisuuden tietokan-noiksi mietittiin LOMAXia, PSA-ELTIEtä tai uutta tietokantaa. Tulevaisuuden tietokantavaihtoehdoksi on päädytty ehdottamaan LOMAXia, joka vaatii vähem-män muutoksia muihin vaihtoehtoihin nähden. Tällainen laajalti käytössä oleva yhteinen tietokanta mahdollistaa sen, että tiedot ovat helpommin ja varmemmin kaikkien niitä tarvitsevien käytettävissä ja asiantuntijoiden muokattavissa, millä myös varmistetaan tietojen oikeellisuutta ja pysymistä ajan tasalla. Tulevaan LOMAX päivitykseen on ehdotettu tarpeellisia tietokenttien lisäyksiä ja kaapeli-hierarkian parantamista kaapelitietokannaksi käyttöönottamista varten.

Asiakastarpeiden kartoitus kuljetusten häiriöiden analysoinnin ja hallinnan kehittämiseksi

Tämä diplomityö on tehty osana Logproof-tutkimushanketta, joka keskittyy häiriöttömyyden hallintaan logistisissa monitoimijaverkostoissa. Työn tavoitteena on selvittää logistiikkaintensiivisten yritysten tarpeita kuljetusten häiriöiden analysoinnin ja hallinnan kehittämiseksi ja siten ennakoivan riskienhallinnan edistämiseksi. Asiakastarvetietoa on kerätty hyödyntäen puolistrukturoituja haastatteluja ja tietoa on analysoitu käyttäen hyväksi sisällönanalyysiä sekä tulkintataulukkoa. Kiinnostus kuljetusten häiriöitä ja niiden analysointia kohtaan on kasvamassa ja yrityksissä tiedostetaan hallintajärjestelmien ja analysoinnin tarve tulevaisuudessa. Kirjallisuuskatsauksen ja asiakastarpeiden kartoituksen avulla työssä on selvitetty yritysten nykytilaa kuljetusten häiriöiden hallinnan ja analysoinnin osalta ja tarkasteltu mahdollisia tulevaisuuden kehityssuuntia analysoimalla asiakkaiden näkyviä ja piileviä tarpeita. Työssä on edellisten lisäksi tarkasteltu, kuinka havaitut asiakastarpeet ovat sovitettavissa yhteen case-yrityksen, Oy Lars Krogius Ab:n, ARS (Analytic Rou-ting Solution) -palvelun ominaispiirteiden kanssa. Työ tarjoaa tarvetietoa palvelun tulevaisuuden kehitykselle.

On Energy Efficient Computing Platforms

In accordance with the Moore's law, the increasing number of on-chip integrated transistors has enabled modern computing platforms with not only higher processing power but also more affordable prices. As a result, these platforms, including portable devices, work stations and data centres, are becoming an inevitable part of the human society. However, with the demand for portability and raising cost of power, energy efficiency has emerged to be a major concern for modern computing platforms. As the complexity of on-chip systems increases, Network-on-Chip (NoC) has been proved as an efficient communication architecture which can further improve system performances and scalability while reducing the design cost. Therefore, in this thesis, we study and propose energy optimization approaches based on NoC architecture, with special focuses on the following aspects. As the architectural trend of future computing platforms, 3D systems have many bene ts including higher integration density, smaller footprint, heterogeneous integration, etc. Moreover, 3D technology can signi cantly improve the network communication and effectively avoid long wirings, and therefore, provide higher system performance and energy efficiency. With the dynamic nature of on-chip communication in large scale NoC based systems, run-time system optimization is of crucial importance in order to achieve higher system reliability and essentially energy efficiency. In this thesis, we propose an agent based system design approach where agents are on-chip components which monitor and control system parameters such as supply voltage, operating frequency, etc. With this approach, we have analysed the implementation alternatives for dynamic voltage and frequency scaling and power gating techniques at different granularity, which reduce both dynamic and leakage energy consumption. Topologies, being one of the key factors for NoCs, are also explored for energy saving purpose. A Honeycomb NoC architecture is proposed in this thesis with turn-model based deadlock-free routing algorithms. Our analysis and simulation based evaluation show that Honeycomb NoCs outperform their Mesh based counterparts in terms of network cost, system performance as well as energy efficiency.

Design Space Exploration for MPSoC Architectures

Multiprocessor system-on-chip (MPSoC) designs utilize the available technology and communication architectures to meet the requirements of the upcoming applications. In MPSoC, the communication platform is both the key enabler, as well as the key differentiator for realizing efficient MPSoCs. It provides product differentiation to meet a diverse, multi-dimensional set of design constraints, including performance, power, energy, reconfigurability, scalability, cost, reliability and time-to-market. The communication resources of a single interconnection platform cannot be fully utilized by all kind of applications, such as the availability of higher communication bandwidth for computation but not data intensive applications is often unfeasible in the practical implementation. This thesis aims to perform the architecture-level design space exploration towards efficient and scalable resource utilization for MPSoC communication architecture. In order to meet the performance requirements within the design constraints, careful selection of MPSoC communication platform, resource aware partitioning and mapping of the application play important role. To enhance the utilization of communication resources, variety of techniques such as resource sharing, multicast to avoid re-transmission of identical data, and adaptive routing can be used. For implementation, these techniques should be customized according to the platform architecture. To address the resource utilization of MPSoC communication platforms, variety of architectures with different design parameters and performance levels, namely Segmented bus (SegBus), Network-on-Chip (NoC) and Three-Dimensional NoC (3D-NoC), are selected. Average packet latency and power consumption are the evaluation parameters for the proposed techniques. In conventional computing architectures, fault on a component makes the connected fault-free components inoperative. Resource sharing approach can utilize the fault-free components to retain the system performance by reducing the impact of faults. Design space exploration also guides to narrow down the selection of MPSoC architecture, which can meet the performance requirements with design constraints.