Test hardware del primo batch di schede rod per l'esperimento atlas ibl.

L’acceleratore di particelle LHC, al CERN di Ginevra, permette studi molto rilevanti nell'ambito della fisica subnucleare. L’importanza che ricopre in questo campo il rivelatore è grandissima ed è per questo che si utilizzano tecnologie d’avanguardia nella sua costruzione. É altresì fondamentale disporre di un sistema di acquisizione dati quanto più moderno ma sopratutto efficiente. Tale sistema infatti è necessario per gestire tutti i segnali elettrici che derivano dalla conversione dell’evento fisico, passaggio necessario per rendere misurabili e quantificabili le grandezze di interesse. In particolare in questa tesi viene seguito il lavoro di test delle schede ROD dell’esperimento ATLAS IBL, che mira a verificare la loro corretta funzionalità, prima che vengano spedite nei laboratori del CERN. Queste nuove schede gestiscono i segnali in arrivo dal Pixel Detector di ATLAS, per poi inviarli ai computer per la successiva elaborazione. Un sistema simile era già implementato e funzionante, ma il degrado dei chip ha causato una perdita di prestazioni, che ha reso necessario l’inserimento di un layer aggiuntivo. Il nuovo strato di rivelatori a pixel, denominato Insertable Barrel Layer (IBL), porta così un aggiornamento tecnologico e prestazionale all'interno del Pixel Detector di ATLAS, andando a ristabilire l’efficacia del sistema.

Many-Core Architectures: Hardware-Software Optimization and Modeling Techniques

During the last few decades an unprecedented technological growth has been at the center of the embedded systems design paramount, with Moore’s Law being the leading factor of this trend. Today in fact an ever increasing number of cores can be integrated on the same die, marking the transition from state-of-the-art multi-core chips to the new many-core design paradigm. Despite the extraordinarily high computing power, the complexity of many-core chips opens the door to several challenges. As a result of the increased silicon density of modern Systems-on-a-Chip (SoC), the design space exploration needed to find the best design has exploded and hardware designers are in fact facing the problem of a huge design space. Virtual Platforms have always been used to enable hardware-software co-design, but today they are facing with the huge complexity of both hardware and software systems. In this thesis two different research works on Virtual Platforms are presented: the first one is intended for the hardware developer, to easily allow complex cycle accurate simulations of many-core SoCs. The second work exploits the parallel computing power of off-the-shelf General Purpose Graphics Processing Units (GPGPUs), with the goal of an increased simulation speed. The term Virtualization can be used in the context of many-core systems not only to refer to the aforementioned hardware emulation tools (Virtual Platforms), but also for two other main purposes: 1) to help the programmer to achieve the maximum possible performance of an application, by hiding the complexity of the underlying hardware. 2) to efficiently exploit the high parallel hardware of many-core chips in environments with multiple active Virtual Machines. This thesis is focused on virtualization techniques with the goal to mitigate, and overtake when possible, some of the challenges introduced by the many-core design paradigm.

OpenMP task scheduling strategies to mitigate hardware variability in tightly-coupled shared memory clusters

In questa tesi sono stati apportati due importanti contributi nel campo degli acceleratori embedded many-core. Abbiamo implementato un runtime OpenMP ottimizzato per la gestione del tasking model per sistemi a processori strettamente accoppiati in cluster e poi interconnessi attraverso una network on chip. Ci siamo focalizzati sulla loro scalabilità e sul supporto di task di granularità fine, come è tipico nelle applicazioni embedded. Il secondo contributo di questa tesi è stata proporre una estensione del runtime di OpenMP che cerca di prevedere la manifestazione di errori dati da fenomeni di variability tramite una schedulazione efficiente del carico di lavoro.

Test hardware del secondo batch di schede ROD per il layer 2 del pixel detector dell'esperimento ATLAS al CERN

In questa tesi viene seguito il lavoro di test delle schede ROD del layer 2 del Pixel Detector dell’ esperimento ATLAS, che mira a verificare la loro corretta funzionalità, prima che vengano spedite nei laboratori del CERN. Queste nuove schede gestiscono i segnali in arrivo dal Pixel Detector di ATLAS, per poi inviarli ai computer per la successiva elaborazione. Le schede ROD andranno a sostituire le precedenti schede SiROD nella catena di acquisizione dati dell’esperimento, procedendo dal nuovo strato IBL, e proseguendo con i tre layer del Pixel Detector, corroborando l’aggiornamento tecnologico e prestazionale necessario in vista dell’incremento di luminosità dell’esperimento.

Realizzazione di un sistema di automazione domotica con tecnologia open-hardware

Il termine Domotica deriva dall’unione dei termini domus e robotics e spazia oltre alle competenze in ambito informatico ed elettronico, avvalendosi dell’architettura e di determinati campi dell’ingegneria come: energetica, edile, dell’ automazione, elettrotecnica, delle telecomunicazioni. La Domotica agevola gli aspetti della quotidianità all’interno dell’ambiente casalingo o, più in generale, di ambienti antropizzati. Questa tesi ha l’intento di spiegare come può essere realizzato un sistema domotizzato casalingo utilizzando dispositivi open-hardware. Inizialmente verranno messi in chiaro i concetti chiave generici di un sistema domotico e verranno discussi i prodotti attualmente in commercio e verrà fatta una piccola introduzione sul concetto di open-hardware. Successivamente verrà discusso il sistema realizzato dandone una panoramica, si esaminerà la strutturazione sia software che hardware e le tecnologie ed i dispositivi utilizzati, per poi enucleare casi d’uso. A seguire le conclusioni.

Hardware accelerated ray cast of volume data and volume gradient for an optimized splines-based multi-resolution 2D-3D registration

This paper describes a method for DRR generation as well as for volume gradients projection using hardware accelerated 2D texture mapping and accumulation buffering and demonstrates its application in 2D-3D registration of X-ray fluoroscopy to CT images. The robustness of the present registration scheme are guaranteed by taking advantage of a coarse-to-fine processing of the volume/image pyramids based on cubic B-splines. A human cadaveric spine specimen together with its ground truth was used to compare the present scheme with a purely software-based scheme in three aspects: accuracy, speed, and capture ranges. Our experiments revealed an equivalent accuracy and capture ranges but with much shorter registration time with the present scheme. More specifically, the results showed 0.8 mm average target registration error, 55 second average execution time per registration, and 10 mm and 10° capture ranges for the present scheme when tested on a 3.0 GHz Pentium 4 computer.

Potential for hardware-based techniques for reuse distance analysis

Reuse distance analysis, the prediction of how many distinct memory addresses will be accessed between two accesses to a given address, has been established as a useful technique in profile-based compiler optimization, but the cost of collecting the memory reuse profile has been prohibitive for some applications. In this report, we propose using the hardware monitoring facilities available in existing CPUs to gather an approximate reuse distance profile. The difficulties associated with this monitoring technique are discussed, most importantly that there is no obvious link between the reuse profile produced by hardware monitoring and the actual reuse behavior. Potential applications which would be made viable by a reliable hardware-based reuse distance analysis are identified.

Development of Hardware-In-the-Loop Simulation System for Hybrid Electric Vehicle Study

The development of embedded control systems for a Hybrid Electric Vehicle (HEV) is a challenging task due to the multidisciplinary nature of HEV powertrain and its complex structures. Hardware-In-the-Loop (HIL) simulation provides an open and convenient environment for the modeling, prototyping, testing and analyzing HEV control systems. This thesis focuses on the development of such a HIL system for the hybrid electric vehicle study. The hardware architecture of the HIL system, including dSPACE eDrive HIL simulator, MicroAutoBox II and MotoTron Engine Control Module (ECM), is introduced. Software used in the system includes dSPACE Real-Time Interface (RTI) blockset, Automotive Simulation Models (ASM), Matlab/Simulink/Stateflow, Real-time Workshop, ControlDesk Next Generation, ModelDesk and MotoHawk/MotoTune. A case study of the development of control systems for a single shaft parallel hybrid electric vehicle is presented to summarize the functionality of this HIL system.

Hierarchical Markov Random Fields Applied to Model Soft Tissue Deformations on Graphics Hardware

Many methodologies dealing with prediction or simulation of soft tissue deformations on medical image data require preprocessing of the data in order to produce a different shape representation that complies with standard methodologies, such as mass–spring networks, finite element method s (FEM). On the other hand, methodologies working directly on the image space normally do not take into account mechanical behavior of tissues and tend to lack physics foundations driving soft tissue deformations. This chapter presents a method to simulate soft tissue deformations based on coupled concepts from image analysis and mechanics theory. The proposed methodology is based on a robust stochastic approach that takes into account material properties retrieved directly from the image, concepts from continuum mechanics and FEM. The optimization framework is solved within a hierarchical Markov random field (HMRF) which is implemented on the graphics processor unit (GPU See Graphics processing unit ).

Rendering Falling Leaves on Graphics Hardware

There is a growing interest in simulating natural phenomena in computer graphics applications. Animating natural scenes in real time is one of the most challenging problems due to the inherent complexity of their structure, formed by millions of geometric entities, and the interactions that happen within. An example of natural scenario that is needed for games or simulation programs are forests. Forests are difficult to render because the huge amount of geometric entities and the large amount of detail to be represented. Moreover, the interactions between the objects (grass, leaves) and external forces such as wind are complex to model. In this paper we concentrate in the rendering of falling leaves at low cost. We present a technique that exploits graphics hardware in order to render thousands of leaves with different falling paths in real time and low memory requirements.

Manifiesto : algunas ideas del grupo en relación al rol del diseño gráfico en el contexto de la Argentina actual

Fil: Grupo GRAPO.

El diseño en función social : transferencia de un proyecto final de la carrera de Diseño Gráfico : sistema señalético del Hospital del Niño Jesús de la Ciudad de San Miguel de Tucumán

Fil: Castro, Edgardo. Universidad Nacional de Cuyo. Facultad de Artes y Diseño