On designing linearly tunable high-Q OTA-C filters with low sensitivity

This paper discusses a design approach for a high-Q low-sensitivity OTA-C biquad bandpass section. An optimal relationship is established between transconductances defining the differenceβ - γ in the Q-factor denominator, setting the Q-sensitivity to tuning voltages around unity. A 30-MHz filter was designed based on a 0.35μn CMOS process and VDD=3.3V. A range of circuit simulation supports the theoretical analysis. Q-factor spans from 20.5 to 60, while ensuring filter stability along the tuning range. Although a Mode-operating OTA is used, the procedure can be extended to other types of transconductor.

A low-voltage low-sensitivity sinusoidal VCO for DPLL realizations

A quasi-sinusoidal linearly tunable OTA-C VCO built with triode-region transconductors is presented. Oscillation upon power-on is ensured by RHP poles associated with gate-drain capacitances of OTA input devices. Since the OTA nonlinearity stabilizes the amplitude, the oscillation frequency f0 is first-order independent of VDD, making the VCO adequate to mixed-mode designs. A range of simulations attests the theoretical analysis. As part of a DPLL, the VCO was prototyped on a 0.8μm CMOS process, occupying an area of 0.15mm2. Nominal f0 is 1MHz, with K VCo=8.4KHz/mV. Measured sensitivity to VDD is below 2.17, while phase noise is -86dBc at 100-KHz offset. The feasibility of the VCO for higher frequencies is verified by a redesign based on a 0.35μm CMOS process and VDD=3.3V, with a linear frequency-span of l3.2MHz - 61.5MHz.

A Gm-C bump equalizer for low-voltage low-power applications

A low-voltage low-power 2nd-order CMOS pseudo-differential bump-equalizer is presented. Its topology comprises a bandpass section with adjustable center frequency and quality factor, together with a programmable current amplifier. The basic building blocks are triode-operating transconductors, tunable by means of either a DC voltage or a digitally controlled current divider. The bump-equalizer as part of a battery-operated hearing aid device is designed for a 1.4V-supply and a 0.35μm CMOS fabrication process. The circuit performance is supported by a set of simulation results, which indicates a center frequency from 600Hz to 2.4kHz, 1≤Q≤5, and an adjustable gain within ±6dB at center frequency. The filter dynamic range lies around 40dB. Quiescent consumption is kept below 12μW for any configuration of the filter.

Common architecture for discrete wavelet transform analysis and synthesis with sequential and constant processing elements

This paper adresses the problem on processing biological data such as cardiac beats, audio and ultrasonic range, calculating wavelet coefficients in real time, with processor clock running at frequency of present ASIC's and FPGA. The Paralell Filter Architecture for DWT has been improved, calculating wavelet coefficients in real time with hardware reduced to 60%. The new architecture, which also processes IDWT, is implemented with the Radix-2 or the Booth-Wallace Constant multipliers. Including series memory register banks, one integrated circuit Signal Analyzer, ultrasonic range, is presented.

Effects of the thyristor controlled serie capacitor on the electric power system

This work deals with the effects of the series compensation on the electric power system for small-signal stability studies. Therefore, the system is modeled admitting the existence of the compensation and then, the equations are linearized and a linear model is obtained for a single machine-infinite bus power system with a compensator installed. The resulting model with nine defined constants is very similar to the Heffron & Phillips linear model widely used on the existent literature. Finally, simulations are executed for an example system, to analyze the behavior of these constants when loading the system. © 2004 IEEE.

An active/reactive predispatch model incorporating ramp rate constraints solved by dual decomposition/lagrangian relaxation

The Predispatch model (PD) calculates a short-term generation policy for power systems. In this work a PD model is proposed that improves two modeling aspects generally neglected in the literature: voltage/reactive power constraints and ramp rate constraints for generating units. Reactive power constraints turn the PD into a non-linear problem and the ramp rate constraints couple the problem dynamically in time domain. The solution of the PD is turned into a harder task when such constraints are introduced. The dual decomposition/ lagrangian relaxation technique is used in the solution approach for handing dynamic constraints. As a result the PD is decomposed into a series of independent Optimal Power Flow (FPO) sub problems, in which the reactive power is represented in detail. The solution of the independent FPO is coordinated by means of Lagrange multipliers, so that dynamic constraints are iteratively satisfied. Comparisons between dispatch policies calculated with and without the representation of ramp rate constraints are performed, using the IEEE 30 bus test system. The results point-out the importance of representing such constraints in the generation dispatch policy. © 2004 IEEE.

Dielectric and ferroelectric properties of PZT and PT thin films for saw sensors applications

It is very important for the building of the SAW devices to study dielectric and ferroelectrics properties because every SAW device is based in piezoelectric effect that it is made up to transform an electric sign in the mechanical or acoustic sign and a mechanical or acoustic sign in an electric sign. Thus, the purpose of the present work is to prepare PbZr 0,53Ti0.47O3 (PZT) and PbTiO3 (PT) thin films on the Si (100) substrates across spin-coating using a chemical method based in polymeric precursors. After conventional treatment in the furnace, the films were characterized by impedance spectroscopy and hysteresis loops to know its dielectric and ferroelectric properties.

Artificial immune systems applied to optimal capacitor placement in radial distribution networks

The capacitor placement problem for radial distribution networks aims to determine capacitor types, sizes, locations and control scheme. This is a combinatorial problem that can be formulated as a mixed integer nonlinear program. The paper presents an algorithm inspired in artificial immune systems and developed for this specific problem. A good performance was obtained through experimental tests applied to known systems. © 2006 IEEE.

Heuristic algorithm to solve the short term transmission network expansion planning

In this paper, a method for solving the short term transmission network expansion planning problem is presented. This is a very complex mixed integer nonlinear programming problem that presents a combinatorial explosion in the search space. In order to And a solution of excellent quality for this problem, a constructive heuristic algorithm is presented in this paper. In each step of the algorithm, a sensitivity index is used to add a circuit (transmission line or transformer) or a capacitor bank (fixed or variable) to the system. This sensitivity index is obtained solving the problem considering the numbers of circuits and capacitors banks to be added (relaxed problem), as continuous variables. The relaxed problem is a large and complex nonlinear programming and was solved through a higher order interior point method. The paper shows results of several tests that were performed using three well-known electric energy systems in order to show the possibility and the advantages of using the AC model. ©2007 IEEE.

Development of a DC-DC converter for DC bus voltage control of series connected device

The purpose of this work is to study voltage control and energy balance of a split DC bus topology within a power electronics equipment connected to the AC mains, such as UPS systems, wind power generators, active filters and FACTS devices. A typical configuration in such equipment has two mains connected converters sharing a common DC bus, one series connected and the other parallel connected. The DC bus is usually composed by a battery or a capacitor bank. In the proposed topology, the DC bus is divided in two sides, interconnected with a buck-boost converter, which controls power flow and DC voltage on both sides. © 2009 IEEE.

Hardware implementation of type-2 programmable fuzzifier

The design of full programmable type-2 membership function circuit is presented in this paper. This circuit is used to implement the fuzzifier block of Type-2 Fuzzy Logic Controller chip. In this paper the type-2 fuzzy set was obtained by blurring the width of the type-1 fuzzy set. This circuit allows programming the height and the shape of the membership function. It operates in current mode, with supply voltage of 3.3V. The simulation results of interval type-2 membership function circuit have been done in CMOS 0.35μm technology using Mentor Graphics software. © 2011 IEEE.

Bandgap voltage reference with low susceptibility to electromagnetic interference (EMI)

In this paper, the susceptibility of a current-mode bandgap voltage reference to electromagnetic interference (EMI) superimposed to the power supply is investigated by simulation. Designed for AMS 0.35 CMOS process, the circuit provides a stable voltage reference in the temperature range of -40-150°C. When EMI disturbances are present, the circuit exhibits only 6.7 mV of offset for interfering signals in the frequency range of 150 kHz-1 GHz. © 2011 ACM.

Short-term planning of electric power distribution networks using multiobjective genetic algorithim

The high active and reactive power level demanded by the distribution systems, the growth of consuming centers, and the long lines of the distribution systems result in voltage variations in the busses compromising the quality of energy supplied. To ensure the energy quality supplied in the distribution system short-term planning, some devices and actions are used to implement an effective control of voltage, reactive power, and power factor of the network. Among these devices and actions are the voltage regulators (VRs) and capacitor banks (CBs), as well as exchanging the conductors sizes of distribution lines. This paper presents a methodology based on the Non-Dominated Sorting Genetic Algorithm (NSGA-II) for optimized allocation of VRs, CBs, and exchange of conductors in radial distribution systems. The Multiobjective Genetic Algorithm (MGA) is aided by an inference process developed using fuzzy logic, which applies specialized knowledge to achieve the reduction of the search space for the allocation of CBs and VRs.

Resonant (P+RES) controller applied to voltage source inverter with minimum DC link capacitor

Voltage source inverters use large electrolytic capacitors in order to decouple the energy between the utility and the load, keeping the DC link voltage constant. Decreasing the capacitance reduces the distortion in the inverter input current but this also affects the load with low-order harmonics and generate disturbances at the input voltage. This paper applies the P+RES controller to solve the challenge of regulating the output current by means of controlling the magnitude of the current space vector, keeping it constant thus rejecting harmonic disturbances that would otherwise propagate to the load. This work presents a discussion of the switching and control strategy. © 2011 IEEE.

Differential mixer with NMOS/PMOS stack at switching stage

This paper proposes a novel differential mixer topology. The traditional stage of switching is replaced by a stack of NMOS and PMOS transistors combined. A design is given of a 900 MHz down-conversion mixer using a 0.35 μm CMOS process. Comparison with conventional mixer shows that the topology leads to a better performance in terms of conversion gain and linearity. ©2012 IEEE.