967 resultados para Voltage ripples


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Current methods for molecular simulations of Electric Double Layer Capacitors (EDLC) have both the electrodes and the electrolyte region in a single simulation box. This necessitates simulation of the electrode-electrolyte region interface. Typical capacitors have macroscopic dimensions where the fraction of the molecules at the electrode-electrolyte region interface is very low. Hence, large systems sizes are needed to minimize the electrode-electrolyte region interfacial effects. To overcome these problems, a new technique based on the Gibbs Ensemble is proposed for simulation of an EDLC. In the proposed technique, each electrode is simulated in a separate simulation box. Application of periodic boundary conditions eliminates the interfacial effects. This in addition to the use of constant voltage ensemble allows for a more convenient comparison of simulation results with experimental measurements on typical EDLCs. (C) 2014 AIP Publishing LLC.

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Non-crystalline semiconductor based thin film transistors are the building blocks of large area electronic systems. These devices experience a threshold voltage shift with time due to prolonged gate bias stress. In this paper we integrate a recursive model for threshold voltage shift with the open source BSIM4V4 model of AIM-Spice. This creates a tool for circuit simulation for TFTs. We demonstrate the integrity of the model using several test cases including display driver circuits.

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This paper studies the feasibility of utilizing the reactive power of grid-connected variable-speed wind generators to enhance the steady-state voltage stability margin of the system. Allowing wind generators to work at maximum reactive power limit may cause the system to operate near the steady-state stability limit, which is undesirable. This necessitates proper coordination of reactive power output of wind generators with other reactive power controllers in the grid. This paper presents a trust region framework for coordinating reactive output of wind generators-with other reactive sources for voltage stability enhancement. Case studies on 418-bus equivalent system of Indian southern grid indicates the effectiveness of proposed methodology in enhancing the steady-state voltage stability margin.

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A simple and scalable method of decorating 3D-carbon nanotube (CNT) forest with metal particles has been developed. The results observed in aluminum (AI) decorated CNTs and copper (Cu) decorated CNTs on silicon (Si) and Inconel are compared with undecorated samples. A significant improvement in the field emission characteristics of the cold cathode was observed with ultralow turn on voltage (E-to similar to 0.1 V/mu m) due to decoration of CNTs with metal nanoparticles. Contact resistance between the CNTs and the substrate has also been reduced to a large extent, allowing us to get stable emission for longer duration without any current degradation, thereby providing a possibility of their use in vacuum microelectronic devices.

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Investigations on the electrical switching, structural, optical and photoacoustic analysis have been undertaken on chalcogenide GeSe1.5S0.5 thin films of various thicknesses prepared by vacuum evaporation technique. The decrease of band gap energy with increase in film thickness has been explained using the `density of states model'. The structural units of the films are characterized using Raman spectroscopy and the deconvoluted Raman peaks obtained from Gaussian fit around 188 cm(-1), 204 cm(-1) and 214 cm(-1) favors Ge-chalcogen tetrahedral units forming corner and edge sharing tetrahedra. All the thin films samples have been exhibited memory-type electrical switching behavior. An enhancement in the threshold voltages of GeSe1.5S0.5 thin films have been observed with increase in film thickness. The thickness dependence of switching voltages provide an insight into the switching mechanism and it is explained by the Joule heating effect. (C) 2014 Elsevier B.V. All rights reserved.

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High-power voltage-source inverters (VSI) are often switched at low frequencies due to switching loss constraints. Numerous low-switching-frequency PWM techniques have been reported, which are quite successful in reducing the total harmonic distortion under open-loop conditions at such low operating frequencies. However, the line current still contains low-frequency components (though of reduced amplitudes), which are fed back to the current loop controller during closed-loop operation. Since the harmonic frequencies are quite low and are not much higher than the bandwidth of the current loop, these are amplified by the current controller, causing oscillations and instability. Hence, only the fundamental current should be fed back. Filtering out these harmonics from the measured current (before feeding back) leads to phase shift and attenuation of the fundamental component, while not eliminating the harmonics totally. This paper proposes a method for on-line extraction of the fundamental current in induction motor drives, modulated with low-switching-frequency PWM. The proposed method is validated through simulations on MATLAB/Simulink. Further, the proposed algorithm is implemented on Cyclone FPGA based controller board. Experimental results are presented for an R-L load.

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Inverter dead-time, which is meant to prevent shoot-through fault, causes harmonic distortion and change in the fundamental voltage in the inverter output. Typical dead-time compensation schemes ensure that the amplitude of the fundamental output current is as desired, and also improve the current waveform quality significantly. However, even with compensation, the motor line current waveform is observed to be distorted close to the current zero-crossings. The IGBT switching transition times being significantly longer at low currents than at high currents is an important reason for this zero-crossover distortion. Hence, this paper proposes an improved dead-time compensation scheme, which makes use of the measured IGBT switching transition times at low currents. Measured line current waveforms in a 2.2 kW induction motor drive with the proposed compensation scheme are compared against those with the conventional dead-time compensation scheme and without dead-time compensation. The experimental results on the motor drive clearly demonstrate the improvement in the line current waveform quality with the proposed method.

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Temperature dependent current-voltage (I-V) measurements of electrochemically prepared zinc oxide nanowire/polypyrrole (ZnONW/PPy) nanocomposite yielded non-linear I-V characteristics at temperatures between 300 and 4.5 K. The low-field conductance (G) of the ZnONW/PPy film exhibits pronounced temperature dependence with room temperature conductance (G(300K)) similar to 10(-3) S and a conductance ratio (G(300)K/G(4.5K)) of similar to 10(4), indicating dominance of significant temperature dependent charge transport processes. The conduction mechanism of the film is satisfactorily understood by extended fluctuation induced tunneling (FIT) model as the non-linear I-V characteristics fit fairly well to the extended FIT model. Further, the temperature dependence of G(o) obtained from fitting followed Sheng's model also. (C) 2014 AIP Publishing LLC.

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Multilevel inverters with dodecagonal (12-sided polygon) voltage space vector structure have advantages, such as complete elimination of fifth and seventh harmonics, reduction in electromagnetic interference, reduction in device voltage ratings, reduction of switching frequency, extension of linear modulation range, etc., making it a viable option for high-power medium-voltage drives. This paper proposes two power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles (for the first time) with minimum number of dc-link power supplies and floating capacitor H-bridges. The first power topology is composed of two hybrid cascaded five-level inverters connected to either side of an open-end winding induction machine. Each inverter consists of a three-level neutral-point-clamped inverter, which is cascaded with an isolated H-bridge making it a five-level inverter. The second topology is for a normal induction motor. Both of these circuit topologies have inherent capacitor balancing for floating H-bridges for all modulation indexes, including transient operations. The proposed topologies do not require any precharging circuitry for startup. A simple pulsewidth modulation timing calculation method for space vector modulation is also presented in this paper. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any offline computation, lookup tables, or angle computation. Experimental results for steady-state operation and transient operation are also presented to validate the proposed concept.

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Optimal switching angles for minimization of total harmonic distortion of line current (I-THD) in a voltage source inverter are determined traditionally by imposing half-wave symmetry (HWS) and quarter-wave symmetry (QWS) conditions on the pulse width modulated waveform. This paper investigates optimal switching angles with QWS relaxed. Relaxing QWS expands the solution space and presents the possibility of improved solutions. The optimal solutions without QWS are shown here to outperform the optimal solutions with QWS over a range of modulation index (M) between 0.82 and 0.94 for a switching frequency to fundamental frequency ratio of 5. Theoretical and experimental results are presented on a 2.3kW induction motor drive.

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This paper presents a low energy memory decoder architecture for ultra-low-voltage systems containing multiple voltage domains. Due to limitations in scalability of memory supply voltages, these systems typically contain a core operating at subthreshold voltages and memories operating at a higher voltage. This difference in voltage provides a timing slack on the memory path as the core supply is scaled. The paper analyzes the feasibility and trade-offs in utilizing this timing slack to operate a greater section of memory decoder circuitry at the lower supply. A 256x16-bit SRAM interface has been designed in UMC 65nm low-leakage process to evaluate the above technique with the core and memory operating at 280 mV and 500 mV respectively. The technique provides a reduction of up to 20% in energy/cycle of the row decoder without any penalty in area and system-delay.

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A neonatal temperature monitoring system operating in subthreshold regime that utilizes time mode signal processing is presented. Resistance deviations in a thermistor due to temperature variations are converted to delay variations that are subsequently quantized by a Delay measurement unit (DMU). The DMU does away with the need for any analog circuitry and is synthesizable entirely from digital logic. An FPGA implementation of the system demonstrates the viability of employing time mode signal processing, and measured results show that temperature resolution better than 0.1 degrees C can be achieved using this approach.

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Cell voltage for a fully charged-substrate-integrated lead-carbon hybrid ultracapacitor is about 2.3 V. Therefore, for applications requiring higher DC voltage, several of these ultracapacitors need to be connected in series. However, voltage distribution across each series-connected ultracapacitor tends to be uneven due to tolerance in capacitance and parasitic parallel-resistance values. Accordingly, voltage-management circuit is required to protect constituent ultracapacitors from exceeding their rated voltage. In this study, the design and characterization of the substrate-integrated lead-carbon hybrid ultracapacitor with co-located terminals is discussed. Voltage-management circuit for the ultracapacitor is presented, and its effectiveness is validated experimentally.

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Rechargeable batteries based on Li and Na ions have been growing leaps and bounds since their inception in the 1970s. They enjoy significant attention from both the fundamental science point of view and practical applications ranging from portable electronics to hybrid vehicles and grid storage. The steady demand for building better batteries calls for discovery, optimisation and implementation of novel positive insertion (cathode) materials. In this quest, chemists have tried to unravel many future cathode materials by taking into consideration their eco-friendly synthesis, material/process economy, high energy density, safety, easy handling and sustainability. Interestingly, sulfate-based cathodes offer a good combination of sustainable syntheses and high energy density owing to their high-voltage operation, stemming from electronegative SO42- units. This review delivers a sneak peak at the recent advances in the discovery and development of sulfate-containing cathode materials by focusing on their synthesis, crystal structure and electrochemical performance. Several family of cathodes are independently discussed. They are 1) fluorosulfates AMSO(4)F], 2) bihydrated fluorosulfates AMSO(4)F2H(2)O], 3) hydroxysulfate AMSO(4)OH], 4) bisulfates A(2)M(SO4)(2)], 5) hydrated bisulfates A(2)M(SO4)(2)nH(2)O], 6) oxysulfates Fe-2(SO4)(2)O] and 7) polysulfates A(2)M(2)(SO4)(3)]. A comparative study of these sulfate-based cathodes has been provided to offer an outlook on the future development of high-voltage polyanionic cathode materials for next-generation batteries.

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In this paper, for the first time, the key design parameters of a shallow trench isolation-based drain-extended MOS transistor are discussed for RF power applications in advanced CMOS technologies. The tradeoff between various dc and RF figures of merit (FoMs) is carefully studied using well-calibrated TCAD simulations. This detailed physical insight is used to optimize the dc and RF behavior, and our work also provides a design window for the improvement of dc as well as RF FoMs, without affecting the breakdown voltage. An improvement of 50% in R-ON and 45% in RF gain is achieved at 1 GHz. Large-signal time-domain analysis is done to explore the output power capability of the device.