Online Computation of Hysteresis Boundary for Constant Switching Frequency Current-Error Space-Vector-Based Hysteresis Controller for VSI-Fed IM Drives

This paper proposes a current-error space-vector-based hysteresis controller with online computation of boundary for two-level inverter-fed induction motor (IM) drives. The proposed hysteresis controller has got all advantages of conventional current-error space-vector-based hysteresis controllers like quick transient response, simplicity, adjacent voltage vector switching, etc. Major advantage of the proposed controller-based voltage-source-inverters-fed drive is that phase voltage frequency spectrum produced is exactly similar to that of a constant switching frequency space-vector pulsewidth modulated (SVPWM) inverter. In this proposed hysteresis controller, stator voltages along alpha- and beta-axes are estimated during zero and active voltage vector periods using current errors along alpha- and beta-axes and steady-state model of IM. Online computation of hysteresis boundary is carried out using estimated stator voltages in the proposed hysteresis controller. The proposed scheme is simple and capable of taking inverter upto six-step-mode operation, if demanded by drive system. The proposed hysteresis-controller-based inverter-fed drive scheme is experimentally verified. The steady state and transient performance of the proposed scheme is extensively tested. The experimental results are giving constant frequency spectrum for phase voltage similar to that of constant frequency SVPWM inverter-fed drive.

Aggregate download throughput for TCP-controlled long file transfers in a WLAN with multiple STA-AP association rates

We consider several WLAN stations associated at rates r(1), r(2), ... r(k) with an Access Point. Each station (STA) is downloading a long file from a local server, located on the LAN to which the Access Point (AP) is attached, using TCP. We assume that a TCP ACK will be produced after the reception of d packets at an STA. We model these simultaneous TCP-controlled transfers using a semi-Markov process. Our analytical approach leads to a procedure to compute aggregate download, as well as per-STA throughputs, numerically, and the results match simulations very well. (C) 2012 Elsevier B.V. All rights reserved.

Piecewise Linearization Technique for Compact Charge Modeling of Independent DG MOSFET

Charge linearization techniques have been used over the years in advanced compact models for bulk and double-gate MOSFETs in order to approximate the position along the channel as a quadratic function of the surface potential (or inversion charge densities) so that the terminal charges can be expressed as a compact closed-form function of source and drain end surface potentials (or inversion charge densities). In this paper, in case of the independent double-gate MOSFETs, we show that the same technique could be used to model the terminal charges quite accurately only when the 1-D Poisson solution along the channel is fully hyperbolic in nature or the effective gate voltages are same. However, for other bias conditions, it leads to significant error in terminal charge computation. We further demonstrate that the amount of nonlinearity that prevails between the surface potentials along the channel actually dictates if the conventional charge linearization technique could be applied for a particular bias condition or not. Taking into account this nonlinearity, we propose a compact charge model, which is based on a novel piecewise linearization technique and shows excellent agreement with numerical and Technology Computer-Aided Design (TCAD) simulations for all bias conditions and also preserves the source/drain symmetry which is essential for Radio Frequency (RF) circuit design. The model is implemented in a professional circuit simulator through Verilog-A, and simulation examples for different circuits verify good model convergence.

Quantum capacitance in bilayer graphene nanoribbon

We address a physically based analytical model of quantum capacitance (C-Q) in a bilayer graphene nanoribbon (BGN) under the application of an external longitudinal static bias. We demonstrate that as the gap (Delta) about the Dirac point increases, a phenomenological population inversion of the carriers in the two sets of subbands occurs. This results in a periodic and composite oscillatory behavior in the C-Q with the channel potential, which also decreases with increase in Delta. We also study the quantum size effects on the C-Q, which signatures heavy spatial oscillations due to the occurrence of van Hove singularities in the total density-of-states function of both the sets of subbands. All the mathematical results as derived in this paper converge to the corresponding well-known solution of graphene under certain limiting conditions and this compatibility is an indirect test of our theoretical formalism. (C) 2012 Elsevier By. All rights reserved.

Inclusion of body doping in compact models for fully-depleted common double gate MOSFET adapted to gate-oxide thickness asymmetry

Since it is difficult to find the analytical solution of the governing Poisson equation for double gate MOSFETs with the body doping term included, the majority of the compact models are developed for undoped-body devices for which the analytical solution is available. Proposed is a simple technique to included a body doping term in such surface potential based common double gate MOSFET models also by taking into account any differences between the gate oxide thickness. The proposed technique is validated against TCAD simulation and found to be accurate as long as the channel is fully depleted.

Theoretical estimation of electromigration in metallic carbon nanotubes considering self-heating effect

In this paper, we estimate the solution of the electromigration diffusion equation (EMDE) in isotopically pure and impure metallic single-walled carbon nanotubes (CNTs) (SWCNTs) by considering self-heating. The EMDE for SWCNT has been solved not only by invoking the dependence of the electromigration flux on the usual applied static electric field across its two ends but also by considering a temperature-dependent thermal conductivity (κ) which results in a variable temperature distribution (T) along its length due to self-heating. By changing its length and isotopic impurity, we demonstrate that there occurs a significant deviation in the SWCNT electromigration performance. However, if κ is assumed to be temperature independent, the solution may lead to serious errors in performance estimation. We further exhibit a tradeoff between length and impurity effect on the performance toward electromigration. It is suggested that, to reduce the vacancy concentration in longer interconnects of few micrometers, one should opt for an isotopically impure SWCNT at the cost of lower κ, whereas for comparatively short interconnects, pure SWCNT should be used. This tradeoff presented here can be treated as a way for obtaining a fairly well estimation of the vacancy concentration and mean time to failure in the bundles of CNT-based interconnects. © 2012 IEEE.

Bond Graph Modeling for Energy-Harvesting Wireless Sensor Networks

Researchers can use bond graph modeling, a tool that takes into account the energy conservation principle, to accurately assess the dynamic behavior of wireless sensor networks on a continuous basis.

Derating Based Hardware Optimizations in Soft Error Tolerant Designs

Ensuring reliable operation over an extended period of time is one of the biggest challenges facing present day electronic systems. The increased vulnerability of the components to atmospheric particle strikes poses a big threat in attaining the reliability required for various mission critical applications. Various soft error mitigation methodologies exist to address this reliability challenge. A general solution to this problem is to arrive at a soft error mitigation methodology with an acceptable implementation overhead and error tolerance level. This implementation overhead can then be reduced by taking advantage of various derating effects like logical derating, electrical derating and timing window derating, and/or making use of application redundancy, e. g. redundancy in firmware/software executing on the so designed robust hardware. In this paper, we analyze the impact of various derating factors and show how they can be profitably employed to reduce the hardware overhead to implement a given level of soft error robustness. This analysis is performed on a set of benchmark circuits using the delayed capture methodology. Experimental results show upto 23% reduction in the hardware overhead when considering individual and combined derating factors.

Integrated magnetics based multi-port bidirectional DC-DC converter topology for discontinuous-mode operation

A new type of multi-port isolated bidirectional DC-DC converter is proposed in this study. In the proposed converter, transfer of power takes place through addition of magnetomotive forces generated by multiple windings on a common transformer core. This eliminates the need for a centralised storage capacitor to interface all the ports. Hence, the requirement of an additional power transfer stage from the centralised capacitor can also be eliminated. The converter can be used for a multi-input, multi-output (MIMO) system. A pulse width modulation (PWM) strategy for controlling simultaneous power flow in the MIMO converter is also proposed. The proposed PWM scheme works in the discontinuous conduction mode. The leakage inductance can be chosen to aid power transfer. By using the proposed converter topology and PWM scheme, the need to compute power flow equations to determine the magnitude and direction of power flow between ports is alleviated. Instead, a simple controller structure based on average current control can be used to control the power flow. This study discusses the operating phases of the proposed multi-port converter along with its PWM scheme, the design process for each of the ports and finally experimental waveforms that validate the multi-port scheme.

Multilevel dodecagonal space-vector generation for induction motor drives by cascading three-level and two-level inverters

This study proposes an inverter circuit topology capable of generating multilevel dodecagonal (12-sided polygon) voltage space vectors by the cascaded connection of two-level and three-level inverters. By the proper selection of DC-link voltages and resultant switching states for the inverters, voltage space vectors whose tips lie on three concentric dodecagons, are obtained. A rectifier circuit for the inverter is also proposed, which significantly improves the power factor. The topology offers advantages such as the complete elimination of the fifth and seventh harmonics in phase voltages and an extension of the linear modulation range. In this study, a simple method for the calculation of pulse width modulation timing was presented along with extensive simulation and experimental results in order to validate the proposed concept.

Microstructural Evolution and Some Unusual Effects During Thermo-Mechanical Cycling of Sn-Ag-Cu Alloys

Sn-Ag-Cu (SAC) solders are susceptible to appreciable microstructural coarsening during storage or service. This results in evolution of joint properties over time, and thereby influences the long-term reliability of microelectronic packages. Accurate prediction of this aging behavior is therefore critical for joint reliability predictions. Here, we study the precipitate coarsening behavior in two Sn-Ag-Cu (SAC) alloys, namely Sn-3.0Ag-0.5Cu and Sn-1.0Cu-0.5Cu, under different thermo-mechanical excursions, including isothermal aging at 150 degrees C for various lengths of time and thermo-mechanical cycling between -25 degrees C and 125 degrees C, with an imposed shear strain of similar to 19.6% per cycle, for different number of cycles. During isothermal aging and the thermo-mechanical cycling up to 200 cycles, Ag3Sn precipitates undergo rapid, monotonous coarsening. However, high number of thermo-mechanical cycling, usually between 200 and 600 cycles, causes dissolution and re-precipitation of precipitates, resulting in a fine and even distribution. Also, recrystallization of Sn-grains near precipitate clusters was observed during severe isothermal aging. Such responses are quite unusual for SAC solder alloys. In the regime of usual precipitate coarsening in these SAC alloys, an explicit parameter, which captures the thermo-mechanical history dependence of Ag3Sn particle size, was defined. Brief mechanistic description for the recrystallization of Sn grains during isothermal aging and reprecipitation of the Ag3Sn due to high number of thermo-mechanical cycles are also presented.

SEU Tolerant Robust Memory Cell Design

The implementation of semiconductor circuits and systems in nano-technology makes it possible to achieve high speed, lower voltage level and smaller area. The unintended and undesirable result of this scaling is that it makes integrated circuits susceptible to soft errors normally caused by alpha particle or neutron hits. These events of radiation strike resulting into bit upsets referred to as single event upsets(SEU), become increasingly of concern for the reliable circuit operation in the field. Storage elements are worst hit by this phenomenon. As we further scale down, there is greater interest in reliability of the circuits and systems, apart from the performance, power and area aspects. In this paper we propose an improved 12T SEU tolerant SRAM cell design. The proposed SRAM cell is economical in terms of area overhead. It is easy to fabricate as compared to earlier designs. Simulation results show that the proposed cell is highly robust, as it does not flip even for a transient pulse with 62 times the Q(crit) of a standard 6T SRAM cell.

A physics-based flexural phonon-dependent thermal conductivity model for single layer graphene

In this paper, we address a physics-based closed-form analytical model of flexural phonon-dependent diffusive thermal conductivity (kappa) of suspended rectangular single layer graphene sheet. A quadratic dependence of the out-of-plane phonon frequency, generally called flexural phonons, on the phonon wave vector has been taken into account to analyze the behavior of kappa at lower temperatures. Such a dependence has further been used for the determination of second-order three-phonon Umklapp and isotopic scatterings. We find that these behaviors in our model are best explained through the upper limit of Debye cut-off frequency in the second-order three-phonon Umklapp scattering of the long phonon waves that actually remove the thermal conductivity singularity by contributing a constant scattering rate at low frequencies and note that the out-of-plane Gruneisen parameter for these modes need not be too high. Using this, we clearly demonstrate that. follows a T-1.5 and T-2 law at lower and higher temperatures in the absence of isotopes, respectively. However in their presence, the behavior of kappa sharply deviates from the T-2 law at higher temperatures. The present geometry-dependent model of kappa is found to possess an excellent match with various experimental data over a wide range of temperatures which can be put forward for efficient electro-thermal analyses of encased/supported graphene.

A Hybrid Five-Level Inverter With Common-Mode Voltage Elimination Having Single Voltage Source for IM Drive Applications

A new hybrid five-level inverter topology with common-mode voltage (CMV) elimination for induction motor drive is proposed in this paper. This topology has only one dc source, and different voltage levels are generated by using this voltage source along with floating capacitors charged to asymmetrical voltage levels. The pulsewidth modulation (PWM) scheme employed in this topology balances the capacitor voltages at the required levels at any power factor and modulation index while eliminating the CMV. This inverter has good fault-tolerant capability as it can be operated in three-or two-level mode with CMV elimination, in case of any failure in the H-bridges. More voltage levels with CMV elimination can be realized from this topology but only in a limited range of modulation index and power factor. Extensive simulation is done to validate the PWM technique for CMV elimination and balancing of the capacitor voltages. The experimental verification of the proposed inverter-fed induction motor is carried out in the linear modulation and overmodulation regions. The steady-state and transient operations of the drive are verified. The dynamics of the capacitor voltage balancing is also tested. The experimental results demonstrate that the proposed topology can be considered for industrial drive applications.

Smart Network Interface Selection for E-DTNs

We implement two energy models that accurately and comprehensively estimates the system energy cost and communication energy cost for using Bluetooth and Wi-Fi interfaces. The energy models running on a system is used to smartly pick the most energy optimal network interface so that data transfer between two end points is maximized.