Derating Based Hardware Optimizations in Soft Error Tolerant Designs


Autoria(s): Prasanth, V; Singh, Virendra; Parekhji, Rubin
Data(s)

2012

Resumo

Ensuring reliable operation over an extended period of time is one of the biggest challenges facing present day electronic systems. The increased vulnerability of the components to atmospheric particle strikes poses a big threat in attaining the reliability required for various mission critical applications. Various soft error mitigation methodologies exist to address this reliability challenge. A general solution to this problem is to arrive at a soft error mitigation methodology with an acceptable implementation overhead and error tolerance level. This implementation overhead can then be reduced by taking advantage of various derating effects like logical derating, electrical derating and timing window derating, and/or making use of application redundancy, e. g. redundancy in firmware/software executing on the so designed robust hardware. In this paper, we analyze the impact of various derating factors and show how they can be profitably employed to reduce the hardware overhead to implement a given level of soft error robustness. This analysis is performed on a set of benchmark circuits using the delayed capture methodology. Experimental results show upto 23% reduction in the hardware overhead when considering individual and combined derating factors.

Formato

application/pdf

Identificador

http://eprints.iisc.ernet.in/45334/1/IEEE_VLIS_2012.pdf

Prasanth, V and Singh, Virendra and Parekhji, Rubin (2012) Derating Based Hardware Optimizations in Soft Error Tolerant Designs. In: 30th IEEE VLSI Test Symposium (VTS), APR 23-25, 2012, Hawaii, USA, pp. 282-287.

Publicador

IEEE

Relação

http://dx.doi.org/10.1109/VTS.2012.6231067

http://eprints.iisc.ernet.in/45334/

Palavras-Chave #Supercomputer Education & Research Centre
Tipo

Conference Proceedings

NonPeerReviewed