Nouvelles approches pour la conception d'outils CAO pour le domaine des systèmes embarqués

Thèse numérisée par la Division de la gestion de documents et des archives de l'Université de Montréal

FPGA-based object detection using classification circuits

Dans l'apprentissage machine, la classification est le processus d’assigner une nouvelle observation à une certaine catégorie. Les classifieurs qui mettent en œuvre des algorithmes de classification ont été largement étudié au cours des dernières décennies. Les classifieurs traditionnels sont basés sur des algorithmes tels que le SVM et les réseaux de neurones, et sont généralement exécutés par des logiciels sur CPUs qui fait que le système souffre d’un manque de performance et d’une forte consommation d'énergie. Bien que les GPUs puissent être utilisés pour accélérer le calcul de certains classifieurs, leur grande consommation de puissance empêche la technologie d'être mise en œuvre sur des appareils portables tels que les systèmes embarqués. Pour rendre le système de classification plus léger, les classifieurs devraient être capable de fonctionner sur un système matériel plus compact au lieu d'un groupe de CPUs ou GPUs, et les classifieurs eux-mêmes devraient être optimisés pour ce matériel. Dans ce mémoire, nous explorons la mise en œuvre d'un classifieur novateur sur une plate-forme matérielle à base de FPGA. Le classifieur, conçu par Alain Tapp (Université de Montréal), est basé sur une grande quantité de tables de recherche qui forment des circuits arborescents qui effectuent les tâches de classification. Le FPGA semble être un élément fait sur mesure pour mettre en œuvre ce classifieur avec ses riches ressources de tables de recherche et l'architecture à parallélisme élevé. Notre travail montre que les FPGAs peuvent implémenter plusieurs classifieurs et faire les classification sur des images haute définition à une vitesse très élevée.

Some Studies and New Results on Multi Microprocessor Applications

One of the fastest expanding areas of computer exploitation is in embedded systems, whose prime function is not that of computing, but which nevertheless require information processing in order to carry out their prime function. Advances in hardware technology have made multi microprocessor systems a viable alternative to uniprocessor systems in many embedded application areas. This thesis reports the results of investigations carried out on multi microprocessors oriented towards embedded applications, with a view to enhancing throughput and reliability. An ideal controller for multiprocessor operation is developed which would smoothen sharing of routines and enable more powerful and efficient code I data interchange. Results of performance evaluation are appended.A typical application scenario is presented, which calls for classifying tasks based on characteristic features that were identified. The different classes are introduced along with a partitioned storage scheme. Theoretical analysis is also given. A review of schemes available for reducing disc access time is carried out and a new scheme presented. This is found to speed up data base transactions in embedded systems. The significance of software maintenance and adaptation in such applications is highlighted. A novel scheme of prov1d1ng a maintenance folio to system firmware is presented, alongwith experimental results. Processing reliability can be enhanced if facility exists to check if a particular instruction in a stream is appropriate. Likelihood of occurrence of a particular instruction would be more prudent if number of instructions in the set is less. A new organisation is derived to form the basement for further work. Some early results that would help steer the course of the work are presented.

Safe Contiki OS: Type and Memory Safety for Contiki OS

Embedded systems, especially Wireless Sensor Nodes are highly prone to Type Safety and Memory Safety issues. Contiki, a prominent Operating System in the domain is even more affected by the problem since it makes extensive use of Type casts and Pointers. The work is an attempt to nullify the possibility of Safety violations in Contiki. We use a powerful, still efficient tool called Deputy to achieve this. We also try to automate the process

Safe Contiki OS: Type and Memory Safety for Contiki OS

Embedded systems, especially Wireless Sensor Nodes are highly prone to Type Safety and Memory Safety issues. Contiki, a prominent Operating System in the domain is even more affected by the problem since it makes extensive use of Type casts and Pointers. The work is an attempt to nullify the possibility of Safety violations in Contiki. We use a powerful, still efficient tool called Deputy to achieve this. We also try to automate the process

Modularität und Wiederverwendung

Tagungsband - Vorträge vom Automation Symposium 2006

Methodische Ansätze für die agentenorientierte Softwareentwicklung im Maschinen-und Anlagenbau

Der Anteil dezentraler eingebetteter Systeme steigt in zahlreichen Andwendungsfeldern, wie der Kfz-Elektronik oder der Anlagenautomatisierung [ScZu03]. Zudem steigen die Anforderungen and die Flexibilität und den Funktionsumfang moderner automatisierungs-technischer Systeme. Der Einsatz agentenorientierter Methoden ist diesbezüglich ein geeigneter Ansatz diesen Anforderungen gerecht zu werden [WGU03]. Mit Agenten können flexible, anpassungsfähige Softwaresysteme entwickelt werden, welche die Verteilung von Informationen, Aufgaben, Ressourcen oder Entscheidungsprozessen der realen Problemstellung im Softwaresystem widerspiegeln. Es ist somit möglich, die gewünschte Flexibilität des Systems, bezüglich der Struktur oder des Verhaltens gezielt zu entwerfen. Nachteilig ist jedoch der Indeterminismus des Verhaltens des Gesamtsystems, der sich aufgrund von schwer vorhersagbaren Interaktionen ergibt [Jen00]. Dem gegenüber stehen statische Softwaresysteme, welche zwar einen hohen Determinismus aufweisen aber wenig flexibel in Bezug auf Änderungen der Struktur des Systems oder des Ablaufs des realen Prozesses sind. Mit der steigenden Komplexität der Systeme ist allerdings selbst mit einem statischen Entwurf die Vorhersagbarkeit immer weniger zu gewährleisten. Die Zahl der möglichen Zustände einer Anlage wird mit der Berücksichtigung von allen möglichen Fehlern, Ausfällen und externen Einflüssen (dynamische Umgebung) so groß, daß diese mit vertretbarem Aufwand kaum noch erfassbar sind und somit auch nicht behandelt werden können. Das von der DFG geförderten Projekt AVE [AVE05], welches in Kooperation mit dem Institut für Automatisierungs- und Softwaretechnik der Universität Stuttgart bearbeitet wird, beschäftigt sich in diesem Kontext mit dem Konflikt, die Vorteile der Flexibilität und Anpassungsfähigkeit von agentenorientierter Software mit den spezifischen Anforderungen der Domäne der Echtzeitsysteme, wie Zeit- und Verlässlichkeitsanforderungen, zu verknüpfen. In einer detaillierten Analyse dieser Anforderungen wurde untersucht, wie die Eigenschaften der Anpassungsfähigkeit und Flexibilität prinzipiell die Anforderungen an Echtzeit- und Verlässlichkeitseigenschaften beeinflussen und wie umgekehrt Anforderungen an Echtzeit- und Verlässlichkeitseigenschaften die Anpassungsfähigkeit und Flexibilität beschränken können. Aufbauend auf diesen Erkenntnissen werden Methoden und Konzepte für den Entwurf und die Implementierung von Agentensystemen auf gängiger Automatisierungshardware, insbesondere Speicher Programmierbare Steuerungen (SPS), entwickelt. In diesem Rahmen wird ein Konzept für die Modellierung von Sicherheit in Agentensystemen vorgestellt, welches insbesondere den modularen Charakter von Agenten berücksichtigt. Kernaspekt ist es, dem Entwickler einen Rahmen vorzugeben, der ihn dabei unterstützt ein möglichst lückenloses Sicherheitskonzept zu erstellen und ihm dabei genug Freiheiten lässt den Aufwand für die Strategien zur Fehlererkennung, Fehlerdiagnose und Fehlerbehandlung je nach Anforderung für jedes Modul individuell festzulegen. Desweiteren ist besonderer Wert darauf gelegt worden, dass die verwendeten Darstellungen und Diagramme aus der Domäne stammen und eine gute Vorlage für die spätere Implementierung auf automatisierungstechnischer Hardware bieten.

An Interpolative Analytical Cache Model with Application to Performance-Power Design Space Exploration

Caches are known to consume up to half of all system power in embedded processors. Co-optimizing performance and power of the cache subsystems is therefore an important step in the design of embedded systems, especially those employing application specific instruction processors. In this project, we propose an analytical cache model that succinctly captures the miss performance of an application over the entire cache parameter space. Unlike exhaustive trace driven simulation, our model requires that the program be simulated once so that a few key characteristics can be obtained. Using these application-dependent characteristics, the model can span the entire cache parameter space consisting of cache sizes, associativity and cache block sizes. In our unified model, we are able to cater for direct-mapped, set and fully associative instruction, data and unified caches. Validation against full trace-driven simulations shows that our model has a high degree of fidelity. Finally, we show how the model can be coupled with a power model for caches such that one can very quickly decide on pareto-optimal performance-power design points for rapid design space exploration.

Dynamic load balancing in parallel KD-tree k-means

One among the most influential and popular data mining methods is the k-Means algorithm for cluster analysis. Techniques for improving the efficiency of k-Means have been largely explored in two main directions. The amount of computation can be significantly reduced by adopting geometrical constraints and an efficient data structure, notably a multidimensional binary search tree (KD-Tree). These techniques allow to reduce the number of distance computations the algorithm performs at each iteration. A second direction is parallel processing, where data and computation loads are distributed over many processing nodes. However, little work has been done to provide a parallel formulation of the efficient sequential techniques based on KD-Trees. Such approaches are expected to have an irregular distribution of computation load and can suffer from load imbalance. This issue has so far limited the adoption of these efficient k-Means variants in parallel computing environments. In this work, we provide a parallel formulation of the KD-Tree based k-Means algorithm for distributed memory systems and address its load balancing issue. Three solutions have been developed and tested. Two approaches are based on a static partitioning of the data set and a third solution incorporates a dynamic load balancing policy.

The internet, information architecture and community memory

This article reviews current technological developments, particularly Peer-to-Peer technologies and Distributed Data Systems, and their value to community memory projects, particularly those concerned with the preservation of the cultural, literary and administrative data of cultures which have suffered genocide or are at risk of genocide. It draws attention to the comparatively good representation online of genocide denial groups and changes in the technological strategies of holocaust denial and other far-right groups. It draws on the author's work in providing IT support for a UK-based Non-Governmental Organization providing support for survivors of genocide in Rwanda.

Supporting ad hoc collaborations in peer-to-peer networks

Traditionally, applications and tools supporting collaborative computing have been designed only with personal computers in mind and support a limited range of computing and network platforms. These applications are therefore not well equipped to deal with network heterogeneity and, in particular, do not cope well with dynamic network topologies. Progress in this area must be made if we are to fulfil the needs of users and support the diversity, mobility, and portability that are likely to characterise group work in future. This paper describes a groupware platform called Coco that is designed to support collaboration in a heterogeneous network environment. The work demonstrates that progress in the p development of a generic supporting groupware is achievable, even in the context of heterogeneous and dynamic networks. The work demonstrates the progress made in the development of an underlying communications infrastructure, building on peer-to-peer concept and topologies to improve scalability and robustness.

Building collaborative environments for advanced computing

Synchronous collaborative systems allow geographically distributed users to form a virtual work environment enabling cooperation between peers and enriching the human interaction. The technology facilitating this interaction has been studied for several years and various solutions can be found at present. In this paper, we discuss our experiences with one such widely adopted technology, namely the Access Grid [1]. We describe our experiences with using this technology, identify key problem areas and propose our solution to tackle these issues appropriately. Moreover, we propose the integration of Access Grid with an Application Sharing tool, developed by the authors. Our approach allows these integrated tools to utilise the enhanced features provided by our underlying dynamic transport layer.

A compositional framework for hardware/software co-design

We describe a compositional framework, together with its supporting toolset, for hardware/software co-design. Our framework is an integration of a formal approach within a traditional design flow. The formal approach is based on Interval Temporal Logic and its executable subset, Tempura. Refinement is the key element in our framework because it will derive from a single formal specification of the system the software and hardware parts of the implementation, while preserving all properties of the system specification. During refinement simulation is used to choose the appropriate refinement rules, which are applied automatically in the HOL system. The framework is illustrated with two case studies. The work presented is part of a UK collaborative research project between the Software Technology Research Laboratory at the De Montfort University and the Oxford University Computing Laboratory.

Compositional technique for synthesising multi-phase regular arrays

We describe a high-level design method to synthesize multi-phase regular arrays. The method is based on deriving component designs using classical regular (or systolic) array synthesis techniques and composing these separately evolved component design into a unified global design. Similarity transformations ar e applied to component designs in the composition stage in order to align data ow between the phases of the computations. Three transformations are considered: rotation, re ection and translation. The technique is aimed at the design of hardware components for high-throughput embedded systems applications and we demonstrate this by deriving a multi-phase regular array for the 2-D DCT algorithm which is widely used in many vide ocommunications applications.