Photovoltaic DC-DC module integrated converter for novel cascaded and bypass grid connection topologies - design and optimisation

Grid connected photovoltaic (PV) inverters fall into three broad categories - central, string and module integrated converters (MICs). MICs offer many advantages in performance and flexibility, but are at a cost disadvantage. Two alternative novel approaches proposed by the author - cascaded dc-dc MICs and bypass dc-dc MICs - integrate a simple non-isolated intelligent dc-dc converter with each PV module to provide the advantages of dc-ac MICs at a lower cost. A suitable universal 150 W 5 A dc-dc converter design is presented based on two interleaved MOSFET half bridges. Testing shows zero voltage switching (ZVS) keeps losses under 1 W for bi-directional power flows up to 15 W between two adjacent 12 V PV modules for the bypass application, and efficiencies over 94% for most of the operational power range for the cascaded converter application. Based on the experimental results, potential optimizations to further reduce losses are discussed.

Provisioning a 3.3 MW PhotoVoltaic generation system onto a distribution authority’s 11 kV rural feeder

This paper describes part of an engineering study that was undertaken to demonstrate that a multi-megawatt Photovoltaic (PV) generation system could be connected to a rural 11 kV feeder without creating power quality issues for other consumers. The paper concentrates solely on the voltage regulation aspect of the study as this was the most innovative part of the study. The study was carried out using the time-domain software package, PSCAD/EMTDC. The software model included real time data input of actual measured load and scaled PV generation data, along with real-time substation voltage regulator and PV inverter reactive power control. The outputs from the model plot real-time voltage, current and power variations throughout the daily load and PV generation variations. Other aspects of the study not described in the paper include the analysis of harmonics, voltage flicker, power factor, voltage unbalance and system losses.

Integrated CMOS Gas Sensors

We present a low power gas sensor system on CMOS platform consisting of micromachined polysilicon microheater, temperature controller circuit, resistance readout circuit and SnO2 transducer film. The design criteria for different building blocks of the system is elaborated The microheaters are optimized for temperature uniformity as well as static and dynamic response. The electrical equivalent model for the microheater is derived by extracting thermal and mechanical poles through extensive laser doppler vibrometer measurements. The temperature controller and readout circuit are realized on 130nm CMOS technology The temperature controller re-uses the heater as a temperature sensor and controls the duty cycle of the waveform driving the gate of the power MOSFET which supplies heater current. The readout circuit, with subthreshold operation of the MOSFETs, is based oil resistance to time period conversion followed by frequency to digital converter Subthreshold operatin of MOSFETs coupled with sub-ranging technique, achieves ultra low power consumption with more than five orders of magnitude dynamic range RF sputtered SnO2 film is optimized for its microstructure to achive high sensitivity to sense LPG gas.

Analysis of SEB and SEGR in super-junction MOSFETs

The electric field distribution in the super junction power MOSFET is analyzed using analytical modeling and numerical simulations in this paper. The single-event burn-out (SEB) and single-event gate rupture (SEGR) phenomena in this device are studied in detail. It is demonstrated that the super junction device is much less sensitive to SEB and SEGR compared to the standard power MOSFET. The physical mechanism is explained.

A method of extracting switching loss from a high efficiency MOSFET based half bridge converter

The measurement of losses in high efficiency / high power converters is difficult. Measuring the losses directly from the difference between the input and output power results in large errors. Calorimetric methods are usually used to bypass this issue but introduce different problems, such as, long measurement times, limited power loss measurement range and/or large set up cost. In this paper the total losses of a converter are measured directly and switching losses are exacted. The measurements can be taken with only three multimeters and a current probe and a standard bench power supply. After acquiring two or three power loss versus output current sweeps, a series of curve fitting processes are applied and the switching losses extracted.

An isolated MOSFET gate driver

Traditional methods of isolated MOSFET/IGBT gate drive are presented, and their pros and cons assessed. The best options are chosen to meet our objective— a small, high speed, low cost, low power isolated gate drive module. Two small ferrite bead transformers are used for isolation, one transmits power at 2.5MHz, the other sends narrow set reset pulses. On the secondary these pulses drive a transistor totem pole to ensure high current drive, and the value is held by CMOS buffers with positive feedback. An alternative design for driving logic level devices uses only an HC buffer on the secondary. Double sided SMDconstruction (primary one side, secondary on the other) yields an upright module 40x18x5mm. Propagation delaywas 20ns, and rise/fall time 15ns with a 1nF load. The design places no limits on frequency of operation or duty cycle. Power supply requirementswere 5V@20mA for operation below 100kHz, dominated by magnetising current.

Comparison of the gate drive parameter space for driving power MOSFETs using conventional and cascode configurations

Conventional voltage driven gate drive circuits utilise a resistor to control the switching speed of power MOS-FETs. The gate resistance is adjusted to provide controlled rate of change of load current and voltage. The cascode gate drive configuration has been proposed as an alternative to the conventional resistor-fed gate drive circuit. While cascode drive is broadly understood in the literature the switching characteristics of this topology are not well documented. This paper explores, through both simulation and experimentation, the gate drive parameter space of the cascode gate drive configuration and provides a comparison to the switching characteristics of conventional gate drive.

Characterisation of the cascode gate drive of power MOSFETs in clamped inductive switching applications

This thesis proposes a novel gate drive circuit to improve the switching performance of MOSFET power switches in power electronic converters. The proposed topology exploits the cascode configuration, allowing the minimisation of switching losses in the presence of practical circuit constraints, which enables efficiency and power density improvements. Switching characteristics of the new topology are investigated and key mechanisms that control the switching process are identified. Unique analysis tools and techniques are also developed to demonstrate the application of the cascode gate drive circuit for switching performance optimisation.

A Simulation Based Study and Analysis of Double Gate Tunnel FET Performance for Low Stand-By Power Applications

The conventional metal oxide semiconductor field effect transistor (MOSFET)may not be suitable for future low standby power (LSTP) applications due to its high off-state current as the sub-threshold swing is theoretically limited to 60mV/decade. Tunnel field effect transistor (TFET) based on gate controlled band to band tunneling has attracted attention for such applications due to its extremely small sub-threshold swing (much less than 60mV/decade). This paper takes a simulation approach to gain some insight into its electrostatics and the carrier transport mechanism. Using 2D device simulations, a thorough study and analysis of the electrical parameters of the planar double gate TFET is performed. Due to excellent sub-threshold characteristics and a reverse biased structure, it offers orders of magnitude less leakage current compared to the conventional MOSFET. In this work, it is shown that the device can be scaled down to channel lengths as small as 30 nm without affecting its performance. Also, it is observed that the bulk region of the device plays a major role in determining the sub-threshold characteristics of the device and considerable improvement in performance (in terms of ION/IOFF ratio) can be achieved if the thickness of the device is reduced. An ION/IOFF ratio of 2x1012 and a minimum point sub-threshold swing of 22mV/decade is obtained.

Multilevel inverters for low-power application

Multilevel inverters are an attractive solution in the medium-voltage and high-power applications. However in the low-power range also it can be a better solution compared to two-level inverters, if MOSFETs are used as devices switching in the order of 100 kHz. The effect of clamping diodes in the diode-clamped multilevel inverters play an important role in determining its efficiency. Power loss introduced by the reverse recovery of MOSFET body diode prohibits the use of MOSFET in hard-switched inverter legs. A technique of avoiding reverse recovery loss of MOSFET body diode in a three-level neutral point clamped inverter is suggested. The use of multilevel inverters topology enables operation at high switching frequency without sacrificing efficiency. High switching frequency of operation reduces the output filter requirement, which in turn helps in reducing the size of the inverter. This study elaborates the trade-off analysis to quantify the suitability of multilevel inverters in the low-power applications. Advantages of using a MOSFET-based three-level diode-clamped inverter for a PM motor drive and UPS systems are discussed.

A mathematical and experimental investigation of microcycle spectral estimates of semiconductor flicker noise

The experimental portion of this thesis tries to estimate the density of the power spectrum of very low frequency semiconductor noise, from 10^-6.3 cps to 1. cps with a greater accuracy than that achieved in previous similar attempts: it is concluded that the spectrum is 1/f^α with α approximately 1.3 over most of the frequency range, but appearing to have a value of about 1 in the lowest decade. The noise sources are, among others, the first stage circuits of a grounded input silicon epitaxial operational amplifier. This thesis also investigates a peculiar form of stationarity which seems to distinguish flicker noise from other semiconductor noise.

In order to decrease by an order of magnitude the pernicious effects of temperature drifts, semiconductor "aging", and possible mechanical failures associated with prolonged periods of data taking, 10 independent noise sources were time-multiplexed and their spectral estimates were subsequently averaged. If the sources have similar spectra, it is demonstrated that this reduces the necessary data-taking time by a factor of 10 for a given accuracy.

In view of the measured high temperature sensitivity of the noise sources, it was necessary to combine the passive attenuation of a special-material container with active control. The noise sources were placed in a copper-epoxy container of high heat capacity and medium heat conductivity, and that container was immersed in a temperature controlled circulating ethylene-glycol bath.

Other spectra of interest, estimated from data taken concurrently with the semiconductor noise data were the spectra of the bath's controlled temperature, the semiconductor surface temperature, and the power supply voltage amplitude fluctuations. A brief description of the equipment constructed to obtain the aforementioned data is included.

The analytical portion of this work is concerned with the following questions: what is the best final spectral density estimate given 10 statistically independent ones of varying quality and magnitude? How can the Blackman and Tukey algorithm which is used for spectral estimation in this work be improved upon? How can non-equidistant sampling reduce data processing cost? Should one try to remove common trands shared by supposedly statistically independent noise sources and, if so, what are the mathematical difficulties involved? What is a physically plausible mathematical model that can account for flicker noise and what are the mathematical implications on its statistical properties? Finally, the variance of the spectral estimate obtained through the Blackman/Tukey algorithm is analyzed in greater detail; the variance is shown to diverge for α ≥ 1 in an assumed power spectrum of k/|f|^α, unless the assumed spectrum is "truncated".