Modeling and manufacturability assessment of bistable quantum-dot cells

We have investigated the behavior of bistable cells made up of four quantum dots and occupied by two electrons, in the presence of realistic confinement potentials produced by depletion gates on top of a GaAs/AlGaAs heterostructure. Such a cell represents the basic building block for logic architectures based on the concept of quantum cellular automata (QCA) and of ground state computation, which have been proposed as an alternative to traditional transistor-based logic circuits. We have focused on the robustness of the operation of such cells with respect to asymmetries derived from fabrication tolerances. We have developed a two-dimensional model for the calculation of the electron density in a driven cell in response to the polarization state of a driver cell. Our method is based on the one-shot configuration-interaction technique, adapted from molecular chemistry. From the results of our simulations, we conclude that an implementation of QCA logic based on simple ¿hole arrays¿ is not feasible, because of the extreme sensitivity to fabrication tolerances. As an alternative, we propose cells defined by multiple gates, where geometrical asymmetries can be compensated for by adjusting the bias voltages. Even though not immediately applicable to the implementation of logic gates and not suitable for large scale integration, the proposed cell layout should allow an experimental demonstration of a chain of QCA cells.

Memristive Computing

Memristive computing refers to the utilization of the memristor, the fourth fundamental passive circuit element, in computational tasks. The existence of the memristor was theoretically predicted in 1971 by Leon O. Chua, but experimentally validated only in 2008 by HP Labs. A memristor is essentially a nonvolatile nanoscale programmable resistor — indeed, memory resistor — whose resistance, or memristance to be precise, is changed by applying a voltage across, or current through, the device. Memristive computing is a new area of research, and many of its fundamental questions still remain open. For example, it is yet unclear which applications would benefit the most from the inherent nonlinear dynamics of memristors. In any case, these dynamics should be exploited to allow memristors to perform computation in a natural way instead of attempting to emulate existing technologies such as CMOS logic. Examples of such methods of computation presented in this thesis are memristive stateful logic operations, memristive multiplication based on the translinear principle, and the exploitation of nonlinear dynamics to construct chaotic memristive circuits. This thesis considers memristive computing at various levels of abstraction. The first part of the thesis analyses the physical properties and the current-voltage behaviour of a single device. The middle part presents memristor programming methods, and describes microcircuits for logic and analog operations. The final chapters discuss memristive computing in largescale applications. In particular, cellular neural networks, and associative memory architectures are proposed as applications that significantly benefit from memristive implementation. The work presents several new results on memristor modeling and programming, memristive logic, analog arithmetic operations on memristors, and applications of memristors. The main conclusion of this thesis is that memristive computing will be advantageous in large-scale, highly parallel mixed-mode processing architectures. This can be justified by the following two arguments. First, since processing can be performed directly within memristive memory architectures, the required circuitry, processing time, and possibly also power consumption can be reduced compared to a conventional CMOS implementation. Second, intrachip communication can be naturally implemented by a memristive crossbar structure.

On Space-Time Trade-Off for Montgomery Multipliers over Finite Fields

La multiplication dans le corps de Galois à 2^m éléments (i.e. GF(2^m)) est une opérations très importante pour les applications de la théorie des correcteurs et de la cryptographie. Dans ce mémoire, nous nous intéressons aux réalisations parallèles de multiplicateurs dans GF(2^m) lorsque ce dernier est généré par des trinômes irréductibles. Notre point de départ est le multiplicateur de Montgomery qui calcule A(x)B(x)x^(-u) efficacement, étant donné A(x), B(x) in GF(2^m) pour u choisi judicieusement. Nous étudions ensuite l'algorithme diviser pour régner PCHS qui permet de partitionner les multiplicandes d'un produit dans GF(2^m) lorsque m est impair. Nous l'appliquons pour la partitionnement de A(x) et de B(x) dans la multiplication de Montgomery A(x)B(x)x^(-u) pour GF(2^m) même si m est pair. Basé sur cette nouvelle approche, nous construisons un multiplicateur dans GF(2^m) généré par des trinôme irréductibles. Une nouvelle astuce de réutilisation des résultats intermédiaires nous permet d'éliminer plusieurs portes XOR redondantes. Les complexités de temps (i.e. le délais) et d'espace (i.e. le nombre de portes logiques) du nouveau multiplicateur sont ensuite analysées: 1. Le nouveau multiplicateur demande environ 25% moins de portes logiques que les multiplicateurs de Montgomery et de Mastrovito lorsque GF(2^m) est généré par des trinômes irréductible et m est suffisamment grand. Le nombre de portes du nouveau multiplicateur est presque identique à celui du multiplicateur de Karatsuba proposé par Elia. 2. Le délai de calcul du nouveau multiplicateur excède celui des meilleurs multiplicateurs d'au plus deux évaluations de portes XOR. 3. Nous determinons le délai et le nombre de portes logiques du nouveau multiplicateur sur les deux corps de Galois recommandés par le National Institute of Standards and Technology (NIST). Nous montrons que notre multiplicateurs contient 15% moins de portes logiques que les multiplicateurs de Montgomery et de Mastrovito au coût d'un délai d'au plus une porte XOR supplémentaire. De plus, notre multiplicateur a un délai d'une porte XOR moindre que celui du multiplicateur d'Elia au coût d'une augmentation de moins de 1% du nombre total de portes logiques.

Characterization of Photonic Materials Using Thermal Lens Technique

The subject of Photonics is concerned with the generation,control and utilization of photons for performing a variety of tasks.It came to existence as a consequence of the harmonious fusion of optical methods with electronic technology.Wide spread use of laser based methods in electronics is slowly replacing elecrtons with photons in the field of Communication,Control and Computing .Therefore,there is a need to promote the R & D activities in the area of Photonics and to generate well trained manpower in laser related fields.Development and characterization of photonic materials is an important subject of research in the field of Photonics.Optical and thermal characterization of photonic materials using thermal lens technique is a PhD thesis in the field of Photonics in which the author describes how thermal lens effect can be used to characterize themal and optical properties of photonic materials.Plausibility of thermal lens based logic gates is also presented in this thesis.

Performance Analysis of Reversible Fast Decimal Adders

This paper presents a performance analysis of reversible, fault tolerant VLSI implementations of carry select and hybrid decimal adders suitable for multi-digit BCD addition. The designs enable partial parallel processing of all digits that perform high-speed addition in decimal domain. When the number of digits is more than 25 the hybrid decimal adder can operate 5 times faster than conventional decimal adder using classical logic gates. The speed up factor of hybrid adder increases above 10 when the number of decimal digits is more than 25 for reversible logic implementation. Such highspeed decimal adders find applications in real time processors and internet-based applications. The implementations use only reversible conservative Fredkin gates, which make it suitable for VLSI circuits.

Black Boxes and Abstraction or A quick run through how computers work

How we get from transistors through to logic gates to ALUs and memory to the stored program and the fetch execute cycle through to machine code and high level languages. Inspired by Tanenbaum's approach in "Structured Computer Organozation"

A double data rate (DDR) architecture for OFDM based wireless consumer devices

The creation of OFDM based Wireless Personal Area Networks (WPANs) has allowed the development of high bit-rate wireless communication devices suitable for streaming High Definition video between consumer products, as demonstrated in Wireless-USB and Wireless-HDMI. However, these devices need high frequency clock rates, particularly for the OFDM, FFT and symbol processing sections resulting in high silicon cost and high electrical power. The high clock rates make hardware prototyping difficult and verification is therefore very important but costly. Acknowledging that electrical power in wireless consumer devices is more critical than the number of implemented logic gates, this paper presents a Double Data Rate (DDR) architecture for implementation inside a OFDM baseband codec in order to reduce the high frequency clock rates by a complete factor of 2. The presented architecture has been implemented and tested for ECMA-368 (Wireless- USB context) resulting in a maximum clock rate of 264MHz instead of the expected 528MHz clock rate existing anywhere on the baseband codec die.

A double data rate (DDR) architecture for OFDM based wireless consumer devices

The creation of OFDM based Wireless Personal Area Networks (WPANs) has allowed high bit-rate wireless communication devices suitable for streaming High Definition video between consumer products as demonstrated in Wireless- USB. However, these devices need high clock rates, particularly for the OFDM sections resulting in high silicon cost and high electrical power. Acknowledging that electrical power in wireless consumer devices is more critical than the number of implemented logic gates, this paper presents a Double Data Rate (DDR) architecture to reduce the OFDM input and output clock rate by a factor of 2. The architecture has been implemented and tested for Wireless-USB (ECMA-368) resulting in a maximum clock of 264MHz instead of 528MHz existing anywhere on the die.

Ensaios sobre computação e informação quânticas: fundamentação e simulações sobre o efeito da entropia

Pós-graduação em Ciência da Computação - IBILCE

Modelagem da disponibilidade de uma unidade geradora da UHE-Tucuruí

Com o advindo do marco regulatório do Setor Elétrico Brasileiro, a partir de 2004, os agentes que atuam neste mercado têm experimentado um acirramento nas disputas por novos negócios, evidenciando um aumento de competitividade. A Disponibilidade dos Ativos Físicos e os Custos com Manutenção se apresentam como os pontos chave para a competitividade dos agentes. O presente trabalho tem por objetivo apresentar uma metodologia de Análise de Disponibilidade de Sistemas Reparáveis, durante as etapas de projeto ou de operação do sistema, contemplando a mensuração dos Custos com Manutenção versus o Desembolso com Aquisição para um nível esperado de desempenho. A metodologia para a Análise de Disponibilidade sugerida se utiliza da construção do Diagrama de Blocos do Sistema com respectivas descrições funcionais, exportação das informações para o formato de Árvore de Sucesso, composta de portas lógicas dos tipos "E" e "OU" as quais caracterizam um subsistema integrante do sistema principal. O analista pode reavaliar a topologia do sistema, agregando ou retirando redundâncias com a finalidade de ajustar o desempenho do projeto aos requisitos de Disponibilidade, Custo de Aquisição e Custos de Manutenção. Como resultados do trabalho foram identificadas lacunas normativas que definem a forma de controle do desempenho dos ativos, estabelecida uma sistemática de integração entre técnicas de modelagem de confiabilidade e disponibilidade, estabelecidos e incorporados indicadores de desempenho de Manutenção Programada em um agente do mercado, foram modelados e discutidos diferentes cenários para um Sistema de Circulação de Óleo de Mancal e foi aplicado o modelo a toda uma Unidade Geradora Hidráulica por meio da implementação computacional do modelo aos componentes críticos dos principais sistemas.

Quantum state tomography and quantum logical operations in a three qubits NMR quadrupolar system

In this work, we present an implementation of quantum logic gates and algorithms in a three effective qubits system, represented by a (I = 7/2) NMR quadrupolar nuclei. To implement these protocols we have used the strong modulating pulses (SMP) and the various stages of each implementation were verified by quantum state tomography (QST). The results for the computational base states, Toffolli logic gates, and Deutsch-Jozsa and Grover algorithms are presented here. Also, we discuss the difficulties and advantages of implementing such protocols using the SMP technique in quadrupolar systems.

Experimental Investigation of Three-Dimensional Single and Double optical Lattices

A complete laser cooling setup was built, with focus on threedimensional near-resonant optical lattices for cesium. These consist of regularly ordered micropotentials, created by the interference of four laser beams. One key feature of optical lattices is an inherent ”Sisyphus cooling” process. It efficiently extracts kinetic energy from the atoms, leading to equilibrium temperatures of a few µK. The corresponding kinetic energy is lower than the depth of the potential wells, so that atoms can be trapped. We performed detailed studies of the cooling processes in optical lattices by using the time-of-flight and absorption-imaging techniques. We investigated the dependence of the equilibrium temperature on the optical lattice parameters, such as detuning, optical potential and lattice geometry. The presence of neighbouring transitions in the cesium hyperfine level structure was used to break symmetries in order to identify, which role “red” and “blue” transitions play in the cooling. We also examined the limits for the cooling process in optical lattices, and the possible difference in steady-state velocity distributions for different directions. Moreover, in collaboration with ´Ecole Normale Sup´erieure in Paris, numerical simulations were performed in order to get more insight in the cooling dynamics of optical lattices. Optical lattices can keep atoms almost perfectly isolated from the environment and have therefore been suggested as a platform for a host of possible experiments aimed at coherent quantum manipulations, such as spin-squeezing and the implementation of quantum logic-gates. We developed a novel way to trap two different cesium ground states in two distinct, interpenetrating optical lattices, and to change the distance between sites of one lattice relative to sites of the other lattice. This is a first step towards the implementation of quantum simulation schemes in optical lattices.

THE RESONATE-AND-FIRE NEURON: TIME DEPENDENT AND FREQUENCY SELECTIVE NEURONS IN NEURAL NETWORKS

The means through which the nervous system perceives its environment is one of the most fascinating questions in contemporary science. Our endeavors to comprehend the principles of neural science provide an instance of how biological processes may inspire novel methods in mathematical modeling and engineering. The application ofmathematical models towards understanding neural signals and systems represents a vibrant field of research that has spanned over half a century. During this period, multiple approaches to neuronal modeling have been adopted, and each approach is adept at elucidating a specific aspect of nervous system function. Thus while bio-physical models have strived to comprehend the dynamics of actual physical processes occurring within a nerve cell, the phenomenological approach has conceived models that relate the ionic properties of nerve cells to transitions in neural activity. Further-more, the field of neural networks has endeavored to explore how distributed parallel processing systems may become capable of storing memory. Through this project, we strive to explore how some of the insights gained from biophysical neuronal modeling may be incorporated within the field of neural net-works. We specifically study the capabilities of a simple neural model, the Resonate-and-Fire (RAF) neuron, whose derivation is inspired by biophysical neural modeling. While reflecting further biological plausibility, the RAF neuron is also analytically tractable, and thus may be implemented within neural networks. In the following thesis, we provide a brief overview of the different approaches that have been adopted towards comprehending the properties of nerve cells, along with the framework under which our specific neuron model relates to the field of neuronal modeling. Subsequently, we explore some of the time-dependent neurocomputational capabilities of the RAF neuron, and we utilize the model to classify logic gates, and solve the classic XOR problem. Finally we explore how the resonate-and-fire neuron may be implemented within neural networks, and how such a network could be adapted through the temporal backpropagation algorithm.

Low-power vertical cavity NAND gate

The study of the Vertical-Cavity Semiconductor Optical Amplifiers (VCSOAs) for optical signal processing applications is increasing his interest. Due to their particular structure, the VCSOAs present some advantages when compared to their edge-emitting counterparts including low manufacturing costs, high coupling efficiency to optical fibers and the ease to fabricate 2-D arrays of this kind of devices. As a consequence, all-optical logic gates based on VCSOAs may be very promising devices for their use in optical computing and optical switching in communications. Moreover, since all the boolean logic functions can be implemented by combining NAND logic gates, the development of a Vertical-Cavity NAND gate would be of particular interest. In this paper, the characteristics of the dispersive optical bistability appearing on a VCSOA operated in reflection are studied. A progressive increment of the number of layers compounding the top Distributed Bragg Reflector (DBR) of the VCSOA results on a change on the shape of the appearing bistability from an S-shape to a clockwise bistable loop. This resulting clockwise bistability has high on-off contrast ratio and input power requirements one order of magnitude lower than those needed for edge-emitting devices. Based on these results, an all-optical vertical-cavity NAND gate with high on-off contrast ratio and an input power for operation of only 10|i\V will be reported in this paper.