Arquitetura em hardware para co-processamento de tarefas em sistema operacional tempo real

Os sistemas operacionais de tempo real, assim como os sistemas embarcados, estão inseridos no desenvolvimento de projetos de automação industrial segmentado em diversas áreas de pesquisa como, por exemplo, robótica, telecomunicações, e barramentos industriais. As aplicações de sistemas modernos de controle e automação necessitam de alta confiabilidade, velocidade de comunicação, além de, determinismo temporal. Sistemas operacionais de tempo real (SOTR) têm-se apresentado como uma solução confiável quando aplicadas em sistemas que se fundamentam no cumprimento de requisitos temporais. Além disso, o desempenho computacional é totalmente dependente da capacidade operacional da unidade de processamento. Em um sistema monoprocessado, parte da capacidade computacional da unidade de processamento é utilizada em atividades administrativas, como por exemplo, processos de chaveamento e salvamento de contexto. Em decorrência disto, surge a sobrecarga computacional como fator preponderante para o desempenho do sistema. Este trabalho tem por objetivo, analisar e fornecer uma arquitetura alternativa para realizar o co-processamento de tarefas em uma plataforma IBM-PC, aumentando a capacidade computacional do microprocessador principal. No presente trabalho, a plataforma de coprocessamento realiza a execução do algoritmo de escalonamento do sistema operacional, desta forma distribuiu-se o gerenciamento temporal das tarefas entre a plataforma IBM-PC e a unidade de co-processamento.

Redes-em-chip de baixo custo

Com as recentes tecnologias de fabricação é possível integrar milhões de transistores em um único chip, permitindo a criação dos chamados System-on-Chip (SoCs), que integram em um único chip um grande número de componentes (tipicamente blocos reutilizáveis conhecidos por núcleos). Quanto mais complexos forem estes sistemas, melhores técnicas de projeto serão necessárias para também reduzir o tempo e custo do projeto. Uma destas técnicas, chamada de Network-on-Chip (NoC), permite melhorar a performance da comunicação entre os núcleos e, ao mesmo tempo, fornecer uma plataforma de comunicação escalável e que pode ser reutilizada para um grande número de sistemas. Uma NoC pode ser definida como uma estrutura de roteadores e canais ponto-a-ponto que interconectam os núcleos de um sistema, provendo o suporte de comunicação entre eles. Os dados são transmitidos pela rede na forma de mensagens, que podem ser divididas em unidades menores chamadas de pacote. Uma das desvantagens desta plataforma de comunicação é o impacto na área do sistema causado pelos roteadores. Dentro deste contexto, este trabalho apresenta uma arquitetura de roteador de baixo custo, com o objetivo de permitir o uso de NoCs em sistemas onde a área do roteador representará um grande impacto no custo do sistema. A arquitetura deste roteador, chamado de Tonga, é baseada em um roteador chamado RASoC, um soft-core para SoCs. Nesta dissertação será apresentada também uma rede heterogênea, baseada na rede SoCIN, e composta por dois tipos de roteadores – RASoC e Tonga. Estes roteadores visam diferentes objetivos: Rasoc alcança uma maior performance comparada ao Tonga, mas ocupa área consideravelmente maior. Potencialmente, uma NoC heterogênea otimizada pode ser desenvolvida combinando estes roteadores, procurando o melhor compromisso entre área e latência. Os modelos desenvolvidos permitem a estimativa de área e do desempenho das arquiteturas de comunicação propostas e são apresentados resultados de performance para algumas aplicações.

T&D-bench : explorando o espaço de projeto de processadores em ensino e em pesquisa

Uma metodologia de modelagem para a exploração do espaço de projeto de processadores é apresentada. A exploração do espaço de projeto constitui uma das etapas do fluxo de projeto dos atuais processadores de alto desempenho e de sistemas embarcados, que auxilia os projetistas no tratamento da complexidade inerente ao processo contemporâneo de projeto de sistemas computacionais. A principal característica desta metodologia é um processo de modelagem simples e rápido. Isso é obtido através da disponibilização dos recursos de modelagem em camadas com propósitos e níveis de complexidade de uso diferenciados e da limitação do número de elementos (palavras-chave, classes e métodos) que devem ser conhecidos pelo projetista para o acesso a estes recursos, independentemente da camada na qual eles se encontram. A única exigência para o uso de tais recursos são conhecimentos que estudantes de Computação adquirem ao longo dos seus cursos da área de Computação e Informática. Outras características da metodologia de modelagem incluem: recursos específicos e distintos para a descrição da organização, da arquitetura e de aspectos temporais do processador; um estilo de descrição estrutural de alto nível da organização; a possibilidade de uso de recursos gráficos em tempo de modelagem e em tempo de simulação; e a existência de informações nos modelos que podem ser usadas para a tradução das descrições para uma Hardware Description Language Todas estas características constituem um conjunto de soluções de modelagem e simulação de processadores que não é encontrado em outros ambientes usados na exploração do espaço de projeto, baseados em Architecture Description Languages, Hardware Description Languages e ferramentas de simulação. Além disso, os modelos de processadores, desenvolvidos com esta metodologia, fornecem os recursos para a aceleração do aprendizado de conteúdos de arquitetura de computadores que só são encontrados em simuladores para ensino. Uma infra-estrutura de software que implementa a metodologia de modelagem foi desenvolvida e está disponível. Ela foi usada no ensino e no contexto da pesquisa para a modelagem e simulação de diversos processadores. Uma comparação com a metodologia de modelagem de uma Architecture Description Language demonstra a simplicidade e a rapidez do processo de modelagem previsto na metodologia apresentada.

Metodologia para adaptação de microarquiteturas microprogramadas soft-core à uma ISA padrão: estudo do impacto sobre a complexidade de hardware para o padrão MIPS

In academia, it is common to create didactic processors, facing practical disciplines in the area of Hardware Computer and can be used as subjects in software platforms, operating systems and compilers. Often, these processors are described without ISA standard, which requires the creation of compilers and other basic software to provide the hardware / software interface and hinder their integration with other processors and devices. Using reconfigurable devices described in a HDL language allows the creation or modification of any microarchitecture component, leading to alteration of the functional units of data path processor as well as the state machine that implements the control unit even as new needs arise. In particular, processors RISP enable modification of machine instructions, allowing entering or modifying instructions, and may even adapt to a new architecture. This work, as the object of study addressing educational soft-core processors described in VHDL, from a proposed methodology and its application on two processors with different complexity levels, shows that it s possible to tailor processors for a standard ISA without causing an increase in the level hardware complexity, ie without significant increase in chip area, while its level of performance in the application execution remains unchanged or is enhanced. The implementations also allow us to say that besides being possible to replace the architecture of a processor without changing its organization, RISP processor can switch between different instruction sets, which can be expanded to toggle between different ISAs, allowing a single processor become adaptive hybrid architecture, which can be used in embedded systems and heterogeneous multiprocessor environments

Processamento embarcado aplicado a um sistema de deteccão de vazamentos

Embedded systems are widely spread nowadays. An example is the Digital Signal Processor (DSP), which is a high processing power device. This work s contribution consist of exposing DSP implementation of the system logic for detecting leaks in real time. Among the various methods of leak detection available today this work uses a technique based on the pipe pressure analysis and usesWavelet Transform and Neural Networks. In this context, the DSP, in addition to do the pressure signal digital processing, also communicates to a Global Positioning System (GPS), which helps in situating the leak, and to a SCADA, sharing information. To ensure robustness and reliability in communication between DSP and SCADA the Modbus protocol is used. As it is a real time application, special attention is given to the response time of each of the tasks performed by the DSP. Tests and leak simulations were performed using the structure of Laboratory of Evaluation of Measurement in Oil (LAMP), at Federal University of Rio Grande do Norte (UFRN)

Desenvolvimento de uma arquitetura em hardware prototipada em FPGA para aplicações genéricas utilizando redes neurais artificiais embarcadas

This work proposes hardware architecture, VHDL described, developed to embedded Artificial Neural Network (ANN), Multilayer Perceptron (MLP). The present work idealizes that, in this architecture, ANN applications could easily embed several different topologies of MLP network industrial field. The MLP topology in which the architecture can be configured is defined by a simple and specifically data input (instructions) that determines the layers and Perceptron quantity of the network. In order to set several MLP topologies, many components (datapath) and a controller were developed to execute these instructions. Thus, an user defines a group of previously known instructions which determine ANN characteristics. The system will guarantee the MLP execution through the neural processors (Perceptrons), the components of datapath and the controller that were developed. In other way, the biases and the weights must be static, the ANN that will be embedded must had been trained previously, in off-line way. The knowledge of system internal characteristics and the VHDL language by the user are not needed. The reconfigurable FPGA device was used to implement, simulate and test all the system, allowing application in several real daily problems

Desenvolvimento de um ambiente para projeto de controladores fuzzy para dispositivos móveis

Fuzzy intelligent systems are present in a variety of equipment ranging from household appliances to Fuzzy intelligent systems are present in a variety of equipment ranging from household appliances to small devices such as digital cameras and cell phones being used primarily for dealing with the uncertainties in the modeling of real systems. However, commercial implementations of Fuzzy systems are not general purpose and do not have portability to different hardware platforms. Thinking about these issues this work presents the implementation of an open source development environment that consists of a desktop system capable of generate Graphically a general purpose Fuzzy controller and export these parameters for an embedded system with a Fuzzy controller written in Java Platform Micro Edition To (J2ME), whose modular design makes it portable to any mobile device that supports J2ME. Thus, the proposed development platform is capable of generating all the parameters of a Fuzzy controller and export it in XML file, and the code responsible for the control logic that is embedded in the mobile device is able to read this file and start the controller. All the parameters of a Fuzzy controller are configurable using the desktop system, since the membership functions and rule base, even the universe of discourse of the linguistic terms of output variables. This system generates Fuzzy controllers for the interpolation model of Takagi-Sugeno. As the validation process and testing of the proposed solution the Fuzzy controller was embedded on the mobile device Sun SPOT ® and used to control a plant-level Quanser®, and to compare the Fuzzy controller generated by the system with other types of controllers was implemented and embedded in sun spot a PID controller to control the same level plant of Quanser®

SOA-DB: uma arquitetura embarcada orientada a serviço para acesso a dispositivos biomédicos

The great diversity in the architecture of biomedical devices, coupled with their different communication protocols, has hindered the implementation of systems that need to make access to these devices. Given these differences, the need arises to provide access to such a transparent manner. In this sense, this paper proposes an embedded architecture, service-oriented, for access to biomedical devices, as a way to abstract the mechanism for writing and reading data on these devices, thereby contributing to the increase in quality and productivity of biomedical systems so as to enable that, the focus of the development team of biomedical software, is almost exclusively directed to its functional requirements

Implementação de um sistema embarcado aplicado ao controle de pressão arterial

Hypertension is a dangerous disease that can cause serious harm to a patient health. In some situations the necessity to control this pressure is even greater, as in surgical procedures and post-surgical patients. To decrease the chances of a complication, it is necessary to reduce blood pressure as soon as possible. Continuous infusion of vasodilators drugs, such as sodium nitroprusside (SNP), rapidly decreased blood pressure in most patients, avoiding major problems. Maintaining the desired blood pressure requires constant monitoring of arterial blood pressure and frequently adjusting the drug infusion rate. Manual control of arterial blood pressure by clinical personnel is very demanding, time consuming and, as a result, sometimes of poor quality. Thus, the aim of this work is the design and implementation of a database of tuned controllers based on patients models, in order to find a suitable PID to be embedded in a Programmable Integrated Circuit (PIC), which has a smaller cost, smaller size and lower power consumption. For best results in controlling the blood pressure and choosing the adequate controller, tuning algorithms, system identification techniques and Smith predictor are used. This work also introduces a monitoring system to assist in detecting anomalies and optimize the process of patient care.

Implementação Hardware/Software da estimação de movimento segundo o padrão H.264

Motion estimation is the main responsible for data reduction in digital video encoding. It is also the most computational damanding step. H.264 is the newest standard for video compression and was planned to double the compression ratio achievied by previous standards. It was developed by the ITU-T Video Coding Experts Group (VCEG) together with the ISO/IEC Moving Picture Experts Group (MPEG) as the product of a partnership effort known as the Joint Video Team (JVT). H.264 presents novelties that improve the motion estimation efficiency, such as the adoption of variable block-size, quarter pixel precision and multiple reference frames. This work defines an architecture for motion estimation in hardware/software, using a full search algorithm, variable block-size and mode decision. This work consider the use of reconfigurable devices, soft-processors and development tools for embedded systems such as Quartus II, SOPC Builder, Nios II and ModelSim

Avaliação do Uso de Smartphones na Interação com as Aplicações da Televisão Digital Brasileira

Brazil is going through the process from analogical transmission to digital transmission. This new technology, in addition to providing a high quality audio and video, also allows applications to execute on television. Equipment called Set-Top Box are needed to allow the reception of this new signal and create the appropriate environment necessary to execute applications. At first, the only way to interact with these applications is given by remote control. However, the remote control has serious usability problems when used to interact with some types of applications. This research suggests a software resources implementation capable to create a environment that allows a smartphone to interact with applications. Besides this implementation, is performed a comparative study between use remote controle and smartphones to interact with applications of digital television, taking into account parameters related to usability. After analysis of data collected by the comparative study is possible to identify which device provides an interactive experience more interesting for users

Avaliação da execução de aplicações orientadas à dados na arquitetura de redes em chip IPNoSys

The increasing complexity of integrated circuits has boosted the development of communications architectures like Networks-on-Chip (NoCs), as an architecture; alternative for interconnection of Systems-on-Chip (SoC). Networks-on-Chip complain for component reuse, parallelism and scalability, enhancing reusability in projects of dedicated applications. In the literature, lots of proposals have been made, suggesting different configurations for networks-on-chip architectures. Among all networks-on-chip considered, the architecture of IPNoSys is a non conventional one, since it allows the execution of operations, while the communication process is performed. This study aims to evaluate the execution of data-flow based applications on IPNoSys, focusing on their adaptation against the design constraints. Data-flow based applications are characterized by the flowing of continuous stream of data, on which operations are executed. We expect that these type of applications can be improved when running on IPNoSys, because they have a programming model similar to the execution model of this network. By observing the behavior of these applications when running on IPNoSys, were performed changes in the execution model of the network IPNoSys, allowing the implementation of an instruction level parallelism. For these purposes, analysis of the implementations of dataflow applications were performed and compared

Contribuições para verificação automática de applets javacard

The widespread growth in the use of smart cards (by banks, transport services, and cell phones, etc) has brought an important fact that must be addressed: the need of tools that can be used to verify such cards, so to guarantee the correctness of their software. As the vast majority of cards that are being developed nowadays use the JavaCard technology as they software layer, the use of the Java Modeling Language (JML) to specify their programs appear as a natural solution. JML is a formal language tailored to Java. It has been inspired by methodologies from Larch and Eiffel, and has been widely adopted as the de facto language when dealing with specification of any Java related program. Various tools that make use of JML have already been developed, covering a wide range of functionalities, such as run time and static checking. But the tools existent so far for static checking are not fully automated, and, those that are, do not offer an adequate level of soundness and completeness. Our objective is to contribute to a series of techniques, that can be used to accomplish a fully automated and confident verification of JavaCard applets. In this work we present the first steps to this. With the use of a software platform comprised by Krakatoa, Why and haRVey, we developed a set of techniques to reduce the size of the theory necessary to verify the specifications. Such techniques have yielded very good results, with gains of almost 100% in all tested cases, and has proved as a valuable technique to be used, not only in this, but in most real world problems related to automatic verification

Implementação da técnica de software pipelining na rede em chip IPNoSyS

Alongside the advances of technologies, embedded systems are increasingly present in our everyday. Due to increasing demand for functionalities, many tasks are split among processors, requiring more efficient communication architectures, such as networks on chip (NoC). The NoCs are structures that have routers with channel point-to-point interconnect the cores of system on chip (SoC), providing communication. There are several networks on chip in the literature, each with its specific characteristics. Among these, for this work was chosen the Integrated Processing System NoC (IPNoSyS) as a network on chip with different characteristics compared to general NoCs, because their routing components also accumulate processing function, ie, units have functional able to execute instructions. With this new model, packets are processed and routed by the router architecture. This work aims at improving the performance of applications that have repetition, since these applications spend more time in their execution, which occurs through repeated execution of his instructions. Thus, this work proposes to optimize the runtime of these structures by employing a technique of instruction-level parallelism, in order to optimize the resources offered by the architecture. The applications are tested on a dedicated simulator and the results compared with the original version of the architecture, which in turn, implements only packet level parallelism

Controle adaptativo por modelo de referencia e estrutura variável discreto no tempo

With the technology progess, embedded systems using adaptive techniques are being used frequently. One of these techniques is the Variable Structure Model- Reference Adaptive Control (VS-MRAC). The implementation of this technique in embedded systems, requires consideration of a sampling period which if not taken into consideration, can adversely affect system performance and even takes the system to instability. This work proposes a stability analysis of a discrete-time VS-MRAC accomplished for SISO linear time-invariant plants with relative degree one. The aim is to analyse the in uence of the sampling period in the system performance and the relation of this period with the chattering and system instability