A framework for fault tolerant real time systems based on reconfigurable FPGAs

To increase the amount of logic available to the users in SRAM-based FPGAs, manufacturers are using nanometric technologies to boost logic density and reduce costs, making its use more attractive. However, these technological improvements also make FPGAs particularly vulnerable to configuration memory bit-flips caused by power fluctuations, strong electromagnetic fields and radiation. This issue is particularly sensitive because of the increasing amount of configuration memory cells needed to define their functionality. A short survey of the most recent publications is presented to support the options assumed during the definition of a framework for implementing circuits immune to bit-flips induction mechanisms in memory cells, based on a customized redundant infrastructure and on a detection-and-fix controller.

Work-in-progress on a thin IEEE1451.0 - architecture to implement reconfigurable Weblab infrastructures

Institutions have been creating their own specific weblab infrastructures. Usually, they use distinct software and hardware architectures comprehending instruments and modules (I&M) able to be parameterized but difficult to be shared. These aspects are impairing their widespread in education, since collaboration between institutions, in developing and sharing resources, is still low. To handle both aspects, this paper proposes the adoption of the IEEE1451.0 Std. with FPGA technology for creating reconfigurable weblab infrastructures. It is suggested the adoption of an IEEE1451.0 infrastructure with compatible instruments, described in Hardware Description Languages (HDL), to be reconfigured in FPGA-based boards. Besides an overview of the IEEE1451.0 Std., this paper presents a solution currently under development which seeks to enable the reconfiguration and the remote control of weblab infrastructures using a set of IEEE1451.0 HTTP commands.

On-line defragmentation for run-time partially reconfigurable FPGAs

Dynamically reconfigurable systems have benefited from a new class of FPGAs recently introduced into the market, which allow partial and dynamic reconfiguration at run-time, enabling multiple independent functions from different applications to share the same device, swapping resources as needed. When the sequence of tasks to be performed is not predictable, resource allocation decisions have to be made on-line, fragmenting the FPGA logic space. A rearrangement may be necessary to get enough contiguous space to efficiently implement incoming functions, to avoid spreading their components and, as a result, degrading their performance. This paper presents a novel active replication mechanism for configurable logic blocks (CLBs), able to implement on-line rearrangements, defragmenting the available FPGA resources without disturbing those functions that are currently running.

A new approach to assess defragmentation strategies in dynamically reconfigurable FPGAs

Fragmentation on dynamically reconfigurable FPGAs is a major obstacle to the efficient management of the logic space in reconfigurable systems. When resource allocation decisions have to be made at run-time a rearrangement may be necessary to release enough contiguous resources to implement incoming functions. The feasibility of run-time relocation depends on the processing time required to set up rearrangements. Moreover, the performance of the relocated functions should not be affected by this process or otherwise the whole system performance, and even its operation, may be at risk. Relocation should take into account not only specific functional issues, but also the FPGA architecture, since these two aspects are normally intertwined. A simple and fast method to assess performance degradation of a function during relocation and to speed up the defragmentation process, based on previous function labelling and on the application of the Euclidian distance concept, is proposed in this paper.

Reconfigurable antenna for mobile terminal

Trabalho Final de Mestrado para obtenção do grau de Mestrado em Engenharia Electrónica e Telecomunicações

Run-time defragmentation for dynamically reconfigurable hardware

Reconfigurable computing experienced a considerable expansion in the last few years, due in part to the fast run-time partial reconfiguration features offered by recent SRAM-based Field Programmable Gate Arrays (FPGAs), which allowed the implementation in real-time of dynamic resource allocation strategies, with multiple independent functions from different applications sharing the same logic resources in the space and temporal domains. However, when the sequence of reconfigurations to be performed is not predictable, the efficient management of the logic space available becomes the greatest challenge posed to these systems. Resource allocation decisions have to be made concurrently with system operation, taking into account function priorities and optimizing the space currently available. As a consequence of the unpredictability of this allocation procedure, the logic space becomes fragmented, with many small areas of free resources failing to satisfy most requests and so remaining unused. A rearrangement of the currently running functions is therefore necessary, so as to obtain enough contiguous space to implement incoming functions, avoiding the spreading of their components and the resulting degradation of system performance. A novel active relocation procedure for Configurable Logic Blocks (CLBs) is herein presented, able to carry out online rearrangements, defragmenting the available FPGA resources without disturbing functions currently running.

Sparse matrix multiplication on a reconfigurable many-core architecture

Sparse matrix-vector multiplication (SMVM) is a fundamental operation in many scientific and engineering applications. In many cases sparse matrices have thousands of rows and columns where most of the entries are zero, while non-zero data is spread over the matrix. This sparsity of data locality reduces the effectiveness of data cache in general-purpose processors quite reducing their performance efficiency when compared to what is achieved with dense matrix multiplication. In this paper, we propose a parallel processing solution for SMVM in a many-core architecture. The architecture is tested with known benchmarks using a ZYNQ-7020 FPGA. The architecture is scalable in the number of core elements and limited only by the available memory bandwidth. It achieves performance efficiencies up to almost 70% and better performances than previous FPGA designs.

Controller implementation using analog reconfigurable hardware (FPAA)

This Thesis has the main target to make a research about FPAA/dpASPs devices and technologies applied to control systems. These devices provide easy way to emulate analog circuits that can be reconfigurable by programming tools from manufactures and in case of dpASPs are able to be dynamically reconfigurable on the fly. It is described different kinds of technologies commercially available and also academic projects from researcher groups. These technologies are very recent and are in ramp up development to achieve a level of flexibility and integration to penetrate more easily the market. As occurs with CPLD/FPGAs, the FPAA/dpASPs technologies have the target to increase the productivity, reducing the development time and make easier future hardware reconfigurations reducing the costs. FPAA/dpAsps still have some limitations comparing with the classic analog circuits due to lower working frequencies and emulation of complex circuits that require more components inside the integrated circuit. However, they have great advantages in sensor signal condition, filter circuits and control systems. This thesis focuses practical implementations of these technologies to control system PID controllers. The result of the experiments confirms the efficacy of FPAA/dpASPs on signal condition and control systems.

Reconfigurable photonic logic architecture

The amorphous silicon photo-sensor studied in this thesis, is a double pin structure (p(a-SiC:H)-i’(a-SiC:H)-n(a-SiC:H)-p(a-SiC:H)-i(a-Si:H)-n(a-Si:H)) sandwiched between two transparent contacts deposited over transparent glass thus with the possibility of illumination on both sides, responding to wave-lengths from the ultra-violet, visible to the near infrared range. The frontal il-lumination surface, glass side, is used for light signal inputs. Both surfaces are used for optical bias, which changes the dynamic characteristics of the photo-sensor resulting in different outputs for the same input. Experimental studies were made with the photo-sensor to evaluate its applicability in multiplexing and demultiplexing several data communication channels. The digital light sig-nal was defined to implement simple logical operations like the NOT, AND, OR, and complex like the XOR, MAJ, full-adder and memory effect. A pro-grammable pattern emission system was built and also those for the validation and recovery of the obtained signals. This photo-sensor has applications in op-tical communications with several wavelengths, as a wavelength detector and to execute directly logical operations over digital light input signals.

OnBoard reconfigurable battery charger for electric vehicles with traction-to-auxiliary mode

This paper proposes a single-phase reconfigurable battery charger for Electric Vehicle (EV) that operates in three different modes: Grid-to-Vehicle (G2V) mode, in which the traction batteries are charged from the power grid; Vehicle-to-Grid (V2G) mode, in which the traction batteries deliver part of the stored energy back to the power grid; and in Traction-to-Auxiliary (T2A) mode, in which the auxiliary battery is charged from the traction batteries. When connected to the power grid, the battery charger works with sinusoidal current in the AC side, for both G2V and V2G modes, and also regulates the reactive power. When the EV is disconnected from the power grid, the control algorithms are modified and the full-bridge AC-DC bidirectional converter works as a full-bridge isolated DC-DC converter that is used to charge the auxiliary battery of the EV, avoiding the use of an additional charger to accomplish this task. To assess the behavior of the proposed reconfigurable battery charger under different operation scenarios, a 3.6 kW laboratory prototype has been developed and experimental results are presented.

La protection des biotopes en droit suisse : étude de droit matériel

Introduction : Confronter les intérêts de la protection de la nature à d'autres, c'est vouloir faire passer les petites fleurs et les grenouilles avant l'Homme. Hérésie ! C'est en effet parfois l'existence même d'un régime légal de protection des biotopes qui fait sourire. L'étudier en profondeur n'en paraît que plus oiseux. Ce problème d'acceptation est sans doute propre au droit de l'environnement de manière générale : l'intérêt public défendu ici n'est pas rattachable directement à l'intérêt du plus grand nombre. On peut parfois même en être très loin. Si, malgré cela, certains domaines du droit de l'environnement sont actuellement très en vogue, la protection de la nature fait partie de ses aspects moins porteurs. Ce type de préoccupations est pour beaucoup futile, voire inutile ou même déplacé. Il apparaît ainsi important de commencer par se demander pourquoi protéger la nature, et que protéger dans cette nature (chapitre 1). Vient ensuite évidemment la question de la portée de la protection. Il convient pour cela tout d'abord de faire le point sur le droit en vigueur (chapitre 2) : l'histoire des règles topiques en matière de protection des biotopes a été particulièrement mouvementée et son analyse apporte un important éclairage à la compréhension des dispositions actuelles ; cette législation est en outre complétée par une multitude de dispositions connexes ou apparentées, de droit interne et de droit international. Ce contexte général posé, la portée de la protection s'examine plus précisément par l'analyse des articles 18 ss LPN (chapitre 3) : les biotopes protégés de manière générale par l'article 18 LPN lui-même - remarquable exemple d'un droit dynamique -, les biotopes inventoriés et la végétation des rives. Il est enfin nécessaire de se pencher sur le « comment protéger» par une étude des instruments de mise en oeuvre (chapitre 4) et des instruments auxiliaires à la protection (chapitre 5). Ce faisant, la pertinence du régime légal de protection des biotopes sera soulignée, tant sur le fond que sur la forme. En l'introduisant aux subtilités de ce régime et de son intégration dans l'ordre juridique en général, nous espérons ainsi faire passer le lecteur au-delà des idées reçues.