GIDL behavior of p- and n-MuGFET devices with different TiN metal gate thickness and high-k gate dielectrics

This work studies the gate-induced drain leakage (GIDL) in p- and n-MuGFET structures with different TiN metal gate thickness and high-k gate dielectrics. As a result of this analysis, it was observed that a thinner TiN metal gate showed a larger GIDL due to the different gate oxide thickness and a reduced metal gate work function. In addition, replacing SiON by a high-k dielectric (HfSiON) results for nMuGFETs in a decrease of the GIDL On the other hand, the impact of the gate dielectric on the GIDL for p-channel MuGFETs is marginal. The effect of the channel width was also studied, whereby narrow fin devices exhibit a reduced GIDL current in spite of the larger vertical electric field expected for these devices. Finally, comparing the effect of the channel type, an enhanced GIDL current for pMuGFET devices was observed. (C) 2011 Elsevier Ltd. All rights reserved.

Development of high-k gate dielectric materials

The traditional gate dielectric material Of SiO2 can not satisfy the need of the continuous downscaling of CMOS dimensions. High-K gate dielectric materials have attracted extensive research efforts recently and obtained great progress. In this paper, the developments of high-K gate materials were reviewed. Based on the author's background and research work in the area, the latest achievements of high-K gate dielectric materials on the recrystalization temperature, the low-K interface layer, and the dielectric breakdown and metal gate electrode were introduced in detail.

Organic Thin-Film Transistor Memory With Nanoparticle Floating Gate

Organic thin-film transistor memory devices were realized by inserting a layer of nanoparticles (such as Ag or CaF2) between two Nylon 6 gate dielectrics as the floating gate. The transistor memories were fabricated on glass substrates by full thermal deposition. The transistors exhibit significant hysteresis behavior in current-voltage characteristics, due to the separated Ag or CaF2 nanoparticle islands that act as charge trap centers. The mechanism of the transistor memory operation was discussed.

Electrical characterization of copper phthalocyanine thin-film transistors with fluoride gate insulator

Different fluoride materials are used as gate dielectrics to fabricate copper phthalocyanine (CuPc) thin film. transistors (OTFTs). The fabricated devices exhibit good electrical characteristics and the mobility is found to be dependent on the gate voltage from 10(-3) to 10(-1) cm(2) V(-1)s(-1). The observed noticeable electron injection at the drain electrode is of great significance in achieving ambipolar OTFTs. The same method for formation of organic semiconductors and gate dielectric films greatly simplifies the fabrication process. This provides a convenient way to produce high-performance OTFTs on a large scale and should be useful for integration in organic displays.

Preparation and Characterization ofHigh-k Aluminum Oxide Thin Films by Atomic Layer Deposition for Gate Dielectric Applications

Present work deals with the Preparation and characterization of high-k aluminum oxide thin films by atomic layer deposition for gate dielectric applications.The ever-increasing demand for functionality and speed for semiconductor applications requires enhanced performance, which is achieved by the continuous miniaturization of CMOS dimensions. Because of this miniaturization, several parameters, such as the dielectric thickness, come within reach of their physical limit. As the required oxide thickness approaches the sub- l nm range, SiO 2 become unsuitable as a gate dielectric because its limited physical thickness results in excessive leakage current through the gate stack, affecting the long-term reliability of the device. This leakage issue is solved in the 45 mn technology node by the integration of high-k based gate dielectrics, as their higher k-value allows a physically thicker layer while targeting the same capacitance and Equivalent Oxide Thickness (EOT). Moreover, Intel announced that Atomic Layer Deposition (ALD) would be applied to grow these materials on the Si substrate. ALD is based on the sequential use of self-limiting surface reactions of a metallic and oxidizing precursor. This self-limiting feature allows control of material growth and properties at the atomic level, which makes ALD well-suited for the deposition of highly uniform and conformal layers in CMOS devices, even if these have challenging 3D topologies with high aspect-ratios. ALD has currently acquired the status of state-of-the-art and most preferred deposition technique, for producing nano layers of various materials of technological importance. This technique can be adapted to different situations where precision in thickness and perfection in structures are required, especially in the microelectronic scenario.

Temperature performance of AlGaN/GaN MOS-HEMTs on Si substrates using Gd2O3 as gate dielectric

GaN based high electron mobility transistors have draw great attention due to its potential in high temperature, high power and high frequency applications [1, 2]. However, significant gate leakage current is still one of the issues which need to be solved to improve the performance and reliability of the devices [3]. Several research groups have contributed to solve this problem by using metal–oxide–semiconductor HEMTs (MOSHEMTs), with a thin dielectric layer, such as SiO2 [4], Al2O3 [5], HfO2 [6] and Gd2O3 [7] between the gate and the barrier layer on AlGaN/GaN heterostructures. Gd2O3 has shown low interfacial density of states(Dit) with GaN and a high dielectric constant and low electrical leakage currents [8], thus is considered as a promising candidate for the gate dielectrics on GaN. MOS-HEMTs using Gd2O3 grown by electron-beam heating [7] or molecular beam epitaxy (MBE) [8] on GaN or AlGan/GaN structure have been investigated, but further research is still needed in Gd2O3 based AlGaN/GaN MOSHEMTs.

Effect of Post-Metallization Hydrogen Annealing on C-V Characteristic of Zirconia Grown Using Atomic Layer Deposition

Substantial amount of fixed charge present in most of the alternative gate dielectrics gives rise to large shifts in the flat-band voltage (VFB) and charge trapping and de-trapping causes hysterectic changes on voltage cycling. Both phenomena affect stable and reliable transistor operation. In this paper we have studied for the first time the effect of post-metallization hydrogen annealing on the C-V curve of MOS capacitors employing zirconia, one of the most promising gate dielectric. Samples were annealed in hydrogen ambient for up to 30 minutes at different temperatures ranging from room temperature to 400°C. C-V measurements were done after annealing at each temperature and the hysteresis width was calculated from the C-V curves. A minimum hysteresis width of ∼35 mV was observed on annealing the sample at 200°C confirming the excellent suitability of this dielectric

Structural, electrical and dielectric properties of sputtered TiO2 films for Al/TiO2/Si capacitors

Metal-oxide semiconductor capacitors based on titanium dioxide (TiO2) gate dielectrics were prepared by RF magnetron sputtering technique. The deposited films were post-annealed at temperatures in the range 773-1173 K in air for 1 hour. The effect of annealing temperature on the structural properties of TiO2 films was investigated by X-ray diffraction and Raman spectroscopy, the surface morphology was studied by atomic force microscopy (AFM) and the electrical properties of Al/TiO2/p-Si structure were measured recording capacitance-voltage and current-voltage characteristics. The as-deposited films and the films annealed at temperatures lower than 773 K formed in the anatase phase, while those annealed at temperatures higher than 973 K were made of mixtures of the rutile and anatase phases. FTIR analysis revealed that, in the case of films annealed at 1173 K, an interfacial layer had formed, thereby reducing the dielectric constant. The dielectric constant of the as-deposited films was 14 and increased from 25 to 50 with increases in the annealing temperature from 773 to 973 K. The leakage current density of as-deposited films was 1.7 x 10(-5) and decreased from 4.7 X 10(-6) to 3.5 x 10(-9) A/cm(2) with increases in the annealing temperature from 773 to 1173 K. The electrical conduction in the Al/TiO2/p-Si structures was studied on the basis of the plots of Schottky emission, Poole-Frenkel emission and Fowler-Nordheim tunnelling. The effect of structural changes on the current-voltage and capacitance-voltage characteristics of Al/TiO2/p-Si capacitors was also discussed.

Photoluminescence behaviors from stoichiometric gadolinium oxide films

Stoichiometric gadolinium oxide thin films have been grown on silicon (100) substrates with a low-energy dual ion-beam epitaxial technique. Gadolinium oxide shares Gd2O3 structures although the ratio of gadolinium and oxygen in the film is about 2:1 and a lot of oxygen deficiencies exist. Photoluminescence (PL) measurements have been carried out within a temperature range of 5-300 K. The detailed characters of the PL emission integrated intensity, peak position, and peak width at different temperature were reported and an anomalous photoluminescence behavior was observed. The character of PL emission integrated intensity is similar to that of some other materials such as porous silicon and silicon nanocrystals in silicon dioxide. Four peaks relative to alpha band and beta band were observed also. Therefore we suggest that the nanoclusters with the oxygen deficiencies contribute to the PL emission and the model of singlet-triplet exchange splitting of exciton was employed for discussion. (C) 2003 American Institute of Physics.

Very low hysteresis organic thin-film transistors

Very low hysteresis vanadyl-phthalocyanine/para-sexiphenyl thin-film transistors (TFTs) have been fabricated using benzocyclobutenone (BCBO) derivatives/tantalum pentoxide (Ta2O5)/BCBO triple gate dielectrics. The field effect mobility, on/off current ratio and threshold voltage of organic TFTs are 0.45 cm(2) V-1 s(-1), 3.5 x 10(4) and -6.8 V, respectively. To clarify the mechanism of hysteresis, devices with different dielectrics have been studied. It is found that the bottom BCBO derivatives (contact with a gate electrode) block the electron injection from a gate electrode to dielectrics.

Bilayer Photoresist Insulator for High Performance Organic Thin-Film Transistors on Plastic Films

A novel bilayer photoresist insulator is applied in flexible vanadyl-phthalocyanine (VOPc) organic thin-film transistors (OTFTs). The micron-size patterns of this photoresisit insulator can be directly defined only by photolithography without the etching process. Furthermore, these OTFTs exhibit high field-effect mobility (about 0.8 cm(2)/Vs) and current on/off ratio (about 10(6)). In particular, they show rather low hysteresis (< 1 V). The results demonstrate that this bilayer photoresist insulator can be applied in large-area electronics and in the facilitation of patterning insulators.

Improved performance by a double-insulator layer in organic thin-flim transistors

Organic thin film transistors based on pentacene are fabricated by the method of full evaporation. The thickness of insulator film can be controlled accurately, which influences the device operation voltage markedly. Compared to the devices with a single-insulator layer, the electric performance of devices by using a double-insulator as the gate dielectric has good improvement. It is found that the gate leakage current can be reduced over one order of magnitude, and the on-state current can be enhanced over one order of magnitude. The devices with double-insulator layer exhibit field-effect mobility as large as 0.14 cm(2)/Vs and near the zero threshold voltage. The results demonstrate that using proper double insulator as the gate dielectrics is an effective method to fabricate OTFTs with high electrical performance.

Electrical characterization of poly(amide-imide) for application in organic field effect devices

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)