Decimal Multiplication using compact BCD Multiplier

Decimal multiplication is an integral part offinancial, commercial, and internet-based computations. The basic building block of a decimal multiplier is a single digit multiplier. It accepts two Binary Coded Decimal (BCD) inputs and gives a product in the range [0, 81] represented by two BCD digits. A novel design for single digit decimal multiplication that reduces the critical path delay and area is proposed in this research. Out of the possible 256 combinations for the 8-bit input, only hundred combinations are valid BCD inputs. In the hundred valid combinations only four combinations require 4 x 4 multiplication, combinations need x multiplication, and the remaining combinations use either x or x 3 multiplication. The proposed design makes use of this property. This design leads to more regular VLSI implementation, and does not require special registers for storing easy multiples. This is a fully parallel multiplier utilizing only combinational logic, and is extended to a Hex/Decimal multiplier that gives either a decimal output or a binary output. The accumulation ofpartial products generated using single digit multipliers is done by an array of multi-operand BCD adders for an (n-digit x n-digit) multiplication.

A new look at reversible logic implementation of decimal adder

Reversibility plays a fundamental role when logic gates such as AND, OR, and XOR are not reversible. computations with minimal energy dissipation are considered. Hence, these gates dissipate heat and may reduce the life of In recent years, reversible logic has emerged as one of the most the circuit. So, reversible logic is in demand in power aware important approaches for power optimization with its circuits. application in low power CMOS, quantum computing and A reversible conventional BCD adder was proposed in using conventional reversible gates.

Performance analysis of double digit decimal multiplier on various FPGA logic families

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of (n / 2) 1 cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard

High performance, low latency double digit decimal multiplier on ASIC and FPGA

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated using Leonardo Spectrum from Mentor Graphics Corporation using ASIC Library. The paper also presents area and delay comparisons for these fixed point multipliers on Xilinx, Altera, Actel and Quick logic FPGAs. This multiplier design can be extended to support decimal floating point multiplication for IEEE 754- 2008 standard.

Fixed Point Decimal Multiplication Using RPS Algorithm

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. A novel design for single digit decimal multiplication that reduces the critical path delay and area for an iterative multiplier is proposed in this research. The partial products are generated using single digit multipliers, and are accumulated based on a novel RPS algorithm. This design uses n single digit multipliers for an n × n multiplication. The latency for the multiplication of two n-digit Binary Coded Decimal (BCD) operands is (n + 1) cycles and a new multiplication can begin every n cycle. The accumulation of final partial products and the first iteration of partial product generation for next set of inputs are done simultaneously. This iterative decimal multiplier offers low latency and high throughput, and can be extended for decimal floating-point multiplication.

Performance Analysis of Reversible Fast Decimal Adders

This paper presents a performance analysis of reversible, fault tolerant VLSI implementations of carry select and hybrid decimal adders suitable for multi-digit BCD addition. The designs enable partial parallel processing of all digits that perform high-speed addition in decimal domain. When the number of digits is more than 25 the hybrid decimal adder can operate 5 times faster than conventional decimal adder using classical logic gates. The speed up factor of hybrid adder increases above 10 when the number of decimal digits is more than 25 for reversible logic implementation. Such highspeed decimal adders find applications in real time processors and internet-based applications. The implementations use only reversible conservative Fredkin gates, which make it suitable for VLSI circuits.

Sailkapen Hamartar Unibertsala eskola curriculumetan : unibertsitatekoak ez diren eskoletako liburutegietan fondoak gaiz gai antolatzeko jarraibideak. 'La Clasificación Decimal Universal en los curriculos escolares'.

Resumen tomado de la web del Departamento de Educación

La Clasificación Decimal Universal en los Currículos Escolares : instrucciones para la organización temática de los fondos bibliográficos de las bibliotecas educativas no universitarias.

Resumen basado en el de la publicación

Número decimal.

Se realiza un estudio sobre el sistema de los números decimales partiendo de la unidad simple. Se aportan algunos ejercicios prácticos con el fin de saber reunir unidades enteras y decimales, representar los números decimales, conocer la lectura de los números decimales, la igualdad y desigualdad de números decimales, y sumar, restar, multiplicar y dividir números decimales.

Construimos los números : descubrimos sus secretos : (didáctica del sistema decimal).

Monográfico con el título: 'Enseñar matemáticas'

Estudio de un alumno con s??ndrome de Down en la comprensi??n del sistema de numeraci??n decimal

Resumen tomado de la publicaci??n

Decimal growth stages for precision wheat production in changing environments?

The utility of the decimal growth stage (DGS) scoring system for cereals is reviewed. The DGS is the most widely used scale in academic and commercial applications because of its comprehensive coverage of cereal developmental stages, the ease of use and definition provided and adoption by official agencies. The DGS has demonstrable and established value in helping to optimise the timing of agronomic inputs, particularly with regard to plant growth regulators, herbicides, fungicides and soluble nitrogen fertilisers. In addition, the DGS is used to help parameterise crop models, and also in understanding the response and adaptation of crops to the environment. The value of the DGS for increasing precision relies on it indicating, to some degree, the various stages in the development of the stem apex and spike. Coincidence of specific growth stage scores with the transition of the apical meristem from a vegetative to a reproductive state, and also with the period of meiosis, is unreliable. Nonetheless, in pot experiments it is shown that the broad period of booting (DGS 41–49) appears adequate for covering the duration when the vulnerability of meiosis to drought and heat stress is exposed. Similarly, the duration of anthesis (61–69) is particularly susceptible to abiotic stresses: initially from a fertility perspective, but increasingly from a mean grain weight perspective as flowering progresses to DGS 69 and then milk development. These associations with DGS can have value at the crop level of organisation: for interpreting environmental effects, and in crop modelling. However, genetic, biochemical and physiological analysis to develop greater understanding of stress acclimation during the vegetative state, and tolerance at meiosis, does require more precision than DGS can provide. Similarly, individual floret analysis is needed to further understand the genetic basis of stress tolerance during anthesis.

Aprendendo e ensinando o sistema de numeração decimal: uma contribuição à prática pedagógica do professor

The central question of the present study is to identify the epistemological knowledge that the teachers-trainees possess regarding the characteristics (properties) of the decimal numbering system; its purpose is to offer a contribution to the pedagogic practice of the teachers who work within the Basic Literacy Cycle, in terms of what concerns both the acquisition of contents and the development of the knowledge that helps them in the elaboration of adequate strategies to working with the Decimal Numbering System in the classroom. The study is based on the constructivist sociointeractionist approach to teaching Mathematics and it constitutes, in itself, a methodological intervention with the teachers-trainees engaged in the Professional Qualification Program in Basic Education of the Federal University of Rio Grande do Norte. The foundations of the study were found in investigations of researchers who had carried out studies on the construction of numerical writing, showing, for instance, that the construction process of ideas and procedures involved in groupings and changes to base 10 take a lot longer to be accomplished than one can imagine. A set of activities was then elaborated which could not only contribute to the acquisition of contents but that could also make the teachers-trainees reflect upon their teaching practices in the classroom so that in this way they will be able to elaborate more consistent didactic approaches, taking into consideration the previous knowledge of the students and also some obstacles that often appear along the way. Even when teachers have access to the most appropriate dicactic resources, the lack of knowledge of the content and of the real meaning of that content make the Decimal Numbering System, a subject of fundamental importance, be taught most times in a mechanical way. The analisys of the discussions and behaviours of the teachers-trainees during the activities reavealed that they made them reflect upon their current practices in the classroom and that, as a whole, the aims of each of the activities carried out with the teachers-trainers were reached

Organização temática da doutrina jurídica: elementos metodológicos para uma proposta de extensão da classificação decimal de direito

Specificity and updating of the bibliographic classification systems can be considered a determinant factor to the quality of organization and representation of the legal documentation. In the specific case of Brazil, the Brazilian Law Decimal Classification, does not foresee specific subdivisions for Labor Law procedures. In this sense, it carries out a terminological work based on table of contents of doctrinal Labor Law books of the mentioned area, which are compared to the conceptual structure of the Brazilian Law Decimal Classification. As a result, it presents an extension proposal for Labor Procedures as well as a methodological background for further extensions and updates.

Uso social e escolar dos números racionais: representação fracionária e decimal

Pós-graduação em Educação - FFC