Field programmable gate array based predictive control system for spacecraft rendezvous in elliptical orbits

Copyright © 2014 John Wiley & Sons, Ltd. Copyright © 2014 John Wiley & Sons, Ltd. Summary A field programmable gate array (FPGA) based model predictive controller for two phases of spacecraft rendezvous is presented. Linear time-varying prediction models are used to accommodate elliptical orbits, and a variable prediction horizon is used to facilitate finite time completion of the longer range manoeuvres, whilst a fixed and receding prediction horizon is used for fine-grained tracking at close range. The resulting constrained optimisation problems are solved using a primal-dual interior point algorithm. The majority of the computational demand is in solving a system of simultaneous linear equations at each iteration of this algorithm. To accelerate these operations, a custom circuit is implemented, using a combination of Mathworks HDL Coder and Xilinx System Generator for DSP, and used as a peripheral to a MicroBlaze soft-core processor on the FPGA, on which the remainder of the system is implemented. Certain logic that can be hard-coded for fixed sized problems is implemented to be configurable online, in order to accommodate the varying problem sizes associated with the variable prediction horizon. The system is demonstrated in closed-loop by linking the FPGA with a simulation of the spacecraft dynamics running in Simulink on a PC, using Ethernet. Timing comparisons indicate that the custom implementation is substantially faster than pure embedded software-based interior point methods running on the same MicroBlaze and could be competitive with a pure custom hardware implementation.

A 1,000 Frames/s Programmable Vision Chip with Variable Resolution and Row-Pixel-Mixed Parallel Image Processors

A programmable vision chip with variable resolution and row-pixel-mixed parallel image processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit Algorithmic ADCs, row-parallel gray-scale image processors, pixel-parallel SIMD Processing Element (PE) array, and instruction controller. The resolution of the image in the chip is variable: high resolution for a focused area and low resolution for general view. It implements gray-scale and binary mathematical morphology algorithms in series to carry out low-level and mid-level image processing and sends out features of the image for various applications. It can perform image processing at over 1,000 frames/s (fps). A prototype chip with 64 x 64 pixels resolution and 6-bit gray-scale image is fabricated in 0.18 mu m Standard CMOS process. The area size of chip is 1.5 mm x 3.5 mm. Each pixel size is 9.5 mu m x 9.5 mu m and each processing element size is 23 mu m x 29 mu m. The experiment results demonstrate that the chip can perform low-level and mid-level image processing and it can be applied in the real-time vision applications, such as high speed target tracking.

Design and implementation of a field programmable CRC circuit architecture

The design and implementation of a programmable cyclic redundancy check (CRC) computation circuit architecture, suitable for deployment in network related system-on-chips (SoCs) is presented. The architecture has been designed to be field reprogrammable so that it is fully flexible in terms of the polynomial deployed and the input port width. The circuit includes an embedded configuration controller that has a low reconfiguration time and hardware cost. The circuit has been synthesised and mapped to 130-nm UMC standard cell [application-specific integrated circuit (ASIC)] technology and is capable of supporting line speeds of 5 Gb/s. © 2006 IEEE.

Embedded C programming: a practical course introducing programmable microprocessors

This paper presents a new laboratory-based module for embedded systems teaching, which addresses the current lack of consideration for the link between hardware development, software implementation, course content and student evaluation in a laboratory environment. The course introduces second year undergraduate students to the interface between hardware and software and the programming of embedded devices; in this case, the PIC (originally peripheral interface controller, later rebranded programmable intelligent computer) microcontroller. A hardware development board designed for use in the laboratories of this module is presented. Through hands on laboratory experience, students are encouraged to engage with practical problem-solving exercises and develop programming skills across a broad range of scenarios.

Clinical potential and design of programmable mechanical impedances for orthotic applications

A person with a moderate or severe motor disability will often use specialised or adapted tools to assist their interaction with a general environment. Such tools can assist with the movement of a person's arms so as to facilitate manipulation, can provide postural supports, or interface to computers, wheelchairs or similar assistive technologies. Designing such devices with programmable stiffness and damping may offer a better means for the person to have effective control of their surroundings. This paper addresses the possibility of designing some assistive technologies using impedance elements that can adapt to the user and the circumstances. Two impedance elements are proposed. The first, based on magnetic particle brakes, allows control of the damping coefficient in a passive element. The second, based on detuning the P-D controller in a servo-motor mechanism, allows control of both stiffness and damping. Such a mechanical impedance can be modulated to the conditions imposed by the task in hand. The limits of linear theory are explored and possible uses of programmable impedance elements are proposed.

A VHDL-based protocol controller for NCAP processors

This work presents the development of an IEEE 1451.2 protocol controller based on a low-cost FPGA that is directly connected to the parallel port of a conventional personal computer. In this manner it is possible to implement a Network Capable Application Processor (NCAP) based on a personal computer, without parallel port modifications. This approach allows supporting the ten signal lines of the 10-wire IEEE 1451.2 Transducer Independent Interface (TII), that connects the network processor to the Smart Transducer Interface Module (STIM) also defined in the IEEE 1451.2 standard. The protocol controller is connected to the STIM through the TII's physical interface, enabling the portability of the application at the transducer and network processor level. The protocol controller architecture was fully developed in VHDL language and we have projected a special prototype configured in a general-purpose programmable logic device. We have implemented two versions of the protocol controller, which is based on IEEE 1451 standard, and we have obtained results using simulation and experimental tests. (c) 2008 Elsevier B.V. All rights reserved.

Hardware implementation of type-2 programmable fuzzifier

The design of full programmable type-2 membership function circuit is presented in this paper. This circuit is used to implement the fuzzifier block of Type-2 Fuzzy Logic Controller chip. In this paper the type-2 fuzzy set was obtained by blurring the width of the type-1 fuzzy set. This circuit allows programming the height and the shape of the membership function. It operates in current mode, with supply voltage of 3.3V. The simulation results of interval type-2 membership function circuit have been done in CMOS 0.35μm technology using Mentor Graphics software. © 2011 IEEE.

Design of microprogrammed controllers with address converter implemented on programmable systems with embedded memories

In the paper the improvement of a traditional structure of a microprogrammed controller with sharing codes is discussed. The idea is based on the modification of internal modules and connections of the device. Such a solution permits to reduce the number of embedded memories needed for implementation of the microprogrammed controller on programmable structures, especially FPGAs. © 2011 IEEE.

Programmable electronic platform for the remote control of the cell-migration galvanotaxis

Il presente lavoro di tesi nasce come collaborazione tra il Laboratorio di Progettazione Elettronica e il Laboratorio di Microscopia a Fluorescenza del Dipartimento di Fisica e Astronomia dell' Università di Bologna. In particolare nasce dalla volontà di dotare il dipartimento di un apparato sperimentale in grado di svolgere studi sulla Galvanotassia, un fenomeno biologico consistente nella migrazione di cellule sottoposte a stimolazione elettrica. La Galvanotassia è nota da fine '800 ma non sono ancora chiari i meccanismi cellulari che la provocano. Una migliore comprensione di tale fenomeno potrebbe portare importanti sviluppi in ambito medico, sia diagnostici che terapeutici. Dalla letteratura a riguardo non è emersa l'esistenza di apparecchi elettronici di controllo che permettano lo studio della Galvanotassia e che possano essere duttili a seconda del tipo di esperimento che si voglia svolgere. Da qui l'idea di iniziare lo sviluppo di un dispositivo elettronico, che fosse riprogrammabile, a basso costo e facilmente trasportabile. La progettazione di questo dispositivo ha portato ad una prima fase di test e verifiche sperimentali che hanno permesso di migliorare e affinare la costruzione di uno strumento di misura e controllo dei parametri relativi alla Galvanotassia. Sono già stati programmati test futuri che porteranno ad una versione definitiva dell' apparecchiatura alla quale succederanno più approfondite ricerche sul fenomeno della Galvanotassia.

Controlador MIDI basado en Arduino

El presente proyecto tiene como objetivo la creación de un controlador MIDI económico que haga uso de la tecnología actual, y partiendo de la idea del instrumento clásico, el Theremin, desarrollado por Lev Serguéievich Termen. Para ello se ha dividido el proyecto en dos principales bloques, el primero, hardware y el segundo, software. En la parte del hardware, se explica cual ha sido la razón de la utilización del microprocesador Arduino Uno, sus características técnicas y el uso de sensores de ultrasonido, ya que proporcionan la característica de poder interactuar con el controlador a través de gestos con las manos, al igual que un Theremin clásico. Se explica el montaje de los dispositivos que conforman el controlador, así como la mejora realizada, con la utilización de 4 de estos sensores, para dar más capacidades de interactuación con el controlador MIDI. También se ve en ese apartado, como se programa la tarjeta de Arduino, para que se encargue de realizar medidas con los sensores y enviarlas por el puerto serial USB. En el apartado del software se da una introducción al entorno de programación Max/MSP. Se ve el plug in desarrollado con este lenguaje, para poder comunicar el controlador MIDI con un software de audio profesional (Ableton Live) y se explica con detalle los bloques que conforman el plug in de control de sensores y como es transformada la información que entrega el microprocesador Arduino por el puerto USB, en datos MIDI. También, se da una explicación sobre el manejo correcto del controlador a la hora de mover las manos sobre los sensores y de donde situar el instrumento para que no se produzcan problemas de interferencias con las señales que envían los ultrasonidos. Además, se proporciona un presupuesto del coste de los materiales, y otro del coste del desarrollo realizado por el ingeniero. ABSTRACT The aim of this Project is the creation of an economical MIDI controller that uses nowadays technology and that is based on the idea of the Theremin, a classical instrument conceived by Lev Serguéievich Termen. In order to accomplish this, the project has been divided into two sections: hardware and software. The hardware section explains why the microprocessor Arduino Uno has been chosen, sets out its technical specifications and the use of ultrasonic sensors. These sensors enable the user to interact with the controller through hand gestures like the Theremin. The assembly of the devices is exposed as well as the improvements made with the use of four of these sensors to offer more interactive capabilities with the MIDI controller. The Arduino singleboard programming that performs the measurements with the sensors and sends these measurements through the USB serial port is also explained here. The software section introduces Max/MSP programming environment as well as the plug in developed with this language that connects the MIDI controller with professional audio software (Ableton Live). The blocks that build the sensor controller plug in are explained in detail along with the way the Arduino delivers the information through the USB port into MIDI data. In addition, an explanation of the correct handling of the MIDI controller is given focusing on how the user should move his hands above the sensors and where to place the instrument to avoid interference problems with the signals sent. Also, a cost estimation of both materials and engineering is provided.

Sintetizador analógico en Arduino

Este proyecto consiste en el diseño y construcción de un sintetizador basado en el chip 6581 Sound Interface Device (SID). Este chip era el encargado de la generación de sonido en el Commodore 64, ordenador personal comercializado en 1982, y fue el primer sintetizador complejo construido para ordenador. El chip en cuestión es un sintetizador de tres voces, cada una de ellas capaz de generar cuatro diferentes formas de onda. Cada voz tiene control independiente de varios parámetros, permitiendo una relativamente amplia variedad de sonidos y efectos, muy útil para su uso en videojuegos. Además está dotado de un filtro programable para conseguir distintos timbres mediante síntesis sustractiva. El sintetizador se ha construido sobre Arduino, una plataforma de electrónica abierta concebida para la creación de prototipos, consistente en una placa de circuito impreso con un microcontrolador, programable desde un PC para que realice múltiples funciones (desde encender LEDs hasta controlar servomecanismos en robótica, procesado y transmisión de datos, etc.). El sintetizador es controlable vía MIDI, por ejemplo, desde un teclado de piano. A través de MIDI recibe información tal como qué notas debe tocar, o los valores de los parámetros del SID que modifican las propiedades del sonido. Además, toda esa información también la puede recibir de un PC mediante una conexión USB. Se han construido dos versiones del sintetizador: una versión “hardware”, que utiliza el SID para la generación de sonido, y otra “software”, que reemplaza el SID por un emulador, es decir, un programa que se comporta (en la medida de lo posible) de la misma manera que el SID. El emulador se ha implementado en un microcontrolador Atmega 168 de Atmel, el mismo que utiliza Arduino. ABSTRACT. This project consists on design and construction of a synthesizer which is based on chip 6581 Sound Interface Device (SID). This chip was used for sound generation on the Commodore 64, a home computer presented in 1982, and it was the first complex synthesizer built for computers. The chip is a three-voice synthesizer, each voice capable of generating four different waveforms. Each voice has independent control of several parameters, allowing a relatively wide variety of sounds and effects, very useful for its use on videogames. It also includes a programmable filter, allowing more timbre control via subtractive synthesis. The synthesizer has been built on Arduino, an open-source electronics prototyping platform that consists on a printed circuit board with a microcontroller, which is programmable with a computer to do several functions (lighting LEDs, controlling servomechanisms on robotics, data processing or transmission, etc.). The synthesizer is controlled via MIDI, in example, from a piano-type keyboard. It receives from MIDI information such as the notes that should be played or SID’s parameter values that modify the sound. It also can receive that information from a PC via USB connection. Two versions of the synthesizer have been built: a hardware one that uses the SID chip for sound generation, and a software one that replaces SID by an emulator, it is, a program that behaves (as far as possible) in the same way the SID would. The emulator is implemented on an Atmel’s Atmega 168 microcontroller, the same one that is used on Arduino.

Diseño de un sistema para el manejo a distancia de aeronaves construidas con arduino

El principal objetivo del proyecto es intentar reducir los costes de algunas de las operaciones de vigilancia llevadas a cabo por agencias o instituciones de seguridad. El proyecto consiste en diseñar y desarrollar un sistema informático que permita el manejo a distancia de un cuadricóptero a través de un ordenador, utilizando el teclado y visualizando las imágenes recibidas del módulo de la videocámara. Cada cuadricóptero estará compuesto de diferentes módulos y cada módulo tiene una funcionalidad característica. Se desarrollará un sistema de gestión de aeronaves para poder añadir nuevas unidades de cuadricópteros, así como un sistema de gestión de usuarios para administrar los usuarios en el sistema. Adicionalmente, se construirá un prototipo de cuadricóptero y se implementará su unidad controladora para poder realizar las pruebas del sistema desarrollado con ello. ---ABSTRACT---The aim of this project is to attempt to reduce the costs of some surveillance services offered by security agencies or institutions. The project consists in designing and developing a computer system to remotely control a drone or quad-copter through a computer, manipulating the drone through the keyboard and watching the images captured from the camera module. Each drone is built with one or more modules, and each module has its own functionality. Both new drones and new users can be added to the computer system through the drone management system and the user management system, respectively. Both of management systems are going to be developed. The project also includes the making of a quad-copter prototype and a controller unit implementation.

Functionally partitioned module-based programmable architecture for wireless base-band processing

A specialised reconfigurable architecture is targeted at wireless base-band processing. It is built to cater for multiple wireless standards. It has lower power consumption than the processor-based solution. It can be scaled to run in parallel for processing multiple channels. Test resources are embedded on the architecture and testing strategies are included. This architecture is functionally partitioned according to the common operations found in wireless standards, such as CRC error correction, convolution and interleaving. These modules are linked via Virtual Wire Hardware modules and route-through switch matrices. Data can be processed in any order through this interconnect structure. Virtual Wire ensures the same flexibility as normal interconnects, but the area occupied and the number of switches needed is reduced. The testing algorithm scans all possible paths within the interconnection network exhaustively and searches for faults in the processing modules. The testing algorithm starts by scanning the externally addressable memory space and testing the master controller. The controller then tests every switch in the route-through switch matrix by making loops from the shared memory to each of the switches. The local switch matrix is also tested in the same way. Next the local memory is scanned. Finally, pre-defined test vectors are loaded into local memory to check the processing modules. This paper compares various base-band processing solutions. It describes the proposed platform and its implementation. It outlines the test resources and algorithm. It concludes with the mapping of Bluetooth and GSM base-band onto the platform.

Test strategies on functionally partitioned module-based programmable architecture for base-band processing

A specialised reconfigurable architecture for telecommunication base-band processing is augmented with testing resources. The routing network is linked via virtual wire hardware modules to reduce the area occupied by connecting buses. The number of switches within the routing matrices is also minimised, which increases throughput without sacrificing flexibility. The testing algorithm was developed to systematically search for faults in the processing modules and the flexible high-speed routing network within the architecture. The testing algorithm starts by scanning the externally addressable memory space and testing the master controller. The controller then tests every switch in the route-through switch matrix by making loops from the shared memory to each of the switches. The local switch matrix is also tested in the same way. Next the local memory is scanned. Finally, pre-defined test vectors are loaded into local memory to check the processing modules. This algorithm scans all possible paths within the interconnection network exhaustively and reports all faults. Strategies can be inserted to bypass minor faults

REAL TIME FUZZY CONTROLLER FOR QUADROTOR STABILITY CONTROL

In this report, we develop an intelligent adaptive neuro-fuzzy controller by using adaptive neuro fuzzy inference system (ANFIS) techniques. We begin by starting with a standard proportional-derivative (PD) controller and use the PD controller data to train the ANFIS system to develop a fuzzy controller. We then propose and validate a method to implement this control strategy on commercial off-the-shelf (COTS) hardware. An analysis is made into the choice of filters for attitude estimation. These choices are limited by the complexity of the filter and the computing ability and memory constraints of the micro-controller. Simplified Kalman filters are found to be good at estimation of attitude given the above constraints. Using model based design techniques, the models are implemented on an embedded system. This enables the deployment of fuzzy controllers on enthusiast-grade controllers. We evaluate the feasibility of the proposed control strategy in a model-in-the-loop simulation. We then propose a rapid prototyping strategy, allowing us to deploy these control algorithms on a system consisting of a combination of an ARM-based microcontroller and two Arduino-based controllers. We then use a combination of the code generation capabilities within MATLAB/Simulink in combination with multiple open-source projects in order to deploy code to an ARM CortexM4 based controller board. We also evaluate this strategy on an ARM-A8 based board, and a much less powerful Arduino based flight controller. We conclude by proving the feasibility of fuzzy controllers on Commercial-off the shelf (COTS) hardware, we also point out the limitations in the current hardware and make suggestions for hardware that we think would be better suited for memory heavy controllers.