Buried screen-printed contacts for silicon solar cells

A Simple way to improve solar cell efficiency is to enhance the absorption of light and reduce the shading losses. One of the main objectives for the photovoltaic roadmap is the reduction of metalized area on the front side of solar cell by fin lines. Industrial solar cell production uses screen-printing of metal pastes with a limit in line width of 70-80 μm. This paper will show a combination of the technique of laser grooved buried contact (LGBC) and Screen-printing is able to improve in fine lines and higher aspect ratio. Laser grooving is a technique to bury the contact into the surface of silicon wafer. Metallization is normally done with electroless or electrolytic plating method, which a high cost. To decrease the relative cost, more complex manufacturing process was needed, therefore in this project the standard process of buried contact solar cells has been optimized in order to gain a laser grooved buried contact solar cell concept with less processing steps. The laser scribing process is set at the first step on raw mono-crystalline silicon wafer. And then the texturing etch; phosphorus diffusion and SiNx passivation process was needed once. While simultaneously optimizing the laser scribing process did to get better results on screen-printing process with fewer difficulties to fill the laser groove. This project has been done to make the whole production of buried contact solar cell with fewer steps and could present a cost effective opportunity to solar cell industries.

WTROPIC : um gerador automático de macro células CMOS acessível via WWW

Este trabalho apresenta a pesquisa e o desenvolvimento da ferramenta para geração automática de leiautes WTROPIC. O WTROPIC é uma ferramenta para a geração remota, acessível via WWW, de leiautes para circuitos CMOS adequada ao projeto FUCAS e ao ambiente CAVE. O WTROPIC foi concebido a partir de otimizações realizadas na versão 3 da ferramenta TROPIC. É mostrado também, como as otimizações no leiaute do TROPIC foram implementadas e como essas otimizações permitem ao WTROPIC cerca de 10% de redução da largura dos circuitos gerados em comparação ao TROPIC. Como o TROPIC, o WTROPIC é um gerador de macro células CMOS independente de biblioteca. Apresenta-se também, como a ferramenta WTROPIC foi integrada ao ambiente de concepção de circuitos CAVE, as mudanças propostas para metodologia de integração de ferramentas do CAVE que conduzem a uma melhora na qualidade de integração e a padronização das interfaces de usuário e como a síntese física de um leiaute pode ser então realizada remotamente. Dessa maneira, obteve-se uma ferramenta para a concepção de leiautes disponível a qualquer usuário com acesso a internet, mesmo que esse usuário não disponha de uma máquina com elevada capacidade de processamento, normalmente exigido por ferramentas de CAD.

Estimativa de capacitâncias e consumo de potência em circuitos combinacionais CMOS no nível lógico

Esta tese propõe o desenvolvimento de um método de estimativa de capacitâncias e de potência consumida nos circuitos combinacionais CMOS, no nível de portas lógicas. O objetivo do método é fazer uma previsão do consumo de potência do circuito na fase de projeto lógico, o que permitirá a aplicação de técnicas de redução de potência ou até alteração do projeto antes da geração do seu leiaute. A potência dinâmica consumida por circuitos CMOS depende dos seguintes parâmetros: tensão de alimentação, freqüência de operação, capacitâncias parasitas e atividades de comutação em cada nodo do circuito. A análise desenvolvida na Tese, propõe que a potência seja dividida em duas componentes. A primeira componente está relacionada ao consumo de potência devido às capacitâncias intrínsecas dos transistores, que por sua vez estão relacionadas às dimensões dos transistores. Estas capacitâncias intrínsecas são concentradas nos nodos externos das portas e manifestam-se em função das combinações dos vetores de entrada. A segunda componente está relacionada às interconexões entre as células do circuito. Para esta etapa utiliza-se a estimativa do comprimento médio das interconexões e as dimensões tecnológicas para estimar o consumo de potência. Este comprimento médio é estimado em função do número de transistores e fanout das várias redes do circuito. Na análise que trata das capacitâncias intrínsecas dos transistores os erros encontrados na estimativa da potência dissipada estão no máximo em torno de 11% quando comparados ao SPICE. Já na estimativa das interconexões a comparação feita entre capacitâncias de interconexões estimadas no nível lógico e capacitâncias de interconexões extraídas do leiaute apresentou erros menores que 10%.

Automatic layout generation of static CMOS circuits targeting delay and power

The evolution of integrated circuits technologies demands the development of new CAD tools. The traditional development of digital circuits at physical level is based in library of cells. These libraries of cells offer certain predictability of the electrical behavior of the design due to the previous characterization of the cells. Besides, different versions of each cell are required in such a way that delay and power consumption characteristics are taken into account, increasing the number of cells in a library. The automatic full custom layout generation is an alternative each time more important to cell based generation approaches. This strategy implements transistors and connections according patterns defined by algorithms. So, it is possible to implement any logic function avoiding the limitations of the library of cells. Tools of analysis and estimate must offer the predictability in automatic full custom layouts. These tools must be able to work with layout estimates and to generate information related to delay, power consumption and area occupation. This work includes the research of new methods of physical synthesis and the implementation of an automatic layout generation in which the cells are generated at the moment of the layout synthesis. The research investigates different strategies of elements disposition (transistors, contacts and connections) in a layout and their effects in the area occupation and circuit delay. The presented layout strategy applies delay optimization by the integration with a gate sizing technique. This is performed in such a way the folding method allows individual discrete sizing to transistors. The main characteristics of the proposed strategy are: power supply lines between rows, over the layout routing (channel routing is not used), circuit routing performed before layout generation and layout generation targeting delay reduction by the application of the sizing technique. The possibility to implement any logic function, without restrictions imposed by a library of cells, allows the circuit synthesis with optimization in the number of the transistors. This reduction in the number of transistors decreases the delay and power consumption, mainly the static power consumption in submicrometer circuits. Comparisons between the proposed strategy and other well-known methods are presented in such a way the proposed method is validated.

Design of boundary-scan testing in CMOS image sensors for industrial applications: internship repor

Tests on printed circuit boards and integrated circuits are widely used in industry,resulting in reduced design time and cost of a project. The functional and connectivity tests in this type of circuits soon began to be a concern for the manufacturers, leading to research for solutions that would allow a reliable, quick, cheap and universal solution. Initially, using test schemes were based on a set of needles that was connected to inputs and outputs of the integrated circuit board (bed-of-nails), to which signals were applied, in order to verify whether the circuit was according to the specifications and could be assembled in the production line. With the development of projects, circuit miniaturization, improvement of the production processes, improvement of the materials used, as well as the increase in the number of circuits, it was necessary to search for another solution. Thus Boundary-Scan Testing was developed which operates on the border of integrated circuits and allows testing the connectivity of the input and the output ports of a circuit. The Boundary-Scan Testing method was converted into a standard, in 1990, by the IEEE organization, being known as the IEEE 1149.1 Standard. Since then a large number of manufacturers have adopted this standard in their products. This master thesis has, as main objective: the design of Boundary-Scan Testing in an image sensor in CMOS technology, analyzing the standard requirements, the process used in the prototype production, developing the design and layout of Boundary-Scan and analyzing obtained results after production. Chapter 1 presents briefly the evolution of testing procedures used in industry, developments and applications of image sensors and the motivation for the use of architecture Boundary-Scan Testing. Chapter 2 explores the fundamentals of Boundary-Scan Testing and image sensors, starting with the Boundary-Scan architecture defined in the Standard, where functional blocks are analyzed. This understanding is necessary to implement the design on an image sensor. It also explains the architecture of image sensors currently used, focusing on sensors with a large number of inputs and outputs.Chapter 3 describes the design of the Boundary-Scan implemented and starts to analyse the design and functions of the prototype, the used software, the designs and simulations of the functional blocks of the Boundary-Scan implemented. Chapter 4 presents the layout process used based on the design developed on chapter 3, describing the software used for this purpose, the planning of the layout location (floorplan) and its dimensions, the layout of individual blocks, checks in terms of layout rules, the comparison with the final design and finally the simulation. Chapter 5 describes how the functional tests were performed to verify the design compliancy with the specifications of Standard IEEE 1149.1. These tests were focused on the application of signals to input and output ports of the produced prototype. Chapter 6 presents the conclusions that were taken throughout the execution of the work.

Effects of Silicon and Drought Stress on Tuber Yield and Leaf Biochemical Characteristics in Potato

Silicon has beneficial effects on many crops, mainly under biotic and abiotic stresses. Silicon can affect biochemical, physiological, and photosynthetic processes and, consequently, alleviates drought stress. However, the effects of Si on potato (Solanum tuberosum L.) plants under drought stress are still unknown. The objective of this study was to evaluate the effect of Si supply on some biochemical characteristics and yield of potato tubers, either exposed or not exposed to drought stress. The experiment was conducted in pots containing 50 dm(3) of a Typic Acrortox soil (33% clay, 4% silt, and 63% sand). The treatments consisted of the absence or presence of Si application (0 and 284.4 mg dm(-3)), through soil amelioration with dolomitic lime and Ca and Mg silicate, and in the absence or presence of water deficit (-0.020 MPa and -0.050 MPa soil water potential, respectively), with eight replications. Silicon application and water deficit resulted in the greatest Si concentration in potato leaves. Proline concentrations increased under lower water availability and higher Si availability in the soil, which indicates that Si may be associated with plant osmotic adjustment. Water deficit and Si application decreased total sugars and soluble proteins concentrations in the leaves. Silicon application reduced stalk lodging and increased mean tuber weight and, consequently, tuber yield, especially in the absence of water stress.

Nitrogen and silicon fertilization of upland rice

O silício não é considerado um elemento essencial para o crescimento e desenvolvimento das plantas, entretanto, sua absorção traz inúmeros benefícios, principalmente ao arroz, como aumento da espessura da parede celular, conferindo resistência mecânica a penetração de fungos, melhora o ângulo de abertura das folhas tornando-as mais eretas, diminuindo o auto-sombreamento e aumentando a resistência ao acamamento, especialmente sob altas doses de nitrogênio. O presente trabalho teve por objetivo avaliar os efeitos da adubação nitrogenada e silicatada nos componentes vegetativos, nos componentes da produção, na altura da planta e na produtividade da cultivar de arroz IAC 202. O experimento foi constituído da combinação de três doses de nitrogênio (5, 75 e 150 mg de N kg-1 de solo) aplicado na forma de uréia e quatro doses de silício (0, 200, 400 e 600 mg de SiO2 kg-1 de solo), aplicado na forma de silicato de cálcio. O delineamento experimental utilizado foi o inteiramente casualizado em esquema fatorial 3 ´ 4 (N = 5). A adubação nitrogenada aumentou o número de colmos e panículas por metro quadrado e o número total de espiguetas, refletindo na produtividade de grãos. O perfilhamento excessivo causado pela adubação nitrogenada inadequada causou redução na porcentagem de colmos férteis, na fertilidade das espiguetas e da massa de grãos. A adubação silicatada reduziu o número de espiguetas chochas por panícula e aumentou a massa de grãos sem, contudo, refletir na produtividade de grãos.

Silicon leaf application and physiological quality of white oat and wheat seeds

Plant nutrition can positively influence quality of seeds by improving plant tolerance to adverse climate. In this context, silicon is currently considered a micronutrient and it is beneficial to plant growth, especially Poaceaes such as white oat and wheat, thereby improving physiological quality of seeds. This study had the objective of evaluating the effects of silicon leaf application on plant tillering, silicon levels and physiological quality of white oat and wheat seeds besides establishing correlations between them. Two experiments were carried out in winter with white oat and wheat. The experimental design was the completely randomized block with eight replications. Treatments consisted of foliar application of silicon (0.8% of soluble silicon, as stabilized orthosilicic acid) and a control (with no application). Silicon levels in leaves were determined at flowering whereas the number of plants and panicles/spikes per area was counted right before harvest. Seed quality was evaluated right after harvest through mass, germination and vigor tests. Data was submitted to variance analysis and means were compared by the Tukey test at a probability level of 5%. Person's linear correlation test was performed among silicon level in plants, tillering and seed quality data. Silicon leaf application increases root and total length of white oat seedlings as an effect of higher Si level in leaves. Silicon leaf application increases mass of wheat seeds without affecting germination or vigor.

Seed germination and seedling development of white oat affected by silicon and phosphorus fertilization

Os fertilizantes silicatados tem sido cada vez mais usados na agricultura devido a inúmeros benefícios, tais como correção da acidez de solos tropicais e efeitos positivos no desenvolvimento de gramíneas. A disponibilidade de nutrientes e a nutrição de plantas desempenham papel importante na produção de sementes e podem influenciar a qualidade fisiológica de sementes de aveia-branca (Avena sativa L.). Avaliou-se a germinação de sementes e o desenvolvimento de plântulas de aveia-branca em função da adubação com silício e fósforo. O delineamento experimental foi inteiramente casualizado, em esquema fatorial 2 x 4, com seis repetições. Os tratamentos consistiram de 20 e 200 mg dm-3 de P2O5, aplicados na forma de superfosfato triplo, combinados com 0, 150, 300 e 450 mg dm-3 de Si na forma de silicato de potássio. O experimento foi realizado em casa de vegetação, conduzindo-se sete plantas por vaso, com capacidade para 15 L de terra. As panículas foram colhidas e debulhadas manualmente e, as sementes, armazenadas em sacos de papel em condições normais de ambiente. As sementes foram avaliadas quanto ao teor de água, massa de sementes, germinação, condutividade elétrica, comprimento e massa da matéria seca de plântulas. Sementes de aveia-branca com qualidade superior são produzidas com 20 mg dm-3 de P2O5, independente da dose de Si. Sementes com maior germinação e vigor são obtidas com 300 e 450 mg dm-3 de K2SiO3, respectivamente. Os comprimentos da raiz e total das plântulas foram inferiores nas doses de Si até 300 kg ha-1, porém a dose de fósforo somente afetou o desenvolvimento das plântulas de maneira distinta quando aplicada junto com a maior dose de silício.

A multisampling time-domain CMOS imager with synchronous readout circuit

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Silicon carbide surface modification by nitrogen plasma expander

Silicon carbide (SiC) has been employed in many different fields such as ballistic armor, thermal coating, high performance mirror substrate, semiconductors devices, among other things. Plasma application over the silicon carbide ceramics is relatively recent and it is able to promote relevant superficial modifications. Plasma expander was used in this work which was supplied by nitrogen and switched by a capacitor bank. Nitrogen plasma was applied over ceramic samples for 20 minutes, in a total medium of 1440 plasma pulses. SiC ceramics were produced by uniaxial pressing method (40 MPa) associated to isostatic pressing (300 MPa) and sintered at 1950 degrees C under argon gas atmosphere. Silicon carbide (beta-sic - BF-12) supplied by HC-Starck and sintering additive (7.6% YAG - Yttrium Aluminum Garnet) were used in order to obtain the ceramics. Before and after the plasma application, the samples were characterized by SEM, AFM, contact angle and surface energy measurement.

Cutting forces in turning of gray cast iron using silicon nitride based cutting tool

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Winner-take-all circuit using CMOS technology

In this paper is presented an implementation of winner-take-all circuit using CMOS technology. In the proposed configuration the inputs are current and the outputs voltage. The simulation results show that the circuit can be a winner if its input is larger than the other by 2 mu A. The simulation also shows that the response time is 100ns at a 0.2pF load capacitance. To demonstrate the functionality of the proposed circuit, a two-input winner take all circuit was built and tested by using discrete CMOS transistor array (CD40071).

Low voltage four-quadrant current multiplier: An improved topology for n-well CMOS process

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

An algorithmic of analog-to-digital converter using current-mode and digital CMOS process

In this paper a new algorithmic of Analog-to-Digital Converter is presented. This new topology use the current-mode technique that allows a large dynamic range and can be implemented in digital CMOS process. The ADC proposed is very small and can handle high sampling rates. Simulation results using a 1.2um CMOS process show that an 8-b ADC can support a sampling rate of 50MHz.