100 Gb/s uncooled WDM system using conventional WDM components and advanced receiver signal processing

We demonstrate an uncooled WDM system using standard WDM components and receiver signal processing, with a different number of receivers to transmitters, to allow wide temperature drift of the transmitter lasers. A 100 Gb/s 8-wavelength demonstrator has been developed, which proves the feasibility of the approach over 25 km of SMF. © 2012 OSA.

100 Gb/s uncooled WDM system using conventional WDM components and advanced receiver signal processing

We demonstrate an uncooled WDM system using standard WDM components and receiver signal processing, with a different number of receivers to transmitters, to allow wide temperature drift of the transmitter lasers. A 100 Gb/s 8-wavelength demonstrator has been developed, which proves the feasibility of the approach over 25 km of SMF. © 2012 Optical Society of America.

High performance optical data links using hybrid CAP/QAM transmitter/receiver scheme

We experimentally demonstrate the first optical data link at 20Gb/s using hybrid CAP- 4/QAM-4 with transmission over 4.3km SSMF and a power penalty ~1.5dBo at BER=10-9. The hybrid CAP-4/QAM-4 link significantly outperforms a reference PAM-4 link. © OSA 2013.

Monolithic Integration of Light Emitting Diodes, Photodetector and Receiver Circuit in Standard CMOS Technology

A monolithic silicon CMOS optoelectronic integrated circuit (OEIC) is designed and fabricated with standard 0.35 mu m CMOS technology. This OEIC circuit consists of light emitting diodes (LED), silicon dioxide waveguide, photodiodes and receiver circuit. The silicon LED operates in reverse breakdown mode and can be turned on at 8.5V 10mA. The silicon dioxide waveguide is composed of multiple layers of silicon dioxide between different metals layers. A two PN-junctions photodetector composed of n-well/p-substrate junction and p(+) active implantation/n-well junction maximizes the depletion region width. The readout circuitry in pixels is exploited to handle as small as 0.1nA photocurrent. Simulation and testing results show that the optical emissions powers are about two orders higher than the low frequency detectivity of silicon CMOS photodetcctor and receiver circuit.

An integrated optical receiver in MS/RF CMOS process

A monolithically integrated optoelectronic receiver was realized utilizing a deep sub-micron MS/RF CMOS process. Novel photo-diode with STI and highspeed receiver circuit were designed. This OEIC takes advantage of several new features to improve the performance.

The application of parallel optical transmitter and receiver modules in communication subsystems

A new 12 channels parallel optical transmitter module in which a Vertical Cavity Surface Emitting Laser (VCSEL) has been selected as the optical source is capable of transmitting 37.5Gbps date over hundreds meters. A new 12 channels parallel optical receiver module in which a GaAs PIN (p-intrinsic-n-type) array has been selected as the optical receiver unit is capable of responding to 30Gbps date. A transmission system based on a 12 channels parallel optical transmitter module and a 12 channels parallel optical receiver module can be used as a 10Gbps STM-64 or an OC-192 optical transponder. The parallel optical modules and the parallel optical transmission system have passed the test in laboratory.

A 1Gb/s silicon photo-receiver in standard CMOS for 850-nm optical communication

A monolithic silicon CMOS optoelectronic integrated circuit (OEIC) was designed and fabricated with standard 0.6 mu m CMOS technology. This OEIC circuit consisted of an integrated double photodiode detector (DPD) and a preamplifier. The DPD detector exhibited high bandwidth by screening the bulk-generated diffusion carriers and suppressing the slow diffusion tail effect. The preamplifier exploited the regulated cascode (RGC) configuration as the input stage of receiver, thus isolating the influence of photodiode capacitance and input parasitic capacitance on bandwidth. Testing results showed that the bandwidth of OEIC was 700MHz, indicating the bit rate of 1Gb/s was achieved.

A direct-conversion mixer with DC-offset cancellation for IEEE 802.11a WLAN receiver

A DC-offset cancellation scheme in the 5GHz direct-conversion receiver compliant with IEEE 802.11a wireless LAN standard is described in this paper. It uses the analog feedback loop to eliminate the DC-offset at the output of the double-balanced mixer. The mixer has a simulation voltage conversion gain of IMB at 5.2GHz, noise figure of 9.67dB, IIP3 of 7.6dBm. The solution provides 39.1dB reduction according to the leakage value at LO and mixer load resistors, the additional noise figure added to mixer is less than 0.9dB, the added power dissipation is 0.1mW and was fabricated in 60GHz 0.35 mu m SiGe BiCMOS technology.

A CMOS front-end circuit for SONET OC-96 receiver

An optical receiver front-end for SONET OC-96 receivers was analyzed and designed in 0.18 mu m CMOS process. It consists of a transimpedance amplifier (TIA) and a limiting amplifier (LA). The TIA takes a fully differential configuration, and regulated cascode (RGC) input stage is implemented. The LA was realized by five cascaded identical gain stages with active inductor load. The TIA achieved 4.2GHz bandwidth for 0.5pF photodiode (PD) capacitance and 1.2k 0 transimpedance gain. The LA achieved 5.4GHz bandwidth and 29dB voltage gain. The optical sensitivity is -19dBm at 5-Gb/s for a bit-error rate of 10(-12), and it dissipates 45.5mW for I.8V supply.

一种提高车载单频GPS实时定位精度的方法

民用单频GPS接收机实时定位精度约为 1 0 0m。将民用单频GPS接收机装载到汽车上进行导航工作，如不用差分等方法，则其实时定位精度也只能为 1 0 0m。假设在车上另加测向测距装置，以此为基础，提出一种提高车载单频GPS接收机实时定位精度的算法。