Developments in amplitude-comparator techniques for distance relays

The paper reports the development of new amplitude-comparator techniques which allow the instantaneous comparison of the amplitude of the signals derived from primary line quantities. These techniques are used to derive a variety of impedance characteristics. The merits of the new relaying system are: the simple mode of the relay circuitry, the derivation of closed polar characteristics (i.e. quadrilateral) by a single measuring gate and sharp discontinuities in the polar characteristics. Design principles and circuit models in their schematic form are described and, in addition, a comprehensive theoretical basis for comparison is also presented. Dynamic test results are presented for a quadrilateral characteristic of potentially general application.

New possibilities in amplitude- and phase-comparison techniques for distance relays

The paper reports further work on the amplitude-comparison technique described by the same authors in a previous paper. This technique is extended to develop improved polar characteristics. Discontinuous polar characteristics, like directional parallelograms, are obtained by a single measuring gate with a simple mode of relay circuitry, whereas two measuring gates are required to provide a directional-quadrilateral characteristic of potentially general application. The paper also describes some new possibilities in phase-comparison methods for distance-protection schemes. Comparator models which effect the amplitude and phase comparison of the relaying signals are described in their schematic form. A comprehensive theoretical basis for comparison is also presented.

Composite instantaneous comparators basis for design and their transient performance

Principles of design of composite instantaneous comparators (a combination of amplitude- and phase- comparison techniques) are laid out to provide directional, directional-reactance, nonoffset-resistance and conductance characteristices. The respective signals provided by the voltage transformer and the current transformer are directly used as relaying signals without resorting to any form of mixing. Phase shifts required, are obtained by using magnetic ferrite cores in a novel manner. Sampling units employing a combination of ferrite cores and semiconductor devices provide highly reliable designs. Special attention is paid to the choice of relaying signals, to eliminate the need for any synchronisation or modification and to avoid `image¿ characteristics. These factors have resulted in a considerable simplification of the practical circuitry. A thyristor AND circuit is employed in dual comparator units to provide the final tripping, and leads to a circuit which is much less sensitive to extraneous signals than a single-thyristor unit.

Three-system and single-system static distance relays

Static distance relays employing semiconductor devices as their active elements offer many advantages over the conventional electromagnetic and rectifier relays. The paper describes single-system and three-system static distance relays, which depend for their operation on the instantaneous-comparison or `block-spike¿ scheme. Design principles and typical discriminating and logic circuits are described for the new relaying equipment. The relaying circuitry has been devised for obtaining uniform performance on all kinds of faults, by the use of two phase detectors¿one for multiphase faults and one for earth faults. The phase detector for multiphase faults provides an improved polar characteristic in the complex-impedance plane, which fits only around the fault area of a transmission line. The other features of the relay are: reliable pickup for close-in faults, least susceptibility to maloperation under power-swing conditions, and reduction in cost and panel space required. The operating characteristics of the relays, as expressed by accuracy/range charts, are also presented.

Gate Drive Card for High Power Three Phase PWM Converters

Gate driver is an integral part of every power converter, drives the power semiconductor devices and also provides protection for the switches against short-circuit events and over-voltages during shut down. Gate drive card for IGBTs and MOSFETs with basic features can be designed easily by making use of discrete electronic components. Gate driver ICs provides attractive features in a single package, which improves reliability and reduces effort of design engineers. Either case needs one or more isolated power supplies to drive each power semiconductor devices and provide isolation to the control circuitry from the power circuit. The primary emphasis is then to provide simplified and compact isolated power supplies to the gate drive card with the requisite isolation strength and which consumes less space, and for providing thermal protection to the power semiconductor modules for 3-� 3 wire or 4 wire inverters.

Dual-Stage Power Management Algorithms for Energy Harvesting Sensors

In this paper, we propose power management algorithms for maximizing the utility of energy harvesting sensors (EHS) that operate purely on the basis of energy harvested from the environment. In particular, we consider communication (i.e., transmission and reception) power management issues for EHS under an energy neutrality constraint. We also consider the fixed power loss effects of the circuitry, the battery inefficiency and its storage capacity, in the design of the algorithms. We propose a two-stage structure that exploits the inherent difference in the timescales at which the energy harvesting and channel fading processes evolve, without loss of optimality of the resulting solution. The outer stage schedules the power that can be used by an inner stage algorithm, so as to maximize the long term average utility and at the same time maintain energy neutrality. The inner stage optimizes the communication parameters to achieve maximum utility in the short-term, subject to the power constraint imposed by the outer stage. We optimize the algorithms for different transmission schemes such as the truncated channel inversion and retransmission strategies. The performance of the algorithms is illustrated via simulations using solar irradiance data, and for the case of Rayleigh fading channels. The results demonstrate the significant performance benefits that can be obtained using the proposed power management algorithms compared to the energy efficient (optimum when there is no storage) and the uniform power consumption (optimum when the battery has infinite capacity and is perfectly efficient) approaches.

A low-noise low-power noise-adaptive neural amplifier in 0.13um CMOS technology

Chronic recording of neural signals is indispensable in designing efficient brain machine interfaces and in elucidating human neurophysiology. The advent of multichannel microelectrode arrays has driven the need for electronics to record neural signals from many neurons. The dynamic range of the system is limited by background system noise which varies over time. We propose a neural amplifier in UMC 130 nm, 2P8M CMOS technology. It can be biased adaptively from 200 nA to 2 uA, modulating input referred noise from 9.92 uV to 3.9 uV. We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. The amplifier can pass signal from 5 Hz to 7 kHz while rejecting input DC offsets at electrode-electrolyte interface. The bandwidth of the amplifier can be tuned by the pseudo-resistor for selectively recording low field potentials (LFP) or extra cellular action potentials (EAP). The amplifier achieves a mid-band voltage gain of 37 dB and minimizes the attenuation of the signal from neuron to the gate of the input transistor. It is used in fully differential configuration to reject noise of bias circuitry and to achieve high PSRR.

Photoluminescence decay rate engineering of CdSe quantum dots in ensemble arrays embedded with gold nano-antennae

We discuss experimental results on the ability to significantly tune the photoluminescence decay rates of CdSe quantum dots embedded in an ordered template, using lightly doped small gold nanoparticles (nano-antennae), of relatively low optical efficiency. We observe both enhancement and quenching of photoluminescence intensity of the quantum dots varying monotonically with increasing volume fraction of added gold nanoparticles, with respect to undoped quantum dot arrays. However, the corresponding variation in lifetime of photoluminescence spectra decay shows a hitherto unobserved, non-monotonic variation with gold nanoparticle doping. We also demonstrate that Purcell effect is quite effective for the larger (5 nm) gold nano-antenna leading to more than four times enhanced radiative rate at spectral resonance, for largest doping and about 1.75 times enhancement for off-resonance. Significantly for spectral off-resonance samples, we could simultaneously engineer reduction of non-radiative decay rate along with increase of radiative decay rate. Non-radiative decay dominates the system for the smaller (2 nm) gold nano-antenna setting the limit on how small these plasmonic nano-antennae could be to be effective in engineering significant enhancement in radiative decay rate and, hence, the overall quantum efficiency of quantum dot based hybrid photonic assemblies.

Design Of Start-up Power Circuit For Control Power Supplies With Wide Input Voltage Variation

This paper presents the design of a start up power circuit for a control power supply (CPS) which feeds power to the sub-systems of High Power Converters (HPC). The sub-systems such as gate drive card, annunciation card, protection and delay card etc; needs to be provided power for the operation of a HPC. The control power supply (CPS) is designed to operate over a wide range of input voltage from 90Vac to 270Vac. The CPS output supplies power at a desired voltage of Vout =24V to the auxiliary sub-systems of the HPC. During the starting, the power supply to the control circuitry of CPS in turn, is obtained using a separate start-up power supply. This paper discusses the various design issues of the start-up power circuit to ensure that start-up and shut down of the CPS occurs reliably. The CPS also maintains the power factor close to unity and low total harmonic distortion in input current. The paper also provides design details of gate drive circuits employed for the CPS as well as the design of on-board power supply for the CPS. Index terms: control power supply, start-up power supply, DSFC, pre-regulator

Time-Based All-Digital Technique for Analog Built-in Self-Test

A scheme for built-in self-test of analog signals with minimal area overhead for measuring on-chip voltages in an all-digital manner is presented. The method is well suited for a distributed architecture, where the routing of analog signals over long paths is minimized. A clock is routed serially to the sampling heads placed at the nodes of analog test voltages. This sampling head present at each test node, which consists of a pair of delay cells and a pair of flip-flops, locally converts the test voltage to a skew between a pair of subsampled signals, thus giving rise to as many subsampled signal pairs as the number of nodes. To measure a certain analog voltage, the corresponding subsampled signal pair is fed to a delay measurement unit to measure the skew between this pair. The concept is validated by designing a test chip in a UMC 130-nm CMOS process. Sub-millivolt accuracy for static signals is demonstrated for a measurement time of a few seconds, and an effective number of bits of 5.29 is demonstrated for low-bandwidth signals in the absence of sample-and-hold circuitry.

Throwing light on platinized carbon nanostructured composites for hydrogen generation

In the present study, we have synthesised carbon nanoparticles (CNPs) through a relatively simple process using a hydrocarbon precursor. These synthesised CNPs in the form of elongated spherules and/or agglomerates of 30-55 nm were further used as a support to anchor platinum nanoparticles. The broad light absorption (300-700 nm) and a facile charge transfer property of CNPs in addition to the plasmonic property of Pt make these platinized carbon nanostructures (CNPs/Pt) a promising candidate in photocatalytic water splitting. The photocatalytic activity was evaluated using ethanol as the sacrificial donor. The photocatalyst has shown remarkable activity for hydrogen production under UV-visible light while retaining its stability for nearly 70 h. The broadband absorption of CNPs, along with the Surface Plasmon Resonance (SPR) effect of PtNPs singly and in composites has pronounced influence on the photocatalytic activity, which has not been explored earlier. The steady rate of hydrogen was observed to be 20 mu mol h(-1) with an exceptional cumulative hydrogen yield of 32.16 mmol h(-1) g(-1) observed for CNPs/Pt, which is significantly higher than that reported for carbon-based systems.

Medium-Voltage Drive for Induction Machine With Multilevel Dodecagonal Voltage Space Vectors With Symmetric Triangles

Multilevel inverters with dodecagonal (12-sided polygon) voltage space vector structure have advantages, such as complete elimination of fifth and seventh harmonics, reduction in electromagnetic interference, reduction in device voltage ratings, reduction of switching frequency, extension of linear modulation range, etc., making it a viable option for high-power medium-voltage drives. This paper proposes two power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles (for the first time) with minimum number of dc-link power supplies and floating capacitor H-bridges. The first power topology is composed of two hybrid cascaded five-level inverters connected to either side of an open-end winding induction machine. Each inverter consists of a three-level neutral-point-clamped inverter, which is cascaded with an isolated H-bridge making it a five-level inverter. The second topology is for a normal induction motor. Both of these circuit topologies have inherent capacitor balancing for floating H-bridges for all modulation indexes, including transient operations. The proposed topologies do not require any precharging circuitry for startup. A simple pulsewidth modulation timing calculation method for space vector modulation is also presented in this paper. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any offline computation, lookup tables, or angle computation. Experimental results for steady-state operation and transient operation are also presented to validate the proposed concept.

Energy Efficient Memory Decoder Design for Ultra-Low Voltage Systems

This paper presents a low energy memory decoder architecture for ultra-low-voltage systems containing multiple voltage domains. Due to limitations in scalability of memory supply voltages, these systems typically contain a core operating at subthreshold voltages and memories operating at a higher voltage. This difference in voltage provides a timing slack on the memory path as the core supply is scaled. The paper analyzes the feasibility and trade-offs in utilizing this timing slack to operate a greater section of memory decoder circuitry at the lower supply. A 256x16-bit SRAM interface has been designed in UMC 65nm low-leakage process to evaluate the above technique with the core and memory operating at 280 mV and 500 mV respectively. The technique provides a reduction of up to 20% in energy/cycle of the row decoder without any penalty in area and system-delay.

A Time-based Low Voltage Body Temperature Monitoring Unit

A neonatal temperature monitoring system operating in subthreshold regime that utilizes time mode signal processing is presented. Resistance deviations in a thermistor due to temperature variations are converted to delay variations that are subsequently quantized by a Delay measurement unit (DMU). The DMU does away with the need for any analog circuitry and is synthesizable entirely from digital logic. An FPGA implementation of the system demonstrates the viability of employing time mode signal processing, and measured results show that temperature resolution better than 0.1 degrees C can be achieved using this approach.

Event-triggered Sampling and Reconstruction of Sparse Real-valued Trigonometric Polynomials

We propose data acquisition from continuous-time signals belonging to the class of real-valued trigonometric polynomials using an event-triggered sampling paradigm. The sampling schemes proposed are: level crossing (LC), close to extrema LC, and extrema sampling. Analysis of robustness of these schemes to jitter, and bandpass additive gaussian noise is presented. In general these sampling schemes will result in non-uniformly spaced sample instants. We address the issue of signal reconstruction from the acquired data-set by imposing structure of sparsity on the signal model to circumvent the problem of gap and density constraints. The recovery performance is contrasted amongst the various schemes and with random sampling scheme. In the proposed approach, both sampling and reconstruction are non-linear operations, and in contrast to random sampling methodologies proposed in compressive sensing these techniques may be implemented in practice with low-power circuitry.