931 resultados para Extension taxonomy


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Novel technology dependent scaling parameters i.e. spacer to gradient ratio and effective channel length (Leff) are proposed for source/drain engineered DG MOSFET, and their significance in minimizing short channel effects (SCES) in high-k gate dielectrics is discussed in detail. Results show that a high-k dielectric should be associated with a higher spacer to gradient ratio to minimise SCEs The analytical model agrees with simulated data over the entire range of spacer widths, doping gradients, high-k gate dielectrics and effective channel lengths.

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Se propone un planteamiento teórico/conceptual para determinar si las relaciones interorganizativas e interpersonales de la netchain de las cooperativas agroalimentarias evolucionan hacia una learning netchain. Las propuestas del trabajo muestran que el mayor grado de asociacionismo y la mayor cooperación/colaboración vertical a lo largo de la cadena están positivamente relacionados con la posición horizontal de la empresa focal más cercana del consumidor final. Esto requiere una planificación y una resolución de problemas de manera conjunta, lo que está positivamente relacionado con el mayor flujo y diversidad de la información/conocimiento obtenido y diseminado a lo largo de la netchain. Al mismo tiempo se necesita desarrollar un contexto social en el que fluya la información/conocimiento y las nuevas ideas de manera informal y esto se logra con redes personales y, principalmente, profesionales y con redes internas y, principalmente, externas. Todo esto permitirá una mayor satisfacción de los socios de la cooperativa agroalimentaria y de sus distribuidores y una mayor intensidad en I+D, convirtiéndose la netchain de la cooperativa agroalimentaria, así, en una learning netchain.

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An extension of the Ye and Shreeve group contribution method [C. Ye, J.M. Shreeve, J. Phys. Chem. A 111 (2007) 1456–1461] for the estimation of densities of ionic liquids (ILs) is here proposed. The new version here presented allows the estimation of densities of ionic liquids in wide ranges of temperature and pressure using the previously proposed parameter table. Coefficients of new density correlation proposed were estimated using experimental densities of nine imidazolium-based ionic liquids. The new density correlation was tested against experimental densities available in literature for ionic liquids based on imidazolium, pyridinium, pyrrolidinium and phosphonium cations. Predicted densities are in good agreement with experimental literature data in a wide range of temperatures (273.15–393.15 K) and pressures (0.10–100 MPa). For imidazolium-based ILs, the mean percent deviation (MPD) is 0.45% and 1.49% for phosphonium-based ILs. A low MPD ranging from 0.41% to 1.57% was also observed for pyridinium and pyrrolidinium-based ILs.

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We construct a countable-dimensional Hausdorff locally convex topological vector space $E$ and a stratifiable closed linear subspace $F$ subset of $E$ such that any linear extension operator from $C_b(F)$ to $C_b(E)$ is unbounded (here $C_b(X)$ stands for the Banach space of continuous bounded real-valued functions on $X$).

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This article presents a novel classification of wavelet neural networks based on the orthogonality/non-orthogonality of neurons and the type of nonlinearity employed. On the basis of this classification different network types are studied and their characteristics illustrated by means of simple one-dimensional nonlinear examples. For multidimensional problems, which are affected by the curse of dimensionality, the idea of spherical wavelet functions is considered. The behaviour of these networks is also studied for modelling of a low-dimension map.

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A design methodology to optimise the ratio of maximum oscillation frequency to cutoff frequency, f(MAX)/f(T), in 60 nm FinFETs is presented. Results show that 25 to 60% improvement in f(MAX)/f(T) at drain currents of 20-300 mu A/mu m can be achieved in a non-overlap gate-source/drain architecture. The reported work provides new insights into the design and optimisation of nanoscale FinFETs for RF applications.

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The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A(vo)) and cut-off frequency (f(T)) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 mu A/mu m, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SIDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g(m)), transconductance-to-current ratio (g(m)/I-ds), Early voltage (V-EA), output conductance (g(ds)) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs. (C) 2007 Elsevier B.V. All rights reserved.

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In this letter, we propose a novel design methodology for engineering source/drain extension (SDE) regions to simultaneously improve intrinsic dc gain (A(vo)) and cutoff frequency (f(T)) of 25-nm gate-length FinFETs operated at low drain-current (I-ds = 10 mu A/mu m). SDE region optimization in 25-nm FinFETs results in exceptionally high values of Avo (similar to 45 dB) and f(T) (similar to 70 GHz), which is nearly 2.5 times greater when compared to devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient, and the spacer-to-gradient ratio on key analog figures of merit is examined in detail. This letter provides new opportunities for realizing future low-voltage/low-power analog design with nanoscale SDE-engineered FinFETs.

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In this paper, we propose for the first time, an analytical model for short channel effects in nanoscale source/drain extension region engineered double gate (DG) SOI MOSFETs. The impact of (i) lateral source/drain doping gradient (d), (ii) spacer width (s), (iii) spacer to doping gradient ratio (s/d) and (iv) silicon film thickness (T-si), on short channel effects - threshold voltage (V-th) and subthreshold slope (S), on-current (I-on), off-current (I-on) and I-on/I-off is extensively analysed by using the analytical model and 2D device simulations. The results of the analytical model confirm well with simulated data over the entire range of spacer widths, doping gradients and effective channel lengths. Results show that lateral source/drain doping gradient along with spacer width can not only effectively control short channel effects, thus presenting low off-current, but can also be optimised to achieve high values of on-currents. The present work provides valuable design insights in the performance of nanoscale DG Sol devices with optimal source/drain engineering and serves as a tool to optimise important device and technological parameters for 65 nm technology node and below. (c) 2006 Elsevier Ltd. All rights reserved.