An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process

This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

A low power integrated CMOS transmitter for BCI system

The prototype wafer of a low power integrated CMOS Transmitter for short-range biotelemetry application has been designed and fabricated, which is prospective to be implanted in the human brain to transfer the extracted neural information to the external computer. The transmitter consists of five parts, a bandgap current regulator, a ring oscillator, a buffer, a modulator and a power transistor. High integration and low power are the most distinct criteria for such an implantable integrated circuit. The post-simulation results show that under a 3.3 V power supply the transmitter provides 100.1 MHz half-wave sinusoid current signal to drive the off-chip antenna, the output peak current range is -0.155 mA similar to 1.250 mA, and on-chip static power dissipation is low to 0.374 mW. All the performances of the transmitter satisfy the demands of wireless real-time BCI system for neural signals recording and processing.

5.2 GHz variable-gain amplifier and power amplifier driver for WLAN IEEE 802.11a transmitter front-end

A 5.2 GHz variable-gain amplifier (VGA) and a power amplifier (PA) driver are designed for WLAN IEEE 802.11a monolithic RFIC. The VGA and the PA driver are implemented in a 50 GHz 0.35 μm SiGe BiCMOS technology and occupy 1.12×1.25 mm~2 die area. The VGA with effective temperature compensation is controlled by 5 bits and has a gain range of 34 dB. The PA driver with tuned loads utilizes a differential input, single-ended output topology, and the tuned loads resonate at 5.2 GHz. The maximum overall gain of the VGA and the PA driver is 29 dB with the output third-order intercept point (OIP3) of 11 dBm. The gain drift over the temperature varying from -30 to 85℃ converges within±3 dB. The total current consumption is 45 mA under a 2.85 V power supply.

H桥斩波电源的小信号数学模型及其数字化控制器的实现

A brief summary of H bridge non-isolated DC-DC converter and operation principles is presented in this paper. A small signal model of the ideal converter in continuous current mode is proposed and simulation results of the converter are given. The hardware structure of digital power supply controller based on TMS320F2808 MCU is introduced. 中文摘要：概括了加速器 H 桥非隔离式电源的运行原理与特点，在简化运行方式基础上建立了理想状态下电源连续工作模式的数学模型，并给出了仿真分析结果，介绍了基于 TMS320F2808MCU 实现的数字化电源控制器结构。

AD7690在高精度数字电源上的应用

This paper contains the performance , principles of AD7690 and application design based on TMS320F2808 MCU. AD7690 ’s characters of high speed and high precision satisfy the requirement s of accelerator digital power supply.中文摘要：介绍了 AD7690 的主要性能、 工作原理 ,给出了应用电路以及在 TMS320F2808 上的数字接口设计。AD7690 的高速、 高精度特点适合加速器高精度数字电源方案。

Kicker电源数字延迟线及低压监测系统设计

踢轨磁铁（Kicker）电源系统是HIRFL-CSR注入引出系统中实现快引出的一个关键元件，主要功能是为踢轨磁铁提供快脉冲励磁电流以产生所需要的快脉冲磁场。Kicker电源提供的是高电压大电流的快脉冲，电流脉冲上升沿和下降沿为150ns,脉冲宽度为650ns,其脉冲峰值电流为2700A，工作周期为10s-17s。因此及时监控Kicker电源闸流管的工作状况以及电流脉冲波形特性至关重要。本文针对踢轨磁铁（Kicker）电源的需要，进行了Kicker电源监测系统的设计，主要针对闸流管误漏导通检测、电流脉冲宽度过宽过窄检测、脉冲宽度测量及脉冲计数等功能提出了电路的工作原理，并设计了具体电路。系统输入端采用光纤接口，而输出端采用了PLC数字I/O接口。由于采用PLC接收监测电路板的信号来完成对Kicker电源的监控报警，基于此编写了相关PLC程序，并调试通过。该监测系统电路板已调试完成，可以很好地完成对Kicker电源系统较为全面的状态监测，方便地对Kicker电源系统状态进行监控。另外，为了解决Kicker电源系统脉冲同步的问题，以满足兰州重离子加速器冷却储存环（HIRFL-CSR）环踢轨磁铁（Kicker）电源对电流脉冲进行适当延迟的要求，还分别设计了ECL高速可程控数字延迟线电路系统和基于CPLD的数字延迟线系统，分析介绍了数字延迟线系统结构、工作原理及PCB版图设计等。ECL高速可程控数字延迟线电路已初步调试通过，而基于CPLD的数字延迟线系统已完成了程序编程及仿真工作，它克服了ECL数字延迟线不能实现零延迟的缺点，且可以通过修改VHDL程序来设置出更多位的可编程数字延迟线，方便灵活

Kicker电源数字延迟线及低压监测系统设计

踢轨磁铁（Kicker）电源系统是兰州重离子加速器冷却储存环（HIRFL-CSR）注入引出系统中实现快引出的一个关键元件，主要功能是为踢轨磁铁提供快脉冲励磁电流以产生所需要的快脉冲磁场。踢轨磁铁（Kicker）电源系统各触发脉冲是否同步关系到束流能否顺利注入引出以及有好的束流品质。基于此，本文介绍了基于CPLD-EPM1270T144的数字延迟线系统，以满足HIRFL-CSR踢轨磁铁（Kicker）电源对触发脉冲进行适当延迟的要求；分析介绍了数字延迟线系统结构、工作原理、PCB制版及系统调试。实际检验证明本设计通过修改VHDL程序来调节延迟时间能够方便灵活的完成Kicker电源系统对脉冲同步的要求，延迟精度达到10ns。另外，由于Kicker电源提供的是高电压大电流的快脉冲，电流脉冲上升沿和下降沿为150ns、脉冲宽度为650ns,其脉冲峰值电流为2700A、工作周期为10s-17s，因此及时监控Kicker电源闸流管的工作状况以及电流脉冲波形特性非常重要。基于此，本文还进行了Kicker电源监测系统的设计。该设计主要针对闸流管误漏导通检测、电流脉冲宽度过宽过窄检测、脉冲宽度测量及脉冲计数等功能提出了电路的系统结构、工作原理，并完成了程序编程、仿真及外围电路设计

基于CAN总线的物流拣选设备的设计

简要介绍了物流的发展现状 ,详细描述了基于CAN总线的物流拣选系统的结构、供电方式和参数设定方法 ,并为系统硬件设计中的电源转换、总线驱动和地址译码等公共电路以及总线控制器、电子标签和指示灯控制器等主要设备提供了设计方案 ,为系统软件设计中的C5 1编译、通信协议、命令类型和程序控制规划等问题给出了相应的解决方法 ,还与进口同类产品的性能和价格进行了比较

Resonant power conversion topologies for inductive charging of electrical vehicle batteries

This thesis is concerned with inductive charging of electric vehicle batteries. Rectified power form the 50/60 Hz utility feeds a dc-ac converter which delivers high-frequency ac power to the electric vehicle inductive coupling inlet. The inlet configuration has been defined by the Society of Automotive Engineers in Recommended Practice J-1773. This thesis studies converter topologies related to the series resonant converter. When coupled to the vehicle inlet, the frequency-controlled series-resonant converter results in a capacitively-filtered series-parallel LCLC (SP-LCLC) resonant converter topology with zero voltage switching and many other desirable features. A novel time-domain transformation analysis, termed Modal Analysis, is developed, using a state variable transformation, to analyze and characterize this multi-resonant fourth-orderconverter. Next, Fundamental Mode Approximation (FMA) Analysis, based on a voltage-source model of the load, and its novel extension, Rectifier-Compensated FMA (RCFMA) Analysis, are developed and applied to the SP-LCLC converter. The RCFMA Analysis is a simpler and more intuitive analysis than the Modal Analysis, and provides a relatively accurate closed-form solution for the converter behavior. Phase control of the SP-LCLC converter is investigated as a control option. FMA and RCFMA Analyses are used for detailed characterization. The analyses identify areas of operation, which are also validated experimentally, where it is advantageous to phase control the converter. A novel hybrid control scheme is proposed which integrates frequency and phase control and achieves reduced operating frequency range and improved partial-load efficiency. The phase-controlled SP-LCLC converter can also be configured with a parallel load and is an excellent option for the application. The resulting topology implements soft-switching over the entire load range and has high full-load and partial-load efficiencies. RCFMA Analysis is used to analyze and characterize the new converter topology, and good correlation is shown with experimental results. Finally, a novel single-stage power-factor-corrected ac-dc converter is introduced, which uses the current-source characteristic of the SP-LCLC topology to provide power factor correction over a wide output power range from zero to full load. This converter exhibits all the advantageous characteristics of its dc-dc counterpart, with a reduced parts count and cost. Simulation and experimental results verify the operation of the new converter.

Improved power-saving medium access protocol for IEEE 802.11e QoS-enabled wireless networks

The performance of a new pointer-based medium-access control protocol that was designed to significantly improve the energy efficiency of user terminals in quality-of-service-enabled wireless local area networks was analysed. The new protocol, pointer-controlled slot allocation and resynchronisation protocol (PCSARe), is based on the hybrid coordination function-controlled channel access mode of the IEEE 802.11e standard. PCSARe reduces energy consumption by removing the need for power-saving stations to remain awake for channel listening. Discrete event network simulations were performed to compare the performance of PCSARe with the non-automatic power save delivery (APSD) and scheduled-APSD power-saving modes of IEEE 802.11e. The simulation results show a demonstrable improvement in energy efficiency without significant reduction in performance when using PCSARe. For a wireless network consisting of an access point and eight stations in power-saving mode, the energy saving was up to 39% when using PCSARe instead of IEEE 802.11e non-APSD. The results also show that PCSARe offers significantly reduced uplink access delay over IEEE 802.11e non-APSD, while modestly improving the uplink throughput. Furthermore, although both had the same energy consumption, PCSARe gave a 25% reduction in downlink access delay compared with IEEE 802.11e S-APSD.

Universal power quality manager with a new control scheme

A new universal power quality manager is proposed. The proposal treats a number of power quality problems simultaneously. The universal manager comprises a combined series and shunt three-phase PWM controlled converters sharing a common DC link. A control scheme based on fuzzy logic is introduced and the general features of the design and operation processes are outlined. The performance of two configurations of the proposed power quality manager are compared in terms of a recently formulated unified power quality index. The validity and integrity of the proposed system is proved through computer simulated experiments

Low-power systolic array processor architecture for FSBM video motion estimation

A novel power-efficient systolic array architecture is proposed for full search block matching (FSBM) motion estimation, where the partial distortion elimination algorithm is used to dynamically switch off the computation of eliminated partial candidate blocks. The RTL-level simulation shows that the proposed architecture can reduce the power consumption of the computation part of the algorithm to about 60% of that of the conventional 2D systolic arrays.

In situ diagnostics and prognostics of solder fatigue in IGBT modules for electric vehicle drives

This paper proposes an in situ diagnostic and prognostic (D&P) technology to monitor the health condition of insulated gate bipolar transistors (IGBTs) used in EVs with a focus on the IGBTs' solder layer fatigue. IGBTs' thermal impedance and the junction temperature can be used as health indicators for through-life condition monitoring (CM) where the terminal characteristics are measured and the devices' internal temperature-sensitive parameters are employed as temperature sensors to estimate the junction temperature. An auxiliary power supply unit, which can be converted from the battery's 12-V dc supply, provides power to the in situ test circuits and CM data can be stored in the on-board data-logger for further offline analysis. The proposed method is experimentally validated on the developed test circuitry and also compared with finite-element thermoelectrical simulation. The test results from thermal cycling are also compared with acoustic microscope and thermal images. The developed circuitry is proved to be effective to detect solder fatigue while each IGBT in the converter can be examined sequentially during red-light stopping or services. The D&P circuitry can utilize existing on-board hardware and be embedded in the IGBT's gate drive unit.

An Architecture of a Multi-Agent System for SCADA - Dealing With Uncertainty, Plans and Actions

This paper presents a multi-agent system approach to address the difficulties encountered in traditional SCADA systems deployed in critical environments such as electrical power generation, transmission and distribution. The approach models uncertainty and combines multiple sources of uncertain information to deliver robust plan selection. We examine the approach in the context of a simplified power supply/demand scenario using a residential grid connected solar system and consider the challenges of modelling and reasoning with
uncertain sensor information in this environment. We discuss examples of plans and actions required for sensing, establish and discuss the effect of uncertainty on such systems and investigate different uncertainty theories and how they can fuse uncertain information from multiple sources for effective decision making in
such a complex system.