Improvements in Efficiency of Surface Potential Computation for Independent DG MOSFET

A robust numerical solution of the input voltage equations (IVEs) for the independent-double-gate metal-oxide-semiconductor field-effect transistor requires root bracketing methods (RBMs) instead of the commonly used Newton-Raphson (NR) technique due to the presence of nonremovable discontinuity and singularity. In this brief, we do an exhaustive study of the different RBMs available in the literature and propose a single derivative-free RBM that could be applied to both trigonometric and hyperbolic IVEs and offers faster convergence than the earlier proposed hybrid NR-Ridders algorithm. We also propose some adjustments to the solution space for the trigonometric IVE that leads to a further reduction of the computation time. The improvement of computational efficiency is demonstrated to be about 60% for trigonometric IVE and about 15% for hyperbolic IVE, by implementing the proposed algorithm in a commercial circuit simulator through the Verilog-A interface and simulating a variety of circuit blocks such as ring oscillator, ripple adder, and twisted ring counter.

Structural, electrical and dielectric properties of sputtered TiO2 films for Al/TiO2/Si capacitors

Metal-oxide semiconductor capacitors based on titanium dioxide (TiO2) gate dielectrics were prepared by RF magnetron sputtering technique. The deposited films were post-annealed at temperatures in the range 773-1173 K in air for 1 hour. The effect of annealing temperature on the structural properties of TiO2 films was investigated by X-ray diffraction and Raman spectroscopy, the surface morphology was studied by atomic force microscopy (AFM) and the electrical properties of Al/TiO2/p-Si structure were measured recording capacitance-voltage and current-voltage characteristics. The as-deposited films and the films annealed at temperatures lower than 773 K formed in the anatase phase, while those annealed at temperatures higher than 973 K were made of mixtures of the rutile and anatase phases. FTIR analysis revealed that, in the case of films annealed at 1173 K, an interfacial layer had formed, thereby reducing the dielectric constant. The dielectric constant of the as-deposited films was 14 and increased from 25 to 50 with increases in the annealing temperature from 773 to 973 K. The leakage current density of as-deposited films was 1.7 x 10(-5) and decreased from 4.7 X 10(-6) to 3.5 x 10(-9) A/cm(2) with increases in the annealing temperature from 773 to 1173 K. The electrical conduction in the Al/TiO2/p-Si structures was studied on the basis of the plots of Schottky emission, Poole-Frenkel emission and Fowler-Nordheim tunnelling. The effect of structural changes on the current-voltage and capacitance-voltage characteristics of Al/TiO2/p-Si capacitors was also discussed.

Effect of post-deposition annealing on composition and electrical properties of dc reactive magnetron sputtered Al2O3 thin films

We have investigated the effect of post- deposition annealing on the composition and electrical properties of alumina (Al2O3) thin films. Al2O3 were deposited on n-type Si < 100 >. substrates by dc reactive magnetron sputtering. The films were subjected to post- deposition annealing at 623, 823 and 1023 K in vacuum. X-ray photoelectron spectroscopy results revealed that the composition improved with post- deposition annealing, and the film annealed at 1023 K became stoichiometric with an O/Al atomic ratio of 1.49. Al/Al2O3/Si metal-oxide-semiconductor (MOS) structures were then fabricated, and a correlation between the dielectric constant epsilon(r) and interface charge density Q(i) with annealing conditions were studied. The dielectric constant of the Al2O3 thin films increased to 9.8 with post- deposition annealing matching the bulk value, whereas the oxide charge density decreased to 3.11 x 10(11) cm(-2.) Studies on current-voltage IV characteristics indicated ohmic and Schottky type of conduction at lower electric fields (<0.16 MV cm(-1)) and space charge limited conduction at higher electric fields.

Effect of film thickness and annealing on optical properties of TiO2 thin films and electrical characterization of MOS capacitors

Titanium dioxide (TiO2) thin films were deposited on glass and silicon (100) substrates by the sol-gel method. The influence of film thickness and annealing temperature on optical transmittance/reflectance of TiO2 films was studied. TiO2 films were used to fabricate metal-oxide-semiconductor capacitors. The capacitance-voltage (C-V), dissipation-voltage (D-V) and current-voltage (I-V) characteristics were studied at different annealing temperatures and the dielectric constant, current density and resistivity were estimated. The loss tangent (dissipation) increased with increase of annealing temperature.

Growth of TiO2 Films by RF Magnetron Sputtering for MOS Gate Dielectrics: Influence of Substrate Temperature

Titanium dioxide thin films were deposited by RF reactive magnetron sputtering technique on p-type silicon(100) substrates held at temperatures in the range 303-673 K. The influence of substrate temperature on the core level binding energies, chemical bonding configuration, crystallographic structure and dielectric properties was investigated. X-ray photoelectron spectroscopy studies and Fourier transform infrared transmittance data confirmed the formation of stoichiometric films with anatase phase at a substrate temperature of 673 K. The films formed at 303 K were nanocrystalline with amorphous matrix while those deposited at 673 K were transformed in to crystalline phase and growth of grains in pyramidal like structure as confirmed by X-ray diffraction and atomic force microscopy respectively. Metal-oxide-semiconductor capacitors were fabricated with the configuration of Al/TiO2/Si structures. The current voltage, capacitance voltage and conductance voltage characteristics were studied to understand the electrical conduction and dielectric properties of the MOS devices. The leakage current density (at gate voltage of 2 V) decreased from 2.2 x 10(-6) to 1.7 x 10(-7) A/cm(2), the interface trap density decreased from 1.2 x 10(13) to 2.1 x 10(12) cm(-2) eV(-1) and the dielectric constant increased from 14 to 36 with increase of substrate temperature from 303 to 673 K.

High performance sol-gel spin-coated titanium dioxide dielectric based MOS structures

High-kappa TiO2 thin films have been fabricated using cost effective sol-gel and spin-coating technique on p-Si (100) wafer. Plasma activation process was used for better adhesion between TiO2 films and Si. The influence of annealing temperature on the structure-electrical properties of titania films were investigated in detail. Both XRD and Raman studies indicate that the anatase phase crystallizes at 400 degrees C, retaining its structural integrity up to 1000 degrees C. The thickness of the deposited films did not vary significantly with the annealing temperature, although the refractive index and the RMS roughness enhanced considerably, accompanied by a decrease in porosity. For electrical measurements, the films were integrated in metal-oxide-semiconductor (MOS) structure. The electrical measurements evoke a temperature dependent dielectric constant with low leakage current density. The Capacitance-voltage (C-V) characteristics of the films annealed at 400 degrees C exhibited a high value of dielectric constant (similar to 34). Further, frequency dependent C-V measurements showed a huge dispersion in accumulation capacitance due to the presence of TiO2/Si interface states and dielectric polarization, was found to follow power law dependence on frequency (with exponent `s'=0.85). A low leakage current density of 3.6 x 10(-7) A/cm(2) at 1 V was observed for the films annealed at 600 degrees C. The results of structure-electrical properties suggest that the deposition of titania by wet chemical method is more attractive and cost-effective for production of high-kappa materials compared to other advanced deposition techniques such as sputtering, MBE, MOCVD and AID. The results also suggest that the high value of dielectric constant kappa obtained at low processing temperature expands its scope as a potential dielectric layer in MOS device technology. (C) 2015 Elsevier Ltd. All rights reserved.

Measuring the magnetic-field-dependent chemical potential of a low-density three-dimensional electron gas in n-GaAs and extracting its magnetic susceptibility

We report the magnetic-field-dependent shift of the electron chemical potential in bulk, n-type GaAs at room temperature. A transient voltage of similar to 100 mu V was measured across a Au-Al2O3-GaAs metal-oxide-semiconductor capacitor in a pulsed magnetic field of similar to 6 T. Several spurious voltages larger than the signal that had plagued earlier researchers performing similar experiments were carefully eliminated. The itinerant magnetic susceptibility of GaAs is extracted from the experimentally measured data for four different doping densities, including one as low as 5 x 10(15) cm(-3). Though the susceptibility in GaAs is dominated by Landau-Peierls diamagnetism, the experimental technique demonstrated can be a powerful tool for extracting the total free carrier magnetization of any electron system. The method is also virtually independent of the carrier concentration and is expected to work better in the nondegenerate limit. Such experiments had been successfully performed in two-dimensional electron gases at cryogenic temperatures. However, an unambiguous report on having observed this effect in any three-dimensional electron gas has been lacking. We highlight the 50 year old literature of various trials and discuss the key details of our experiment that were essential for its success. The technique can be used to unambiguously yield only the itinerant part of the magnetic susceptibility of complex materials such as magnetic semiconductors and hexaborides, and thus shed light on the origin of ferromagnetism in such systems.

Detection of quantum well induced single degenerate-transition-dipoles in ZnO nanorods

Quantifying and characterising atomic defects in nanocrystals is difficult and low-throughput using the existing methods such as high resolution transmission electron microscopy (HRTEM). In this article, using a defocused wide-field optical imaging technique, we demonstrate that a single ultrahigh-piezoelectric ZnO nanorod contains a single defect site. We model the observed dipole-emission patterns from optical imaging with a multi-dimensional dipole and find that the experimentally observed dipole pattern and model-calculated patterns are in excellent agreement. This agreement suggests the presence of vertically oriented degenerate-transition-dipoles in vertically aligned ZnO nanorods. The HRTEM of the ZnO nanorod shows the presence of a stacking fault, which generates a localised quantum well induced degenerate-transition-dipole. Finally, we elucidate that defocused wide-field imaging can be widely used to characterise defects in nanomaterials to answer many difficult questions concerning the performance of low-dimensional devices, such as in energy harvesting, advanced metal-oxide-semiconductor storage, and nanoelectromechanical and nanophotonic devices.

Low temperature solution processed high-kappa ZrO2 gate dielectrics for nanoelectonics

The high-kappa gate dielectrics, specifically amorphous films offer salient features such as exceptional mechanical flexibility, smooth surfaces and better uniformity associated with low leakage current density. In this work, similar to 35 nm thick amorphous ZrO2 films were deposited on silicon substrate at low temperature (300 degrees C, 1 h) from facile spin-coating method and characterized by various analytical techniques. The X-ray diffraction and X-ray photoelectron spectroscopy reveal the formation of amorphous phase ZrO2, while ellipsometry analysis together with the Atomic Force Microscope suggest the formation of dense film with surface roughness of 1.5 angstrom, respectively. The fabricated films were integrated in metal-oxide-semiconductor (MOS) structures to check the electrical capabilities. The oxide capacitance (C-ox), flat band capacitance (C-FB), flat band voltage (V-FB), dielectric constant (kappa) and oxide trapped charges (Q(ot)) extracted from high frequency (1 MHz) C-V curve are 186 pF, 104 pF, 0.37V, 15 and 2 x 10(-11) C, respectively. The small flat band voltage 0.37V, narrow hysteresis and very little frequency dispersion between 10 kHz-1 MHz suggest an excellent a-ZrO2/Si interface with very less trapped charges in the oxide. The films exhibit a low leakage current density 4.7 x 10(-9)A/cm(2) at 1V. In addition, the charge transport mechanism across the MOSC is analyzed and found to have a strong bias dependence. The space charge limited conduction mechanism is dominant in the high electric field region (1.3-5 V) due to the presence of traps, while the trap-supported tunneling is prevailed in the intermediate region (0.35-1.3 V). Low temperature solution processed ZrO2 thin films obtained are of high quality and find their importance as a potential dielectric layer on Si and polymer based flexible electronics. (C) 2016 Published by Elsevier B.V.

Critical investigation of high performance spin-coated high-kappa titania thin films based MOS capacitor

We report the tunable dielectric constant of titania films with low leakage current density. Titanium dioxide (TiO2) films of three different thicknesses (36, 63 and 91 nm) were deposited by the consecutive steps of solution preparation, spin-coating, drying, and firing at different temperatures. The problem of poor adhesion between Si substrate and TiO2 insulating layer was resolved by using the plasma activation process. The surface roughness was found to increase with increasing thickness and annealing temperature. The electrical investigation was carried out using metal-oxide-semiconductor structure. The flat band voltage (V-FB), oxide trapped charge (Q(ot)), dielectric constant (kappa) and equivalent oxide thicknesses are calculated from capacitance-voltage (C-V) curves. The C-V characteristics indicate a thickness dependent dielectric constant. The dielectric constant increases from 31 to 78 as thickness increases from 36 to 91 nm. In addition to that the dielectric constant was found to be annealing temperature and frequency dependent. The films having thickness 91 nm and annealed at 600 A degrees C shows the low leakage current density. Our study provides a broad insight of the processing parameters towards the use of titania as high-kappa insulating layer, which might be useful in Si and polymer based flexible devices.

Millisecond processing beyond chip technology: From electronics to photonics

There is a clear and increasing interest in short time annealing processing far below one second, i.e. the lower limit of Rapid Thermal Processing (RTP) called spike annealing. This was driven by the need of suppressing the so-called Transient Enhanced Diffusion in advanced boronimplanted shallow pn-junctions in silicon technology. Meanwhile the interest in flash lamp annealing (FLA) in the millisecond range spread out into other fields related to silicon technology and beyond. This paper reports on recent experiments regarding shallow junction engineering in germanium, annealing of ITO layers on glass and plastic foil to form an conductive layer as well as investigations which we did during the last years in the field of wide band gap semiconductor materials (SiC, ZnO). A more common feature evolving from our work was related to the modeling of wafer stress during millisecond thermal processing with flash lamps. Finally recent achievements in the field of silicon-based light emission basing on Metal-Oxide-Semiconductor Light Emitting Devices will be reported. © 2007 IEEE.

A fully integrated 660 MHz low-swing energy-recycling DC-DC converter

A fully integrated 0.18 μm DC-DC buck converter using a low-swing "stacked driver" configuration is reported in this paper. A high switching frequency of 660 MHz reduces filter components to fit on chip, but this suffers from high switching losses. These losses are reduced using: 1) low-swing drivers; 2) supply stacking; and 3) introducing a charge transfer path to deliver excess charge from the positive metal-oxide semiconductor drive chain to the load, thereby recycling the charge. The working prototype circuit converts 2.2 to 0.75-1.0 V at 40-55 mA. Design and simulation of an improved circuit is also included that further improves the efficiency by enhancing the charge recycling path, providing automated zero voltage switching (ZVS) operation, and synchronizing the half-swing gating signals. © 2009 IEEE.

Low on-resistance SOI dual-trench-gate MOSFET

A low specific on-resistance (R-{{\rm on}, {\rm sp}}) integrable silicon-on-insulator (SOI) MOSFET is proposed, and its mechanism is investigated by simulation. The SOI MOSFET features double trenches and dual gates (DTDG SOI): an oxide trench in the drift region, a buried gate inset in the oxide trench, and another trench gate (TG) extended to a buried oxide layer. First, the dual gates form dual conduction channels, and the extended gate widens the vertical conduction area; both of which sharply reduce R-{{\rm on}, {\rm sp}}. Second, the oxide trench folds the drift region in the vertical direction, resulting in a reduced device pitch and R-{{\rm on}, {\rm sp}}. Third, the oxide trench causes multidirectional depletion. This not only enhances the reduced surface field effect and thus reshapes the electric field distribution but also increases the drift doping concentration, leading to a reduced R-{{\rm on}, {\rm sp}} and an improved breakdown voltage (BV). Compared with a conventional SOI lateral Double-diffused metal oxide semiconductor (LDMOS), the DTDG MOSFET increases BV from 39 to 92 V at the same cell pitch or decreases R-{{\rm on}, { \rm sp}} by 77% at the same BV by simulation. Finally, the TG extended synchronously acts as an isolation trench between the high/low-voltage regions in a high-voltage integrated circuit, saving the chip area and simplifying the isolation process. © 2006 IEEE.

200-V lateral superjunction LIGBT on partial SOI

This letter presents a novel lateral superjunction lateral insulated-gate bipolar transistor (LIGBT) in partial silicon-on-insulator (SOI) technology in 0.18-μm partial-SOI (PSOI) high-voltage (HV) process. For an n-type superjunction LIGBT, the p-layer in the superjunction drift region not only helps in achieving uniform electric field distribution but also contributes to the on-state current. The superjunction LIGBT successfully achieves a breakdown voltage (BV) of 210 V with an R dson of 765 mΩ ̇ mm 2. It exhibits half the value of specific on-state resistance R dson and three times higher saturation current (I dsat) for the same BV, compared to a comparable lateral superjunction laterally diffused metal-oxide-semiconductor fabricated in the same technology. It also performs well in higher temperature dc operation with 38.8% increase in R dson at 175°C, compared to the room temperature without any degradation in latch-up performance. To realize this device, it only requires one additional mask layer into X-FAB 0.18-μm PSOI HV process. © 2012 IEEE.

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency. © 2012 Tan et al.